LPC2478FBD208,551 NXP Semiconductors, LPC2478FBD208,551 Datasheet
LPC2478FBD208,551
Specifications of LPC2478FBD208,551
935284069551
LPC2478FBD208-S
Available stocks
Related parts for LPC2478FBD208,551
LPC2478FBD208,551 Summary of contents
Page 1
ES_LPC2478 Errata sheet LPC2478 Rev. 6 — 1 March 2011 Document information Info Content Keywords LPC2478 errata Abstract This errata sheet describes both the known functional problems and any deviations from the electrical specifications known at the release date of ...
Page 2
... For sales office addresses, please send an email to: ES_LPC2478 Errata sheet Added ADC.1. The format of this errata sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. Added Ethernet.1 Added date code info for IRC.2 Added IRC.2 Added Rev D First version. ...
Page 3
... NXP Semiconductors 1. Product identification The LPC2478 devices typically have the following top-side marking: LPC2478xxx xxxxxxx xxYYWWR[x] The last/second to last letter in the third line (field ‘R’) will identify the device revision. This Errata Sheet covers the following revisions of the LPC2478: Table 1. ...
Page 4
... NXP Semiconductors 3. Functional problems detail 3.1 Ethernet.1: Ethernet TxConsumeIndex register does not update correctly after the first frame is sent Introduction: The transmit consume index register defines the descriptor that is going to be transmitted next by the hardware transmit process. After a frame has been transmitted hardware increments the index, wrapping the value to 0 once the value of TxDescriptorNumber has been reached ...
Page 5
... NXP Semiconductors 3.2 Core.1: Incorrect update of the Abort Link register in Thumb state Introduction: If the processor is in Thumb state and executing the code sequence STR, STMIA or PUSH followed relative load, and the STR, STMIA or PUSH is aborted, the PC is saved to the abort link register. ...
Page 6
... NXP Semiconductors 3.3 ADC.1: External sync inputs not operational Introduction: In software-controlled mode (BURST bit is 0), the 10-bit ADC can start conversion by using the following options in the A/D Control Register: Fig 1. A/D control register options Problem: The external start conversion feature, AD0CR:START = 0x2 or 0x3, may not work reliably and ADC external trigger edges on P2 ...
Page 7
... NXP Semiconductors 4. AC/DC deviations detail 4.1 IRC.1: Accuracy of the Internal RC oscillator (IRC) frequency may be outside of the 4 MHz +/ specification only at extreme temperatures Introduction: The device has a 4 MHz internal RC oscillator (IRC) which can be optionally used as the clock source for the Watch Dog Timer (WDT), and/or as the clock that drives the PLL and subsequently the CPU. The IRC frequency spec is 4 MHz +/ ...
Page 8
... NXP Semiconductors 4.2 IRC.2: Accuracy of the Internal RC Oscillator (IRC) frequency for devices only with date codes 0949 and before are outside of the 4 MHz +/ specification only at temperatures between 20 C and 40 C Introduction: The device has a 4 MHz internal RC oscillator (IRC) which can be optionally used as the clock source for the Watch Dog Timer (WDT), and/or as the clock that drives the PLL and subsequently the CPU. The IRC frequency spec is 4 MHz +/ ...
Page 9
... Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...
Page 10
... NXP Semiconductors 7. Contents 1 Product identification . . . . . . . . . . . . . . . . . . . . 3 2 Errata overview . . . . . . . . . . . . . . . . . . . . . . . . . 3 3 Functional problems detail . . . . . . . . . . . . . . . . 4 3.1 Ethernet.1: Ethernet TxConsumeIndex register does not update correctly after the first frame is sent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Introduction Problem Work-around 3.2 Core.1: Incorrect update of the Abort Link register in Thumb state . . . . . . . . . . . . . . . . . . . . . . . . . 5 Introduction Problem Conditions: ...