STM8S105C4T6 STMicroelectronics, STM8S105C4T6 Datasheet - Page 70

• Manufacturer Part Number: STM8S105C4T6
• Description: MCU 16KB FLASH MEM 16MHZ 48LQFP
• Manufacturer: STMicroelectronics
• Series: STM8Sr

Specifications of STM8S105C4T6

• Core Processor: STM8
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 38
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.95 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• Processor Series: STM8S10x
• Core: STM8
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 38
• Number Of Timers: 9
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWSTM8
• Development Tools By Supplier: STICE-SYS001
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 10 Channel
• For Use With: 497-10040 - EVAL KIT STM8S DISCOVERY497-10593 - KIT STARTER FOR STM8S207/8 SER497-5046 - KIT TOOL FOR ST7/UPSD/STR7 MCU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-8818

Electrical characteristics
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Symbol
Symbol
(1)
(2)
(3)
(4)
(5)
(6)
I
t
(1)
(2)
DD(R)
RESETBL
Data guaranteed by design, not tested in production.
t
Measured from interrupt event to interrupt vector fetch.
Configured by the REGAH bit in the CLK_ICKR register.
Configured by the AHALT bit in the FLASH_CR1 register.
Plus 1 LSI clock depending on synchronization.
Data guaranteed by design, not tested in production.
Characterized with all I/Os tied to V
WU(WFI)
Parameter
mode
= 2 x 1/f
Total current consumption and timing in forced reset state
Current consumption of on-chip peripherals
Subject to general operating conditions for V
HSI internal RC/f
Symbol
Parameter
I
I
Supply current in reset
state
Reset pin release to
vector fetch
DD(TIM1)
DD(TIM2)
Table 30: Total current consumption and timing in forced reset state
(3)
(2)
master
+ 7 x 1/f
Parameter
TIM1 supply current
TIM2 supply current
CPU
Conditions
CPU.
= f
Table 31: Peripheral current consumption
MASTER
SS
Conditions
V
V
.
DD
DD
DocID14771 Rev 10
= 16 MHz.
= 5 V
= 3.3 V
(1)
(1)
DD
and T
A
.
Typ.
230
115
Typ
Typ
500
400
Max
Max
150
STM8S105xx
(1)
(1)
Unit
Unit
µA
Unit
μA
μs