MCU 32KB FLASH EEPROM 32-VFQFPN

STM8S105K6U6

Manufacturer Part NumberSTM8S105K6U6
DescriptionMCU 32KB FLASH EEPROM 32-VFQFPN
ManufacturerSTMicroelectronics
SeriesSTM8S
STM8S105K6U6 datasheet
 

Specifications of STM8S105K6U6

Core ProcessorSTM8Core Size8-Bit
Speed16MHzConnectivityI²C, IrDA, LIN, SPI, UART/USART
PeripheralsBrown-out Detect/Reset, POR, PWM, WDTNumber Of I /o25
Program Memory Size32KB (32K x 8)Program Memory TypeFLASH
Eeprom Size1K x 8Ram Size2K x 8
Voltage - Supply (vcc/vdd)2.95 V ~ 5.5 VData ConvertersA/D 7x10b
Oscillator TypeInternalOperating Temperature-40°C ~ 85°C
Package / Case32-VFQFN, 32-VFQFPNProcessor SeriesSTM8S10x
CoreSTM8Data Bus Width8 bit
Data Ram Size2 KBInterface TypeI2C, SPI, UART
Maximum Clock Frequency16 MHzNumber Of Programmable I/os25
Number Of Timers8Maximum Operating Temperature+ 85 C
Mounting StyleSMD/SMT3rd Party Development ToolsEWSTM8
Development Tools By SupplierSTICE-SYS001Minimum Operating Temperature- 40 C
On-chip Adc10 bit, 7 ChannelFor Use With497-10040 - EVAL KIT STM8S DISCOVERY497-10593 - KIT STARTER FOR STM8S207/8 SER
Lead Free Status / RoHS StatusLead free / RoHS CompliantOther names497-10123
STM8S105K6U6
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Product overview
The UBC area remains write-protected during in-application programming. This means that
the MASS keys do not unlock the UBC area. It protects the memory used to store the boot
program, specific code libraries, reset and interrupt vectors, the reset routine and usually the
IAP and communication routines.
Medium density
Flash program memory
  (up to 32 Kbytes)
Read-out protection (ROP)
The read-out protection blocks reading and writing the Flash program memory and data
EEPROM memory in ICP mode (and debug mode). Once the read-out protection is activated,
any attempt to toggle its status triggers a global erase of the program and data memory. Even
if no protection can be considered as totally unbreakable, the feature provides a very high
level of protection for a general purpose microcontroller.
4.5
Clock controller
The clock controller distributes the system clock (f
to the core and the peripherals. It also manages clock gating for low power modes and ensures
clock robustness.
Features
Clock prescaler: To get the best compromise between speed and current consumption
the clock frequency to the CPU and peripherals can be adjusted by a programmable
prescaler.
Safe clock switching: Clock sources can be changed safely on the fly in run mode
through a configuration register. The clock signal is not switched until the new clock source
is ready. The design guarantees glitch-free switching.
Clock management: To reduce power consumption, the clock controller can stop the
clock to the core, individual peripherals or memory.
Master clock sources: Four different clock sources can be used to drive the master
clock:
-
1-16 MHz high-speed external crystal (HSE)
-
Up to 16 MHz high-speed user-external clock (HSE user-ext)
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Figure 2: Flash memory organisation
Data memory area ( 1 Kbyte)
Data
EEPROM
memory
Option bytes
UBC area
Remains write protected during IAP
Program memory area
Write access possible for IAP
MASTER
DocID14771 Rev 10
STM8S105xx
Programmable area
from 1 Kbyte
(2 first pages) up to
32 Kbytes
(1 page steps)
) coming from different oscillators