MCU 32KB FLASH EEPROM 32-VFQFPN

STM8S105K6U6

Manufacturer Part NumberSTM8S105K6U6
DescriptionMCU 32KB FLASH EEPROM 32-VFQFPN
ManufacturerSTMicroelectronics
SeriesSTM8S
STM8S105K6U6 datasheet
 


Specifications of STM8S105K6U6

Core ProcessorSTM8Core Size8-Bit
Speed16MHzConnectivityI²C, IrDA, LIN, SPI, UART/USART
PeripheralsBrown-out Detect/Reset, POR, PWM, WDTNumber Of I /o25
Program Memory Size32KB (32K x 8)Program Memory TypeFLASH
Eeprom Size1K x 8Ram Size2K x 8
Voltage - Supply (vcc/vdd)2.95 V ~ 5.5 VData ConvertersA/D 7x10b
Oscillator TypeInternalOperating Temperature-40°C ~ 85°C
Package / Case32-VFQFN, 32-VFQFPNProcessor SeriesSTM8S10x
CoreSTM8Data Bus Width8 bit
Data Ram Size2 KBInterface TypeI2C, SPI, UART
Maximum Clock Frequency16 MHzNumber Of Programmable I/os25
Number Of Timers8Maximum Operating Temperature+ 85 C
Mounting StyleSMD/SMT3rd Party Development ToolsEWSTM8
Development Tools By SupplierSTICE-SYS001Minimum Operating Temperature- 40 C
On-chip Adc10 bit, 7 ChannelFor Use With497-10040 - EVAL KIT STM8S DISCOVERY497-10593 - KIT STARTER FOR STM8S207/8 SER
Lead Free Status / RoHS StatusLead free / RoHS CompliantOther names497-10123
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STM8S105xx
Addr.
Option
Option
Option bits
name
byte no.
7
NOPT6
0x480C
Reserved
OPT7
0x480D
Reserved
Reserved
NOPT7
0x480E
Reserved
OPTBL
0x487E
Bootloader
BL[7:0]
NOPTBL
0x487F
NBL[7:0]
Option byte no.
OPT0
OPT1
OPT2
OPT3
6
5
4
3
Table 13: Option byte description
Description
ROP[7:0] Memory readout protection (ROP)
AAh: Enable readout protection (write access via SWIM protocol)
Note: Refer to the family reference manual (RM0016) section on
Flash/EEPROM memory readout protection for details.
UBC[7:0] User boot code area
0x00: no UBC, no write-protection
0x01: Page 0 to 1 defined as UBC, memory write-protected
0x02: Page 0 to 3 defined as UBC, memory write-protected
0x03: Page 0 to 4 defined as UBC, memory write-protected
...
0x3E: Pages 0 to 63 defined as UBC, memory write-protected
Other values: Reserved
Note: Refer to the family reference manual (RM0016) section on
Flash write protection for more details.
AFR[7:0]
Refer to following table for the alternate function remapping
decriptions of bits [7:2].
HSITRIM:High speed internal clock trimming register size
0: 3-bit trimming supported in CLK_HSITRIMR register
1: 4-bit trimming supported in CLK_HSITRIMR register
DocID14771 Rev 10
Option bytes
Factory
default
setting
2
1
0
FFh
00h
FFh
00h
FFh
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