MCU 32KB FLASH EEPROM 32-VFQFPN

STM8S105K6U6

Manufacturer Part NumberSTM8S105K6U6
DescriptionMCU 32KB FLASH EEPROM 32-VFQFPN
ManufacturerSTMicroelectronics
SeriesSTM8S
STM8S105K6U6 datasheet
 

Specifications of STM8S105K6U6

Core ProcessorSTM8Core Size8-Bit
Speed16MHzConnectivityI²C, IrDA, LIN, SPI, UART/USART
PeripheralsBrown-out Detect/Reset, POR, PWM, WDTNumber Of I /o25
Program Memory Size32KB (32K x 8)Program Memory TypeFLASH
Eeprom Size1K x 8Ram Size2K x 8
Voltage - Supply (vcc/vdd)2.95 V ~ 5.5 VData ConvertersA/D 7x10b
Oscillator TypeInternalOperating Temperature-40°C ~ 85°C
Package / Case32-VFQFN, 32-VFQFPNProcessor SeriesSTM8S10x
CoreSTM8Data Bus Width8 bit
Data Ram Size2 KBInterface TypeI2C, SPI, UART
Maximum Clock Frequency16 MHzNumber Of Programmable I/os25
Number Of Timers8Maximum Operating Temperature+ 85 C
Mounting StyleSMD/SMT3rd Party Development ToolsEWSTM8
Development Tools By SupplierSTICE-SYS001Minimum Operating Temperature- 40 C
On-chip Adc10 bit, 7 ChannelFor Use With497-10040 - EVAL KIT STM8S DISCOVERY497-10593 - KIT STARTER FOR STM8S207/8 SER
Lead Free Status / RoHS StatusLead free / RoHS CompliantOther names497-10123
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Page 96/127

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Electrical characteristics
Symbol
Parameter
t
START condition hold time
h(STA)
t
Repeated START condition
su(STA)
setup time
t
STOP condition setup time
su(STO)
t
STOP to START condition time
w(STO:STA)
(bus free)
C
Capacitive load for each bus line
b
(1)
f
, must be at least 8 MHz to achieve max fast I
MASTER
(2)
2
Data based on standard I
(3)
The maximum hold time of the start condition has only to be met if the interface does not stretch the
low time.
(4)
The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge
the undefined region of the falling edge of SCL.
Figure 44: Typical application with I
I²C bus
SDA
t f(SDA)
SCL
t w(SCLH)
1. Measurement points are made at CMOS levels: 0.3 x V
96/127
Standard mode I
(2)
Min
4.0
4.7
4.0
4.7
2
C speed (400kHz).
C protocol requirement, not tested in production.
V DD
V DD
S TART
t r(SDA)
t su(SDA)
t h(SDA)
t h(STA)
t w(SCLL)
t r(SCL)
t f(SCL)
DocID14771 Rev 10
STM8S105xx
2
2
(1)
C
Fast mode I
C
(2)
(2)
(2)
Max
Min
Max
0.6
0.6
0.6
1.3
400
400
2
(1)
C bus and timing diagram
STM8S105xx
SDA
SCL
S TART REPEATED
S TART
t su(STA)
t su(STA:STO)
S TOP
t su(STO)
ai15385b
and 0.7 x V
DD
DD
Unit
μs
μs
μs
μs
pF