STM8S105K4T6C STMicroelectronics, STM8S105K4T6C Datasheet - Page 96

• Manufacturer Part Number: STM8S105K4T6C
• Description: MCU 16KB FLASH MEM 16MHZ 32-LQFP
• Manufacturer: STMicroelectronics
• Series: STM8Sr

Specifications of STM8S105K4T6C

• Core Processor: STM8
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 25
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.95 V ~ 5.5 V
• Data Converters: A/D 7x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-LQFP
• Processor Series: STM8S10x
• Core: STM8
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 25
• Number Of Timers: 8
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWSTM8
• Development Tools By Supplier: STICE-SYS001
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 7 Channel
• A/d Bit Size: 10 bit
• A/d Channels Available: 7
• Height: 1.4 mm
• Length: 7 mm
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.95 V
• Width: 7 mm
• For Use With: 497-10040 - EVAL KIT STM8S DISCOVERY497-10593 - KIT STARTER FOR STM8S207/8 SER
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-8947; STM8S105K4T6C

Electrical characteristics
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Symbol
t
t
t
t
C
(1)
(2)
(3)
low time.
(4)
the undefined region of the falling edge of SCL.
w(STO:STA)
h(STA)
su(STA)
su(STO)
b
The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge
f
Data based on standard I
The maximum hold time of the start condition has only to be met if the interface does not stretch the
MASTER
, must be at least 8 MHz to achieve max fast I
Parameter
START condition hold time
Repeated START condition
setup time
STOP condition setup time
STOP to START condition time
(bus free)
Capacitive load for each bus line
1. Measurement points are made at CMOS levels: 0.3 x V
Figure 44: Typical application with I
t f(SDA)
SDA
SCL
I²C bus
t w(SCLH)
2
C protocol requirement, not tested in production.
S TART
t h(STA)
V DD
t r(SDA)
DocID14771 Rev 10
t r(SCL)
t w(SCLL)
V DD
Standard mode I
Min
4.0
4.7
4.0
4.7
t su(SDA)
(2)
2
C speed (400kHz).
t f(SCL)
t h(SDA)
Max
2
400
C bus and timing diagram
SCL
SDA
(2)
2
t su(STA)
C
DD
STM8S105xx
Fast mode I
Min
0.6
0.6
0.6
1.3
S TOP
S TART REPEATED
and 0.7 x V
(2)
t su(STO)
Max
400
t su(STA:STO)
2
DD
C
S TART
(1)
(2)
ai15385b
STM8S105xx
(1)
Unit
μs
μs
μs
μs
pF