Z8F0213PJ005SC Zilog, Z8F0213PJ005SC Datasheet
Z8F0213PJ005SC
Specifications of Z8F0213PJ005SC
Related parts for Z8F0213PJ005SC
Z8F0213PJ005SC Summary of contents
Page 1
... High-Performance 8-Bit Microcontrollers Z8 Encore! XP Series Product Specification PS024314-0308 ® Copyright © 2008 by Zilog , Inc. All rights reserved. www.zilog.com ® F0823 ...
Page 2
... TECHNOLOGY DESCRIBED HEREIN OR OTHERWISE. The information contained within this document has been verified according to the general principles of electrical and mechanical engineering. Z8, Z8 Encore!, Z8 Encore! XP, Z8 Encore! MC, Crimzon, eZ80, and ZNEO are trademarks or registered trademarks of Zilog, Inc. All other product or service names are the property of their respective owners. PS024314-0308 ...
Page 3
Revision History Each instance in Revision History reflects a change to this document from its previous revision. For more details, refer to the corresponding pages and appropriate links in the table below. Revision Date Level March 14 2008 December 13 ...
Page 4
Table of Contents Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 5
On-Chip Debugger Initiated Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Stop Mode Recovery . ...
Page 6
Interrupt Vectors and Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 7
Receiving Data using the Polled Method . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Receiving Data using the Interrupt-Driven Method . ...
Page 8
... Trim Bit Address 0001H—Reserved . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 Trim Bit Address 0002H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 Trim Bit Address 0003H—Reserved . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 Trim Bit Address 0004H—Reserved . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 Zilog Calibration Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 ADC Calibration Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 Serialization Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 Randomized Lot Identifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 On-Chip Debugger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 Architecture ...
Page 9
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 10
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 11
... Zilog microcontroller products based on the 8-bit eZ8 CPU core. Z8 Encore! XP F0823 Series products expand upon Zilog’s extensive line of 8-bit microcontrollers. The Flash in-circuit programming capability allows for faster development time and program changes in the field. The new eZ8 CPU is upward compatible with existing Z8 tions ...
Page 12
V to 3.6 V operating voltage • thirteen 5 V-tolerant input pins • 8-, 20-, and 28-pin packages • 0 °C to +70 °C and -40 °C to +105 °C for operating temperature ranges Part Selection ...
Page 13
Block Diagram Figure 1 on page 3 displays the block diagram of the architecture of Z8 Encore! XP F0823 Series devices. eZ8 CPU Memory Busses Register Bus Timers UART Comparator IrDA GPIO Figure 1. Z8 Encore! XP PS024314-0308 System Oscillator ...
Page 14
... CPU and Peripheral Overview eZ8 CPU Features The eZ8 CPU, Zilog’s latest 8-bit central processing unit (CPU), meets the continuing demand for faster and code-efficient microcontrollers. The eZ8 CPU executes a superset of the original Z8 • Direct register-to-register architecture allows each register to function as an accumulator, improving execution time and decreasing the required program memory. • ...
Page 15
Internal Precision Oscillator The internal precision oscillator (IPO trimmable clock source that requires no external components. 10-Bit Analog-to-Digital Converter The optional analog-to-digital converter (ADC) converts an analog input signal to a 10-bit binary number. The ADC accepts inputs ...
Page 16
Reset Controller ® Z8 Encore! XP time-out, STOP mode exit, or Voltage Brownout warning signal. The RESET pin is bidirectional, that is, it functions as reset source as well as a reset indicator. On-Chip Debugger Z8 Encore! XP F0823 Series ...
Page 17
Pin Description ® Z8 Encore! XP configurations. This chapter describes the signals and pin configurations available for each of the package styles. For information on physical package specifications, see aging on page 209. Available Packages Table 2 lists the package ...
Page 18
The pin configurations listed are preliminary and subject to change based on manufactur- ing limitations. PA0/T0IN/T0OUT/DBG PA1/T0OUT/ANA3/VREF/CLKIN PA2/RESET/DE0/T1OUT Figure 2. Z8F08x3, Z8F04x3, F02x3 and Z8F01x3 in 8-Pin SOIC, QFN/MLF-S, or PDIP Package* PB1/ANA1 PB2/ANA2 PB3/CLKIN/ANA3 PA0/T0IN/T0OUT PA1/T0OUT PA2/DE0 PA3/CTS0 PA4/RXD0 ...
Page 19
Analog input alternate functions (ANA) are not available on the Z8F0x13 devices. Note: Signal Descriptions Table 3 lists the Z8 Encore! XP for the specific package styles, see Table 3. Signal Descriptions Signal Mnemonic I/O Description General-Purpose I/O Ports ...
Page 20
Table 3. Signal Descriptions (Continued) Signal Mnemonic I/O Description Analog ANA[7:0] I Analog port. These signals are used as inputs to the ADC. The ANA0, ANA1, and ANA2 pins can also access the inputs and output of the integrated transimpedance ...
Page 21
Table 5 provides detailed information about the characteristics for each pin available on ® Z8 Encore! XP Note: All six I/O pins on the 8-pin packages are 5 V-tolerant (unless the pull-up devices are enabled). The column in packages only. ...
Page 22
Table 5. Pin Characteristics (8-Pin Devices) ) Symbol Reset Mnemonic Direction Direction PA0/DBG I/O I (but can change during reset if key sequence detected) PA1 I/O I RESET/ I/O I/O PA2 (defaults to RESET) PA[5:3] I/O I VDD N/A N/A ...
Page 23
... These three address spaces are covered briefly in the following subsections. For more detailed information regarding the eZ8 CPU and its address space, refer to eZ8 CPU Core User Manual (UM0128) available for download at www.zilog.com. Register File The Register File address space in the Z8 Encore! XP Register File is composed of two sections: control registers and general-purpose registers ...
Page 24
Encore! XP F0823 Series products. Table 6. Z8 Encore! XP F0823 Series Program Memory Maps Program Memory Address (Hex) Z8F0823 and Z8F0813 Products 0000–0001 0002–0003 0004–0005 0006–0007 0008–0037 0038–003D 003E–0FFF Z8F0423 and ...
Page 25
... F0823 Series does not use the eZ8 CPU’ Data Memory address to FE00H FF7FH Function Zilog Option Bits. Part Number. 20-character ASCII alphanumeric code Left justified and filled with FH. Reserved. Zilog Calibration Data. Reserved. ® Z8 Encore! XP F0823 Series Product Specification . When the Information Area access is Address Space 15 ...
Page 26
PS024314-0308 ® Z8 Encore! XP F0823 Series Product Specification Address Space 16 ...
Page 27
Register Map Table 8 lists the address map for the Register File of the Z8 Encore! XP devices. Not all devices and package styles in the Z8 Encore! XP F0823 Series support the ADC, or all GPIO ports. Consider registers ...
Page 28
Table 8. Register File Address Map (Continued) Address (Hex) Register Description F0C Timer 1 PWM High Byte F0D Timer 1 PWM Low Byte F0E Timer 1 Control 0 F0F Timer 1 Control 1 F10–F3F Reserved UART F40 UART0 Transmit Data ...
Page 29
Table 8. Register File Address Map (Continued) Address (Hex) Register Description F91–FBF Reserved Interrupt Controller FC0 Interrupt Request 0 FC1 IRQ0 Enable High Bit FC2 IRQ0 Enable Low Bit FC3 Interrupt Request 1 FC4 IRQ1 Enable High Bit FC5 IRQ1 ...
Page 30
Table 8. Register File Address Map (Continued) Address (Hex) Register Description FF2 Watchdog Timer Reload High Byte FF3 Watchdog Timer Reload Low Byte FF4–FF5 Reserved Trim Bit Control FF6 Trim Bit Address FF7 Trim Data Flash Memory Controller FF8 Flash ...
Page 31
Reset and Stop Mode Recovery The Reset Controller within the Z8 Encore! XP Mode Recovery operation and provides indication of low supply voltage conditions. In typical operation, the following events cause a Reset: • Power-On Reset (POR) • Voltage Brownout ...
Page 32
Table 9. Reset and Stop Mode Recovery Characteristics and Latency Reset Type Control Registers System Reset (as applicable) Reset Stop Mode Unaffected, except Recovery WDT_CTL and OSC_CTL registers During a System Reset or Stop Mode Recovery, the IPO requires 4 ...
Page 33
Table 10. Reset Sources and Resulting Reset Type Operating Mode Reset Source NORMAL or HALT Power-On Reset/Voltage modes Brownout Watchdog Timer time-out when configured for Reset RESET pin assertion OCD initiated Reset (OCDCTL[0] set to 1) STOP mode Power-On Reset/Voltage ...
Page 34
V POR V VBO Internal Precision Oscillator Internal RESET signal Note: Not to Scale Figure 5. Power-On Reset Operation Voltage Brownout Reset The devices in the Z8 Encore! XP F0823 Series provide low VBO protection. ...
Page 35
POR V VBO Program Execution WDT Clock System Clock Internal RESET signal Note: Not to Scale Figure 6. Voltage Brownout Reset Operation The POR level is greater than the VBO level by the specified ...
Page 36
A reset pulse three clock cycles in duration might trigger a reset; a pulse four cycles in duration always ...
Page 37
Following Stop Mode Recovery, the STOP bit in the Watchdog Timer Control Register is set to 1. actions. The section following the table provides more detailed information on each of the Stop Mode Recovery sources. Table 11. Stop ...
Page 38
Stop Mode Recovery Using the External RESET Pin When the Z8 Encore! XP F0823 Series device is in STOP mode and the external RESET pin is driven Low, a system reset occurs. Because of a glitch filter operating on the ...
Page 39
STOP—Stop Mode Recovery Indicator If this bit is set Stop Mode Recovery is occurred. If the STOP and WDT bits are both set to 1, the Stop Mode Recovery occurred because of a WDT time-out. If the ...
Page 40
PS024314-0308 ® Z8 Encore! XP F0823 Series Product Specification Reset and Stop Mode Recovery 30 ...
Page 41
Low-Power Modes ® Z8 Encore power reduction is provided by the STOP mode, in which nearly all device functions are powered down. The next lower level of power reduction is provided by the HALT mode, in which the ...
Page 42
HALT Mode Executing the eZ8 CPU’s powers down the CPU but leaves all other peripherals active. In HALT mode, the operating characteristics are: • Primary oscillator is enabled and continues to operate. • System clock is enabled and continues to ...
Page 43
This register is only reset during a Power-On Reset sequence. Other System Reset events Note: do not affect it. Table 13. Power Control Register 0 (PWRCTL0) BITS 7 6 Reserved Reserved FIELD 1 0 RESET R/W R/W R/W ADDR Reserved—Must ...
Page 44
PS024314-0308 ® Z8 Encore! XP F0823 Series Product Specification Low-Power Modes 34 ...
Page 45
General-Purpose Input/Output ® Z8 Encore! XP for general-purpose input/output (GPIO) operations. Each port contains control and data registers. The GPIO control registers determine data direction, open-drain, output drive current, programmable pull-ups, Stop Mode Recovery functionality, and alternate pin functions. Each ...
Page 46
Architecture Figure 7 displays a simplified block diagram of a GPIO port pin. In this figure, the ability to accommodate alternate functions and variable port current drive strength is not displayed. System Port Output Data Register DATA D Q Bus ...
Page 47
PA0 and PA6 contain two different timer functions, a timer input and a complementary timer output. Both of these functions require the same GPIO configuration, the selection between the two is based on the timer mode. For more details, see ...
Page 48
GPIO pin not present, the debug feature is disabled until/unless another reset event occurs. For more details, see Crystal Oscillator Override For systems using a crystal oscillator, PA0 and PA1 are used to connect ...
Page 49
Table 15. Port Alternate Function Mapping (Non 8-Pin Parts) Port Pin Mnemonic PA0 T0IN/T0OUT* Port A Reserved PA1 T0OUT Reserved PA2 DE0 Reserved PA3 CTS0 Reserved PA4 RXD0/IRRX0 Reserved PA5 TXD0/IRTX0 Reserved PA6 T1IN/T1OUT* Reserved PA7 T1OUT Reserved Note: Because ...
Page 50
Table 15. Port Alternate Function Mapping (Non 8-Pin Parts) (Continued) Port Pin Mnemonic PB0 Reserved Port B ANA0 PB1 Reserved ANA1 PB2 Reserved ANA2 PB3 CLKIN ANA3 PB4 Reserved ANA7 PB5 Reserved VREF* PB6 Reserved Reserved PB7 Reserved Reserved Note: ...
Page 51
Table 15. Port Alternate Function Mapping (Non 8-Pin Parts) (Continued) Port Pin Mnemonic PC0 Reserved Port C ANA4/CINP/LED Drive PC1 Reserved ANA5/CINN/ LED Drive PC2 Reserved ANA6/LED/ VREF* PC3 COUT LED PC4 Reserved LED PC5 Reserved LED PC6 Reserved LED ...
Page 52
Table 16. Port Alternate Function Mapping (8-Pin Parts) Port Pin Mnemonic PA0 T0IN Port A Reserved Reserved T0OUT PA1 T0OUT Reserved CLKIN Analog Functions* ADC Analog Input/VREF PA2 DE0 RESET T1OUT Reserved PA3 CTS0 COUT T1IN Analog Functions* ADC Analog ...
Page 53
GPIO Interrupts Many of the GPIO port pins are used as interrupt sources. Some port pins are configured to generate an interrupt request on either the rising edge or falling edge of the pin input signal. Other port pin interrupt ...
Page 54
Port A–C Address Registers The Port A–C Address registers select the GPIO Port functionality accessible through the Port A–C Control registers. The Port A–C Address and Control registers combine to provide access to all GPIO Port controls Table 18. Port ...
Page 55
Table 19. Port A–C Control Registers (PxCTL) BITS 7 6 FIELD RESET R/W R/W R/W ADDR PCTL[7:0]—Port Control The Port Control register provides access to all sub-registers that configure the GPIO Port operation. Port A–C Data Direction Sub-Registers The Port ...
Page 56
See GPIO Alternate Functions function associated with each port pin. Caution: Do not enable alternate functions for GPIO port pins for which there is no associated alternate function. Failure to follow this guideline can result in unpredictable operation. ...
Page 57
The drains are enabled for any output mode (unless overridden by the alternate function The drain of the associated pin is disabled (open-drain mode). Port A–C High Drive Enable Sub-Registers The Port A–C High Drive Enable ...
Page 58
PSMRE[7:0]—Port Stop Mode Recovery Source Enabled The Port pin is not configured as a Stop Mode Recovery source. Transitions on this pin during STOP mode do not initiate Stop Mode Recovery The Port pin is configured ...
Page 59
Table 26. Port A–C Alternate Function Set 1 Sub-Registers (PxAFS1) BITS 7 6 PAFS17 PAFS16 FIELD 00H (all ports of 20/28 pin devices); 04H (Port A of 8-pin device) RESET R/W R/W R/W If 07H in Port A–C Address Register, ...
Page 60
Table 28. Port A–C Input Data Registers (PxIN) BITS 7 6 PIN7 PIN6 FIELD X X RESET R R R/W ADDR PIN[7:0]—Port Input Data Sampled data from the corresponding port pin input Input data is logical 0 (Low) ...
Page 61
Table 30. LED Drive Enable (LEDEN) BITS 7 6 FIELD 0 0 RESET R/W R/W R/W ADDR LEDEN[7:0]—LED Drive Enable These bits determine which Port C pins are connected to an internal current sink Tristate the Port ...
Page 62
Table 32. LED Drive Level Low Register (LEDLVLL) BITS 7 6 FIELD 0 0 RESET R/W R/W R/W ADDR LEDLVLH[7:0]—LED Level High Bit {LEDLVLH, LEDLVLL} select one of four programmable current drive levels for each Port C pin ...
Page 63
... The eZ8 CPU supports both vectored and polled interrupt handling. For polled interrupts, the interrupt controller has no effect on operation. For more information on interrupt servicing by the eZ8 CPU, refer to eZ8 CPU Core User Manual (UM0128) available for download at www.zilog.com. Interrupt Vector Listing Table 33 lists all of the interrupts available in order of priority ...
Page 64
Table 33. Trap and Interrupt Vectors in Order of Priority Program Memory Priority Vector Address Interrupt or Trap Source Highest 0002H Reset (not an interrupt) 0004H Watchdog Timer (see 003AH Primary Oscillator Fail Trap (not an interrupt) 003CH Watchdog Timer ...
Page 65
Table 33. Trap and Interrupt Vectors in Order of Priority (Continued) Program Memory Priority Vector Address Interrupt or Trap Source Lowest 0036H Port C Pin 0, both input edges 0038H Reserved Architecture Figure 8 displays the interrupt controller block diagram. ...
Page 66
Writing the IRQE bit in the Interrupt Control register Interrupts are globally disabled by any of the following actions: • Execution of a Disable Interrupt • eZ8 CPU acknowledgement of an interrupt service request from the ...
Page 67
To avoid missing interrupts, use the following coding style to clear bits in the Interrupt Caution: Request 0 register: Good coding style that avoids lost interrupt requests: ANDX IRQ0, MASK Software Interrupt Assertion Program code generates interrupts directly. Writing a ...
Page 68
Interrupt Control Register Definitions For all interrupts other than the Watchdog Timer interrupt, the Primary Oscillator Fail Trap, and the Watchdog Timer Oscillator Fail Trap, the interrupt control registers enable individual interrupts, set interrupt priorities, and indicate interrupt requests. Interrupt ...
Page 69
Interrupt Request 1 Register The Interrupt Request 1 (IRQ1) register vectored and polled interrupts. When a request is presented to the interrupt controller, the corresponding bit in the IRQ1 register becomes 1. If interrupts are globally enabled (vectored interrupts), the ...
Page 70
Table 36. Interrupt Request 2 Register (IRQ2) BITS 7 6 Reserved FIELD 0 0 RESET R/W R/W R/W ADDR Reserved—Must be 0 PCxI—Port C Pin x Interrupt Request interrupt request is pending for GPIO Port C pin ...
Page 71
Reserved—Must be 0 T1ENH—Timer 1 Interrupt Request Enable High Bit T0ENH—Timer 0 Interrupt Request Enable High Bit U0RENH—UART 0 Receive Interrupt Request Enable High Bit U0TENH—UART 0 Transmit Interrupt Request Enable High Bit ADCENH—ADC Interrupt Request Enable High Bit Table ...
Page 72
Table 41. IRQ1 Enable High Bit Register (IRQ1ENH) BITS 7 6 PA7VENH PA6CENH PA5ENH FIELD 0 0 RESET R/W R/W R/W ADDR PA7VENH—Port A Bit[7] Interrupt Request Enable High Bit PA6CENH—Port A Bit[7] or Comparator Interrupt Request Enable High Bit ...
Page 73
Table 43. IRQ2 Enable and Priority Encoding (Continued) IRQ2ENH[x] IRQ2ENL[x] Priority 1 where x indicates the register bits from 0–7. Table 44. IRQ2 Enable High Bit Register (IRQ2ENH) BITS 7 6 Reserved FIELD 0 0 RESET R/W R/W R/W ADDR ...
Page 74
Table 46. Interrupt Edge Select Register (IRQES) BITS 7 6 IES7 IES6 FIELD 0 0 RESET R/W R/W R/W ADDR IESx—Interrupt Edge Select interrupt request is generated on the falling edge of the PAx input or ...
Page 75
Table 48. Interrupt Control Register (IRQCTL) BITS 7 6 IRQE FIELD 0 0 RESET R/W R R/W ADDR IRQE—Interrupt Request Enable This bit is set executing an instruction direct register write ...
Page 76
PS024314-0308 ® Z8 Encore! XP F0823 Series Product Specification Interrupt Controller 66 ...
Page 77
Timers ® Z8 Encore! XP used for timing, event counting, or generation of PWM signals. The timers’ features include: • 16-bit reload counter. • Programmable prescaler with prescale values from 1 to 128. • PWM output generation. • Capture and ...
Page 78
Operation The timers are 16-bit up-counters. Minimum time-out delay is set by loading the value into the Timer Reload High and Low Byte registers and setting the prescale value 0001H to 1. Maximum time-out delay is set by loading the ...
Page 79
Write to the Timer Control register to enable the timer and initiate counting. In ONE-SHOT mode, the system clock always provides the timer input. The timer period is given by the following equation: ONE-SHOT Mode Time-Out Period (s) CONTINUOUS ...
Page 80
COUNTER Mode In COUNTER mode, the timer counts input transitions from a GPIO port pin. The timer input is taken from the GPIO port pin Timer Input alternate function. The Timer Control register selects whether the count occurs on the ...
Page 81
COMPARATOR COUNTER Mode In COMPARATOR COUNTER mode, the timer counts input transitions from the analog comparator output. The TPOL bit in the Timer Control Register selects whether the count occurs on the rising edge or the falling edge of the ...
Page 82
PWM SINGLE OUTPUT Mode In PWM SINGLE OUTPUT mode, the timer outputs a PWM output signal through a GPIO port pin. The timer input is the system clock. The timer first counts up to the 16-bit PWM match value stored ...
Page 83
If an initial starting value other than registers, use the ONE-SHOT mode equation to determine the first PWM time-out period. If TPOL is set to 0, the ratio of the PWM output High time to the total period is represented ...
Page 84
Set the initial logic level (High or Low) and PWM High/Low transition for the – Timer Output alternate function 2. Write to the Timer High and Low Byte registers to set the starting count value (typically 0001H reset in PWM ...
Page 85
Timer Input signal. When the Capture event occurs, an interrupt is generated and the timer continues counting. The interrupt is because of an input capture event. The timer continues counting up to the 16-bit Reload value stored in ...
Page 86
Timer High and Low Byte registers is reset to and counting resumes. The interrupt is because of an input capture event Capture event occurs, the timer counts up to the 16-bit ...
Page 87
Timer Output pin changes state (from Low to High or from High to Low) upon Compare. If the Timer reaches the steps below to configure a timer for COMPARE mode and to initiate ...
Page 88
Follow the steps below to configure a timer for GATED mode and to initiate the count: 1. Write to the Timer Control register to: Disable the timer – Configure the timer for Gated mode – Set the prescale value – ...
Page 89
Configure the timer for CAPTURE/COMPARE mode – Set the prescale value – Set the Capture edge (rising or falling) for the Timer Input – 2. Write to the Timer High and Low Byte registers to set the starting count value ...
Page 90
Timer Control Register Definitions Timer 0–1 High and Low Byte Registers The Timer 0–1 High and Low Byte (TxH and TxL) registers contain the current 16-bit timer count value. When the timer is enabled, a read from TxH causes the ...
Page 91
In COMPARE mode, the Timer Reload High and Low Byte registers store the 16-bit Compare value. Table 51. Timer 0–1 Reload High Byte Register (TxRH) BITS 7 6 FIELD 1 1 RESET R/W R/W R/W ADDR Table 52. Timer 0–1 ...
Page 92
Table 54. Timer 0–1 PWM Low Byte Register (TxPWML) BITS 7 6 FIELD 0 0 RESET R/W R/W R/W ADDR PWMH and PWML—Pulse-Width Modulator High and Low Bytes These two bytes, {PWMH[7:0], PWML[7:0]}, form a 16-bit value that is compared ...
Page 93
Timer Interrupt occurs on all defined Reload, Compare and Input Events 10 = Timer Interrupt only on defined Input Capture/Deassertion Events 11 = Timer Interrupt only on defined Reload/Compare Events Reserved—Must be 0 PWMD—PWM Delay value This field ...
Page 94
ONE-SHOT Mode When the timer is disabled, the Timer Output signal is set to the value of this bit. When the timer is enabled, the Timer Output signal is complemented upon timer Reload. CONTINUOUS Mode When the timer is disabled, ...
Page 95
CAPTURE/COMPARE Mode 0 = Counting is started on the first rising edge of the Timer Input signal. The current count is captured on subsequent rising edges of the Timer Input signal Counting is started on the first falling ...
Page 96
Divide by 4 011 = Divide by 8 100 = Divide by 16 101 = Divide by 32 110 = Divide by 64 111 = Divide by 128 TMODE—Timer mode This field along with the TMODEHI bit in ...
Page 97
Watchdog Timer The Watchdog Timer (WDT) protects against corrupt or unreliable software, power faults, and other system-level problems which can place Z8 Encore! XP into unsuitable operating states. The features of Watchdog Timer include: • On-chip RC oscillator • A ...
Page 98
Watchdog Timer Refresh When first enabled, the WDT is loaded with the value in the Watchdog Timer Reload registers. The Watchdog Timer counts down to executed by the eZ8 CPU. Execution of the reloaded with the WDT Reload value stored ...
Page 99
WDT Reset in NORMAL Operation If configured to generate a Reset when a time-out occurs, the Watchdog Timer forces the device into the System Reset state. The WDT status bit in the Watchdog Timer Control register is set to 1. ...
Page 100
Watchdog Timer Reload Byte registers (WDTU, WDTH, and WDTL) to allow changes to the time-out period. These write operations to the WDTCTL register address produce no effect on the bits in the WDTCTL register. The locking mechanism prevents spurious writes ...
Page 101
Table 59. Watchdog Timer Reload Upper Byte Register (WDTU) BITS 7 6 FIELD RESET R/W* R/W* R/W ADDR R/W*—Read returns the current WDT count value. Write sets the appropriate Reload Value. WDTU—WDT Reload Upper Byte Most significant byte (MSB), Bits[23:16], ...
Page 102
PS024314-0308 ® Z8 Encore! XP F0823 Series Product Specification Watchdog Timer 92 ...
Page 103
Universal Asynchronous Receiver/Transmitter The universal asynchronous receiver/transmitter (UART full-duplex communication channel capable of handling asynchronous data transfers. The UART uses a single 8-bit data mode with selectable parity. The features of UART include: • 8-bit asynchronous data transfer ...
Page 104
Parity Checker RXD Receive Shifter Receive Data Register System Bus Transmit Data Register Transmit Shift TXD Register Parity Generator CTS DE Operation Data Format The UART always transmits and receives data in an 8-bit data format, least-significant bit (lsb) first. ...
Page 105
Idle State of Line lsb 1 Start Bit0 0 Figure 11. UART Asynchronous Data Format without Parity Idle State of Line lsb 1 Start Bit0 Bit1 0 Figure 12. UART Asynchronous Data Format with Parity Transmitting Data using the Polled ...
Page 106
Check the TDRE bit in the UART Status 0 register to determine if the Transmit Data register is empty (indicated by a 1). If empty, continue to register is full (indicated by a 0), continue to monitor the TDRE ...
Page 107
The UART is now configured for interrupt-driven data transmission. Because the UART Transmit Data register is empty, an interrupt is generated immediately. When the UART Transmit interrupt is detected, the associated interrupt service routine (ISR) performs the following: 1. Write ...
Page 108
Receiving Data using the Interrupt-Driven Method The UART Receiver interrupt indicates the availability of new data (as well as error conditions). Follow the steps below to configure the UART receiver for interrupt-driven operation: 1. Write to the UART Baud Rate ...
Page 109
Clears the UART Receiver interrupt in the applicable Interrupt Request register. 4. Executes the more data. Clear To Send (CTS) Operation The CTS pin, if enabled by the CTSE bit of the UART Control 0 register, performs flow control ...
Page 110
In general, the address compare feature reduces the load on the CPU, because it does not require access to the UART when it receives data ...
Page 111
External Driver Enable The UART provides a Driver Enable (DE) signal for off-chip bus transceivers. This feature reduces the software overhead associated with using a GPIO pin to control the transceiver when communicating on a multi-transceiver bus, such as RS-485. ...
Page 112
Transmitter Interrupts The transmitter generates a single interrupt when the Transmit Data Register Empty bit (TDRE) is set to 1. This indicates that the transmitter is ready to accept new data for transmission. The TDRE interrupt occurs after the Transmit ...
Page 113
Read Data Figure 15. UART Receiver Interrupt Service Routine Flow Baud Rate Generator Interrupts If the Baud Rate Generator (BRG) interrupt enable is set, the UART Receiver interrupt asserts when the UART Baud Rate Generator reloads. This condition allows the ...
Page 114
UART. The UART data rate is calculated using the following equation: UART Data Rate (bits/s) When the UART is disabled, the Baud Rate Generator functions as a basic 16-bit ...
Page 115
UART Receive Data Register Data bytes received through the RXDx pin are stored in the UART Receive Data register (Table 63). The read-only UART Receive Data register shares a Register File address with the Write-only UART Transmit Data register. Table ...
Page 116
UART Receive Data register has not been read. If the RDA bit is reset to 0, reading the UART Receive Data register clears this bit overrun error occurred overrun error occurred ...
Page 117
Reserved—R/W bits must be 0 during writes; 0 when read. NEWFRM—Status bit denoting the start of a new frame. Reading the UART Receive Data register resets this bit The current byte is not the first data ...
Page 118
PSEL—Parity Select 0 = Even parity is transmitted and expected on all received data 1 = Odd parity is transmitted and expected on all received data SBRK—Send Break This bit pauses or breaks data transmission. Sending a break interrupts any ...
Page 119
Send the multiprocessor bit location of the data stream (data byte Send the multiprocessor bit location of the data stream (address byte) DEPOL—Driver Enable Polarity signal is ...
Page 120
Table 68. UART Address Compare Register (U0ADDR) BITS 7 6 FIELD 0 0 RESET R/W R/W R/W ADDR COMP_ADDR—Compare Address This 8-bit value is compared to incoming address bytes. UART Baud Rate High and Low Byte Registers The UART Baud ...
Page 121
The baud rate error relative to the acceptable baud rate is calculated using the following equation: UART Baud Rate Error (%) For reliable communication, the UART baud rate error must never exceed five percent. Table 71 provides information about data ...
Page 122
PS024314-0308 ® Z8 Encore! XP F0823 Series Product Specification Universal Asynchronous Receiver/Transmitter 112 ...
Page 123
Infrared Encoder/Decoder ® Z8 Encore! XP UART with Infrared Encoder/Decoder (Endec). The Infrared Endec is integrated with an on-chip UART to allow easy communication between the Z8 Encore! XP and IrDA Phys- ical Layer Specification, Version 1.3-compliant infrared transceivers. Infrared ...
Page 124
Endec, and passed to the UART. Communication is half-duplex, which means simultaneous data transmission and reception is not allowed. The baud rate is set by the UART’s baud rate generator and supports IrDA standard baud rates from 9600 baud to ...
Page 125
Receiving IrDA Data Data received from the infrared transceiver using the IR_RXD signal through the RXD pin is decoded by the Infrared Endec and passed to the UART. The UART’s baud rate clock is used by the Infrared Endec to ...
Page 126
If an incoming pulse is detected inside this window this process is repeated. If the incoming data is a logical 1 (no pulse), ...
Page 127
Analog-to-Digital Converter The Analog-to-Digital Converter (ADC) converts an analog input signal to its digital representation. The features of this sigma-delta ADC include: • 10-bit resolution • Eight single-ended analog input sources are multiplexed with general-purpose I/O ports • Interrupt upon ...
Page 128
Internal Voltage Vrefsel Reference Generator Ref Input 11 ADC Data Analog Input ADC IRQ Figure 19. Analog-to-Digital Converter Block Diagram Operation Data Format The output of the ADC is an 11-bit, signed, two’s complement digital value. The output generally ...
Page 129
As a result, the final value is an 11- bit number. Automatic Powerdown If the ADC is idle (no conversions in progress) for 160 consecutive system clock cycles, portions of ...
Page 130
When the conversion is complete, the ADC control logic performs the following operations: 11-bit two’s-complement result written to {ADCD_H[7:0], ADCD_L[7:5]}. – CEN resets indicate the conversion is complete. – the ADC remains idle for ...
Page 131
... If you have precision references available, its own external calibration can be performed, storing the values into Flash themselves. PS024314-0308 F0823 Series ADC can be factory calibrated for offset error and gain ® Z8 Encore! XP F0823 Series Product Specification Zilog Calibration Data on page 147. Analog-to-Digital Converter 121 ...
Page 132
Software Compensation Procedure The value read from the ADC high and low byte registers are uncompensated. The user mode software must apply gain and offset correction to this uncompensated value for maximum accuracy. The following formula yields the compensated value: ...
Page 133
REFSELL—Voltage Reference Level Select Low Bit; in conjunction with the High bit (REFSELH) in ADC Control/Status Register voltage reference; the following details the effects of {REFSELH, REFSELL}; This reference is independent of the Comparator reference. Note: 00= Internal Reference Disabled, ...
Page 134
ADC Control/Status Register 1 The second ADC Control register contains the voltage reference level selection bit. Table 73. ADC Control/Status Register 1 (ADCCTL1) BITS 7 6 REFSELH FIELD 1 0 RESET R/W R/W R/W ADDR REFSELH—Voltage Reference Level Select High ...
Page 135
ADC Data Low Bits Register The ADC Data Low Byte register contains the lower bits of the ADC output as well as an overflow status bit. The output is a 11-bit two’s complement value. During a single-shot conversion, this value ...
Page 136
PS024314-0308 ® Z8 Encore! XP F0823 Series Product Specification Analog-to-Digital Converter 126 ...
Page 137
Comparator ® Z8 Encore! XP pares two analog input signals. A GPIO ( input. The negative input ( internal reference. The output is available as an interrupt source or can be routed to an external pin using the GPIO multiplex. ...
Page 138
Table 76. Comparator Control Register (CMP0) BITS 7 6 INPSEL INNSEL FIELD 0 0 RESET R/W R/W R/W ADDR INPSEL—Signal Select for Positive Input 0 = GPIO pin used as positive comparator input 1 = temperature sensor used as positive ...
Page 139
Flash Memory The products in Z8 Encore (2048 (1024) of non-volatile Flash memory with read/write/erase capabil- ity. Flash Memory can be programmed and erased in-circuit by either user code or through the On-Chip Debugger. ...
Page 140
Figure 20. Flash Memory Arrangement Flash Information Area The Flash information area is separate from program memory and is mapped to the address range FE00H for the analog peripherals are stored here. Factory calibration data for the ADC is also ...
Page 141
Operation The Flash Controller programs and erases Flash memory. The Flash Controller provides the proper Flash controls and timing for Byte Programming, Page Erase, and Mass Erase of Flash memory. The Flash Controller contains several protection mechanisms to prevent accidental ...
Page 142
Reset Lock State 0 Write Page Select Register Write FCTL No 73H Yes Lock State 1 Write FCTL No 8CH Yes Write Page Select Register No Page Select values match? Yes Yes Page in Protected Sector? No Page Unlocked Program/Erase ...
Page 143
Flash Operation Timing Using the Flash Frequency Registers Before performing either a program or erase operation on Flash memory, you must first configure the Flash Frequency High and Low Byte registers. The Flash Frequency regis- ters allow programming and erasing ...
Page 144
Table 78. Flash Code Protection Using the Flash Option Bits FWP Flash Code Protection Description 0 Programming and erasing disabled for all of Flash Program Memory. In user code programming, Page Erase, and Mass Erase are all disabled. Mass ...
Page 145
... CPU Core User Manual (UM0128) available for LDC LDCI download at www.zilog.com. While the Flash Controller programs the Flash memory, the eZ8 CPU idles but the system clock and on-chip peripherals continue to operate. To exit programming mode and lock the Flash, write any value to the Flash Control register, except the Mass Erase or Page Erase commands ...
Page 146
... Erase operations are also supported when the Flash Controller is bypassed. For more information on bypassing the Flash Controller, refer to Third-Party Flash Pro- gramming Support for Z8 Encore! (AN0117) available for download at www.zilog.com. Flash Controller Behavior in DEBUG Mode The following changes in behavior of the Flash Controller occur when the Flash Controller is accessed using the On-Chip Debugger: • ...
Page 147
Flash Control Register Definitions Flash Control Register The Flash Controller must be unlocked using the Flash Control (FTCTL) register before programming or erasing the Flash memory. Writing the sequence to the Flash Control register unlocks the Flash Controller. When the ...
Page 148
Reserved—0 when read FSTAT—Flash Controller Status 000000 = Flash Controller locked 000001 = First unlock command received (73H written) 000010 = Second unlock command received (8CH written) 000011 = Flash Controller unlocked 000100 = Sector protect register selected 001xxx = ...
Page 149
Flash Sector Protect Register The Flash Sector Protect (FPROT) register is shared with the Flash Page Select Register. When the Flash Control Register this address targets the Flash Sector Protect Register. In all other cases, it targets the Flash Page ...
Page 150
Table 83. Flash Frequency High Byte Register (FFREQH) BITS 7 6 FIELD 0 0 RESET R/W R/W R/W ADDR FFREQH—Flash Frequency High Byte High byte of the 16-bit Flash Frequency value Table 84. Flash Frequency Low Byte Register (FFREQL) BITS ...
Page 151
Flash Option Bits Programmable Flash option bits allow user configuration of certain aspects of ® Z8 Encore! XP Flash program memory and loaded into holding registers during Reset. The features available for control through the Flash Option Bits include: • ...
Page 152
... Flash memory. Randomized Lot Identification Bits As an optional feature, Zilog is able to provide a factory-programmed random lot identifier. With this feature, all devices in a given production lot are programmed with the same random number. This random number is uniquely regenerated for each successive production lot and is not likely to be repeated ...
Page 153
The randomized lot identifier byte binary value, stored in the flash information page (for more details, see ized Lot Identifier memory. Reading the Flash Information Page The following code example shows how to read data from the ...
Page 154
Trim Bit Data Register The Trim Bid Data (TRMDR) register contains the read or write data for access to the trim option bits. Table 86. Trim Bit Data Register (TRMDR) BITS 7 6 FIELD 0 0 RESET R/W R/W R/W ...
Page 155
Watchdog Timer can only be disabled by a Reset or Stop Mode Recovery. This setting is the default for unprogrammed (erased) Flash. Reserved—R/W bits must be 1 during writes; 1 when read. VBO_AO—Voltage Brownout Protection Always Voltage ...
Page 156
This bit only enables the crystal oscillator. Its selection as system clock must be done man- Note: ually Crystal oscillator is enabled during reset, resulting in longer reset timing 1 = Crystal oscillator is disabled during reset, resulting ...
Page 157
... ADDR Note Unchanged by Reset. R/W = Read/Write. IPO_TRIM—Internal Precision Oscillator Trim Byte Contains trimming bits for Internal Precision Oscillator. Trim Bit Address 0003H—Reserved Trim Bit Address 0004H—Reserved Zilog Calibration Data ADC Calibration Data Table 92. ADC Calibration Bits BITS 7 6 FIELD ...
Page 158
Software Compensation Procedure provided in Table 93 Table 93. ADC Calibration Data Location Info Page Memory Compensation Address Address Usage 60 FE60 Offset 08 FE08 Gain High Byte 09 FE09 Gain Low Byte 63 FE63 Offset 0A FE0A Gain High ...
Page 159
Table 95. Serialization Data Locations Info Page Address Memory Address Usage 1C FE1C 1D FE1D 1E FE1E 1F FE1F Randomized Lot Identifier Table 96. Lot Identification Number (RAND_LOT) BITS 7 6 FIELD U U RESET R/W R/W R/W ADDR Note: ...
Page 160
Table 97. Randomized Lot ID Locations (Continued) Info Page Memory Address Address 5C FE5C 5D FE5D 5E FE5E 5F FE5F 61 FE61 62 FE62 64 FE64 65 FE65 67 FE67 68 FE68 6A FE6A 6B FE6B 6D FE6D 6E FE6E ...
Page 161
On-Chip Debugger ® Z8 Encore! XP that provides advanced debugging features that include: • Single pin interface • Reading and writing of the register file • Reading and writing of program and data memory • Setting of breakpoints and watchpoints ...
Page 162
Operation The following sections describes the operation of OCD. OCD Interface The OCD uses the DBG pin for communication with an external host. This one-pin interface is a bidirectional open-drain interface that transmits and receives data. Data transmission is half-duplex, ...
Page 163
RS-232 TX RS-232 RX Figure 24. Interfacing the On-Chip Debugger’s DBG Pin with an RS-232 Interface (2) DEBUG Mode The operating characteristics of the devices in DEBUG mode are: • The eZ8 CPU fetch unit stops, idling the eZ8 CPU, ...
Page 164
PA0/DBG pin can be used to autobaud and cause the device to enter DEBUG mode. For more details, see page 156. Exiting DEBUG Mode The device exits DEBUG mode following any of these operations: • Clearing the DBGMODE ...
Page 165
The maximum possible baud rate for asynchronous datastreams is the system clock frequency divided by four, but this theoretical maximum is possible only for low noise ...
Page 166
OCD Unlock Sequence (8-Pin Devices Only) Because of pin-sharing on the 8-pin device, an unlock sequence must be performed to access the DBG pin. If this sequence is not completed during a system reset, then the PA0/ DBG pin functions ...
Page 167
On-Chip Debugger Commands The host communicates to the OCD by sending OCD commands using the DBG interface. During normal operation, only a subset of the OCD commands are available. In DEBUG mode, all OCD commands become available unless the user ...
Page 168
Command Debug Command Byte Stuff Instruction Execute Instruction Reserved 13H–FFH In the following list of OCD Commands, data and commands sent from the host to the OCD are identified by ’ is identified by ’ DBG → Data • Read ...
Page 169
DBG 05H → DBG OCDCTL[7:0] • Write Program Counter (06H)—The Write Program Counter command writes the data that follows to the eZ8 CPU’s Program Counter (PC). If the device is not in DEBUG mode or if the Flash Read ...
Page 170
DEBUG mode or if the Flash Read Protect Option bit is enabled, the data is dis- carded. ← DBG 0AH ← DBG Program Memory Address[15:8] ← DBG Program Memory Address[7:0] ← DBG Size[15:8] ← DBG Size[7:0] ← ...
Page 171
Read Program Memory CRC (0EH)—The Read Program Memory Cyclic Redundan- cy Check (CRC) command computes and returns the CRC of Program Memory using the 16-bit CRC-CCITT polynomial. If the device is not in DEBUG mode, this command re- turns ...
Page 172
A reset and stop function can be achieved by writing function can be achieved by writing a run function can be implemented by writing . Table 99. OCD Control Register (OCDCTL) BITS 7 6 DBGMODE BRKEN FIELD 0 0 RESET ...
Page 173
OCD Status Register The OCD Status register reports status information about the current state of the debugger and the system. Table 100. OCD Status Register (OCDSTAT) BITS 7 6 DBG HALT FIELD 0 0 RESET R R R/W DBG—Debug Status ...
Page 174
PS024314-0308 ® Z8 Encore! XP F0823 Series Product Specification On-Chip Debugger 164 ...
Page 175
Oscillator Control ® Z8 Encore! XP user-selectable: • On-chip precision trimmed RC oscillator • External clock drive • On-chip low power Watchdog Timer oscillator In addition, Z8 Encore! XP F0823 Series devices contain clock failure detection and recovery circuitry, allowing ...
Page 176
Unintentional accesses to the oscillator control register can actually stop the chip by Caution: switching to a non-functioning oscillator. To prevent this condition, the oscillator con- trol block employs a register unlocking/locking scheme. OSC Control Register Unlocking/Locking To write the ...
Page 177
Watchdog Timer Failure In the event of a Watchdog Timer oscillator failure, a similar non-maskable interrupt-like event is issued. This event does not trigger an attendant clock switch-over, but alerts the CPU of the failure. After a Watchdog Timer failure, ...
Page 178
INTEN—Internal Precision Oscillator Enable 1 = Internal precision oscillator is enabled 0 = Internal precision oscillator is disabled Reserved—R/W bits must be 0 during writes; 0 when read WDTEN—Watchdog Timer Oscillator Enable 1 = Watchdog Timer oscillator is enabled 0 ...
Page 179
Internal Precision Oscillator The internal precision oscillator (IPO) is designed for use without external components. You can either manually trim the oscillator for a non-standard frequency or use the automatic factory-trimmed version to achieve a 5.53 MHz frequency. The features ...
Page 180
PS024314-0308 ® Z8 Encore! XP F0823 Series Product Specification Internal Precision Oscillator 170 ...
Page 181
CPU Instruction Set Assembly Language Programming Introduction The eZ8 CPU assembly language provides a means for writing an application program without concern for actual memory addresses or machine instruction formats. A program written in assembly language is called a ...
Page 182
Assembly Language Syntax For proper instruction execution, eZ8 CPU assembly language syntax requires that the operands be written as ‘destination, source’. After assembly, the object code usually has the operands in the order ‘source, destination’, but ordering is opcode-dependent. The ...
Page 183
Table 105. Notational Shorthand Notation Description b Bit cc Condition Code DA Direct Address ER Extended Addressing Register IM Immediate Data Ir Indirect Working Register IR Indirect Register Irr Indirect Working Register Pair IRR Indirect Register Pair p Polarity ...
Page 184
Table 106 lists additional symbols that are used throughout the Instruction Summary and Instruction Set Description sections. Table 106. Additional Symbols Symbol Definition dst Destination Operand src Source Operand @ Indirect Address Prefix SP Stack Pointer PC Program Counter FLAGS ...
Page 185
Rotate and Shift Tables 107 through number of operands required for each instruction. Some instructions appear in more than one table as these instruction can be considered as a subset of more than one category. Within these tables, the ...
Page 186
Table 108. Bit Manipulation Instructions Mnemonic Operands BCLR bit, dst BIT p, bit, dst BSET bit, dst BSWAP dst CCF — RCF — SCF — TCM dst, src TCMX dst, src TM dst, src TMX dst, src Table 109. Block ...
Page 187
Table 110. CPU Control Instructions (Continued) Mnemonic Operands SCF — SRP src STOP — WDT — Table 111. Load Instructions Mnemonic Operands Instruction CLR dst LD dst, src LDC dst, src LDCI dst, src LDE dst, src LDEI dst, src ...
Page 188
Table 112. Logical Instructions (Continued) Mnemonic Operands Instruction ORX dst, src XOR dst, src XORX dst, src Table 113. Program Control Instructions Mnemonic Operands BRK — BTJ p, bit, src, DA Bit Test and Jump BTJNZ bit, src, DA BTJZ ...
Page 189
Table 114. Rotate and Shift Instructions (Continued) Mnemonic Operands SRA dst SRL dst SWAP dst eZ8 CPU Instruction Summary Table 115 summarizes the eZ8 CPU instructions. The table identifies the addressing modes employed by the instruction, the effect upon the ...
Page 190
Table 115. eZ8 CPU Instruction Summary (Continued) Assembly Mnemonic Symbolic Operation dst ← dst AND src AND dst, src dst ← dst AND src ANDX dst, src ATM Block all interrupt and DMA requests during execution of the next 3 ...
Page 191
Table 115. eZ8 CPU Instruction Summary (Continued) Assembly Mnemonic Symbolic Operation dst ← ~dst COM dst CP dst, src dst - src CPC dst, src dst - src - C CPCX dst, src dst - src - C CPX dst, ...
Page 192
Table 115. eZ8 CPU Instruction Summary (Continued) Assembly Mnemonic Symbolic Operation HALT HALT Mode dst ← dst + 1 INC dst dst ← dst + 1 INCW dst FLAGS ← @SP IRET SP ← ← @SP ...
Page 193
Table 115. eZ8 CPU Instruction Summary (Continued) Assembly Mnemonic Symbolic Operation dst ← src LDC dst, src dst ← src LDCI dst, src r ← ← dst ← src LDE dst, src dst ...
Page 194
Table 115. eZ8 CPU Instruction Summary (Continued) Assembly Mnemonic Symbolic Operation dst ← dst OR src OR dst, src dst ← dst OR src ORX dst, src dst ← @SP POP dst SP ← dst ← @SP ...
Page 195
Table 115. eZ8 CPU Instruction Summary (Continued) Assembly Mnemonic Symbolic Operation RR dst dst RRC dst dst dst ← dst – src - C ...
Page 196
Table 115. eZ8 CPU Instruction Summary (Continued) Assembly Mnemonic Symbolic Operation dst ← dst – src SUBX dst, src dst[7:4] ↔ dst[3:0] SWAP dst TCM dst, src (NOT dst) AND src TCMX dst, src (NOT dst) AND src TM dst, ...
Page 197
Table 115. eZ8 CPU Instruction Summary (Continued) Assembly Mnemonic Symbolic Operation dst ← dst XOR src XOR dst, src dst ← dst XOR src XORX dst, src Flags Notation Value is a function of the result of the ...
Page 198
Opcode Maps A description of the opcode map data and the abbreviations are provided in Figure 27 and Figure 28 Table 116 lists Opcode Map abbreviations. Opcode Upper Nibble First Operand After Assembly Figure 26. Opcode Map Cell Description PS024314-0308 ...
Page 199
Table 116. Opcode Map Abbreviations Abbreviation Description b Bit position cc Condition code X 8-bit signed index or displacement DA Destination address ER Extended Addressing register IM Immediate data value Ir Indirect Working Register IR Indirect register Irr Indirect Working ...
Page 200
BRK SRP ADD ADD 0 IM r1,r2 r1,Ir2 2.2 2.3 2.3 2.4 RLC RLC ADC ADC 1 R1 IR1 r1,r2 r1,Ir2 2.2 2.3 2.3 2.4 INC INC SUB SUB 2 R1 IR1 ...