STM8S207C6T6 STMicroelectronics, STM8S207C6T6 Datasheet - Page 13

MCU 8BIT 32K MEMORY 48-LQFP

STM8S207C6T6

Manufacturer Part Number
STM8S207C6T6
Description
MCU 8BIT 32K MEMORY 48-LQFP
Manufacturer
STMicroelectronics
Series
STM8Sr
Datasheet

Specifications of STM8S207C6T6

Mfg Application Notes
STM8S Getting Started
Core Processor
STM8
Core Size
8-Bit
Speed
24MHz
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
38
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.95 V ~ 5.5 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-LQFP
Processor Series
STM8S20x
Core
STM8
Data Bus Width
8 bit
Data Ram Size
6 KB
Interface Type
CAN, 12C, SPI, UART
Maximum Clock Frequency
24 MHz
Number Of Programmable I/os
38
Number Of Timers
2
Operating Supply Voltage
2.95 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWSTM8
Development Tools By Supplier
STICE-SYS001
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit
For Use With
497-10032 - EVAL KIT MOTOR CONTROL STM8S497-10031 - EVAL KIT TOUCH SENSING STM8S497-10592 - BOARD DAUGHTER FOR STM8S207/8497-10593 - KIT STARTER FOR STM8S207/8 SER497-8506 - BOARD EVAL FOR STM8S
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
497-8950
STM8S207C6T6

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STM8S207xx, STM8S208xx
4
4.1
Product overview
The following section intends to give an overview of the basic features of the STM8S20xxx
performance line functional modules and peripherals.
For more detailed information please refer to the corresponding family reference manual
(RM0016).
Central processing unit STM8
The 8-bit STM8 core is designed for code efficiency and performance.
It contains 6 internal registers which are directly addressable in each execution context, 20
addressing modes including indexed indirect and relative addressing and 80 instructions.
Architecture and registers
Addressing
Instruction set
Harvard architecture
3-stage pipeline
32-bit wide program memory bus - single cycle fetching for most instructions
X and Y 16-bit index registers - enabling indexed addressing modes with or without
offset and read-modify-write type data manipulations
8-bit accumulator
24-bit program counter - 16-Mbyte linear memory space
16-bit stack pointer - access to a 64 K-level stack
8-bit condition code register - 7 condition flags for the result of the last instruction
20 addressing modes
Indexed indirect addressing mode for look-up tables located anywhere in the address
space
Stack pointer relative addressing mode for local variables and parameter passing
80 instructions with 2-byte average instruction size
Standard data movement and logic/arithmetic functions
8-bit by 8-bit multiplication
16-bit by 8-bit and 16-bit by 16-bit division
Bit manipulation
Data transfer between stack and accumulator (push/pop) with direct stack access
Data transfer using the X and Y registers or direct memory-to-memory transfers
Doc ID 14733 Rev 11
Product overview
13/105

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