ST62T20CB6 STMicroelectronics, ST62T20CB6 Datasheet - Page 31

IC MCU 8BIT OTP 4K 20 PDIP

ST62T20CB6

Manufacturer Part Number
ST62T20CB6
Description
IC MCU 8BIT OTP 4K 20 PDIP
Manufacturer
STMicroelectronics
Series
ST6r
Datasheet

Specifications of ST62T20CB6

Core Processor
ST6
Core Size
8-Bit
Speed
8MHz
Peripherals
LVD, POR, WDT
Number Of I /o
12
Program Memory Size
4KB (4K x 8)
Program Memory Type
OTP
Ram Size
64 x 8
Voltage - Supply (vcc/vdd)
3 V ~ 6 V
Data Converters
A/D 8x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
20-DIP (0.300", 7.62mm)
Controller Family/series
ST6
No. Of I/o's
12
Ram Memory Size
64Byte
Cpu Speed
8MHz
No. Of Timers
1
Rohs Compliant
Yes
Processor Series
ST62T2x
Core
ST6
Data Bus Width
8 bit
Data Ram Size
64 B
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
12
Number Of Timers
2
Operating Supply Voltage
3 V to 6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
Development Tools By Supplier
ST622XC-KIT/110, ST62GP-EMU2, ST62E2XC-EPB/110, ST62E6XC-EPB/US, STREALIZER-II
Minimum Operating Temperature
- 40 C
On-chip Adc
8 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Connectivity
-
Lead Free Status / Rohs Status
In Transition
Other names
497-2098-5

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5.11 REGISTER DESCRIPTION
INTERRUPT OPTION REGISTER (IOR)
Address: 0C8h — Write Only
Reset status: 00h
Caution: This register is write-only and cannot be
accessed by single-bit operations (SET, RES,
DEC,...).
Bit 7 =Reserved, must be cleared.
Bit 6 = LES Level/Edge Selection bit.
0: Falling edge sensitive mode is selected for inter-
Table 8. Interrupt Mapping
* Depending on device. See device summary on page 1.
rupt vector #1
Vector #0
Vector #1
Vector #2
Vector #3
Vector #4
7
-
number
Vector
LES
Port A
Port B
TIMER
ESB
RESET
NMI
ADC*
Source
Block
GEN
Reset
Non Maskable Interrupt
Ext. Interrupt Port A
Ext. Interrupt Port B
Timer underflow
End Of Conversion
-
Description
-
NOT USED
-
0
-
Register
ADCR
TSCR
Label
N/A
N/A
N/A
N/A
1: Low level sensitive mode is selected for inter-
Bit 5 = ESB Edge Selection bit.
0: Falling edge mode on interrupt vector #2
1: Rising edge mode on interrupt vector #2
Bit 4 = GEN Global Enable Interrupt.
0: Disable all maskable interrupts
1: Enable all maskable interrupts
Note: When the GEN bit is cleared, the NMI inter-
rupt is active but cannot be used to exit from STOP
or WAIT modes.
Bits 3:0 = Reserved, must be cleared.
rupt vector #1
ST6208C/ST6209C/ST6210C/ST6220C
EOC
Flag
TMZ
N/A
N/A
N/A
N/A
STOP
from
Exit
yes
yes
yes
yes
yes
no
FFCh-FFDh
FFAh-FFBh
FFEh-FFFh
FF8h-FF9h
FF6h-FF7h
FF4h-FF5h
FF2h-FF3h
FF0h-FF1h
Address
Vector
Priority
Highest
Priority
Lowest
Priority
Order
31/104
1

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