IC MCU 8BIT OTP 4K 20 PDIP

ST62T20CB6

Manufacturer Part NumberST62T20CB6
DescriptionIC MCU 8BIT OTP 4K 20 PDIP
ManufacturerSTMicroelectronics
SeriesST6
ST62T20CB6 datasheet
 


Specifications of ST62T20CB6

Core ProcessorST6Core Size8-Bit
Speed8MHzPeripheralsLVD, POR, WDT
Number Of I /o12Program Memory Size4KB (4K x 8)
Program Memory TypeOTPRam Size64 x 8
Voltage - Supply (vcc/vdd)3 V ~ 6 VData ConvertersA/D 8x8b
Oscillator TypeInternalOperating Temperature-40°C ~ 85°C
Package / Case20-DIP (0.300", 7.62mm)Controller Family/seriesST6
No. Of I/o's12Ram Memory Size64Byte
Cpu Speed8MHzNo. Of Timers1
Rohs CompliantYesProcessor SeriesST62T2x
CoreST6Data Bus Width8 bit
Data Ram Size64 BMaximum Clock Frequency8 MHz
Number Of Programmable I/os12Number Of Timers2
Operating Supply Voltage3 V to 6 VMaximum Operating Temperature+ 85 C
Mounting StyleThrough HoleDevelopment Tools By SupplierST622XC-KIT/110, ST62GP-EMU2, ST62E2XC-EPB/110, ST62E6XC-EPB/US, STREALIZER-II
Minimum Operating Temperature- 40 COn-chip Adc8 bit
Lead Free Status / RoHS StatusLead free / RoHS CompliantEeprom Size-
Connectivity-Other names497-2098-5
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5.4 INTERRUPTS
The ST6 core may be interrupted by four maska-
ble interrupt sources, in addition to a Non Maska-
ble Interrupt (NMI) source. The interrupt process-
ing flowchart is shown in
Figure
Maskable interrupts must be enabled by setting
the GEN bit in the IOR register. However, even if
they are disabled (GEN bit = 0), interrupt events
are latched and may be processed as soon as the
GEN bit is set.
Each source is associated with a specific Interrupt
Vector, located in Program space (see
the vector location, the user must write a Jump in-
Figure 17. Interrupts Block Diagram
V D D
NMI
I/O PORT REGISTER
PA0...PA3
“INPUT WITH INTERRUPT”
CONFIGURATION
I/O PORT REGISTER
PB0...PB7
“INPUT WITH INTERRUPT”
CONFIGURATION
TIMER
(TSCR REGISTER)
A/D CONVERTER *
(ADCR REGISTER)
* Depending on device. See device summary on page 1.
ST6208C/ST6209C/ST6210C/ST6220C
struction to the associated interrupt service rou-
tine.
When an interrupt source generates an interrupt
18.
request, the PC register is loaded with the address
of the interrupt vector, which then causes a Jump
to the relevant interrupt service routine, thus serv-
icing the interrupt.
Interrupt are triggered by events either on external
pins, or from the on-chip peripherals. Several
events can be ORed on the same interrupt vector.
Table
8). In
On-chip peripherals have flag registers to deter-
mine which event triggered the interrupt.
LATCH
CLEARED BY H/W
AT START OF VECTOR #0 ROUTINE
LATCH
CLEARED BY H/W
AT START OF
VECTOR #1 ROUTINE
(IOR REGISTER)
LATCH
ESB BIT
CLEARED
(IOR REGISTER)
BY H/W AT START OF
VECTOR #2 ROUTINE
TMZ BIT
ETI BIT
EAI BIT
EOC BIT
VECTOR #0
0
VECTOR #1
1
LES BIT
EXIT FROM
STOP/WAIT
VECTOR #2
VECTOR #3
VECTOR #4
GEN BIT
(IOR REGISTER)
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