IC MCU 8BIT OTP 4K 20 PDIP

ST62T20CB6

Manufacturer Part NumberST62T20CB6
DescriptionIC MCU 8BIT OTP 4K 20 PDIP
ManufacturerSTMicroelectronics
SeriesST6
ST62T20CB6 datasheet
 


Specifications of ST62T20CB6

Core ProcessorST6Core Size8-Bit
Speed8MHzPeripheralsLVD, POR, WDT
Number Of I /o12Program Memory Size4KB (4K x 8)
Program Memory TypeOTPRam Size64 x 8
Voltage - Supply (vcc/vdd)3 V ~ 6 VData ConvertersA/D 8x8b
Oscillator TypeInternalOperating Temperature-40°C ~ 85°C
Package / Case20-DIP (0.300", 7.62mm)Controller Family/seriesST6
No. Of I/o's12Ram Memory Size64Byte
Cpu Speed8MHzNo. Of Timers1
Rohs CompliantYesProcessor SeriesST62T2x
CoreST6Data Bus Width8 bit
Data Ram Size64 BMaximum Clock Frequency8 MHz
Number Of Programmable I/os12Number Of Timers2
Operating Supply Voltage3 V to 6 VMaximum Operating Temperature+ 85 C
Mounting StyleThrough HoleDevelopment Tools By SupplierST622XC-KIT/110, ST62GP-EMU2, ST62E2XC-EPB/110, ST62E6XC-EPB/US, STREALIZER-II
Minimum Operating Temperature- 40 COn-chip Adc8 bit
Lead Free Status / RoHS StatusLead free / RoHS CompliantEeprom Size-
Connectivity-Other names497-2098-5
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ST6208C/ST6209C/ST6210C/ST6220C
5.5
INTERRUPT
RULES
MANAGEMENT
A Reset can interrupt the NMI and peripheral
interrupt routines
The Non Maskable Interrupt request has the
highest priority and can interrupt any peripheral
interrupt routine at any time but cannot interrupt
another NMI interrupt.
No peripheral interrupt can interrupt another. If
more than one interrupt request is pending,
these are processed by the processor core
according to their priority level: vector #1 has the
highest priority while vector #4 the lowest. The
priority of each interrupt source is fixed by
hardware (see
Interrupt Mapping
5.6 INTERRUPTS AND LOW POWER MODES
All interrupts cause the processor to exit from
WAIT mode. Only the external and some specific
interrupts from the on-chip peripherals cause the
processor to exit from STOP mode (refer to the
“Exit from STOP“ column in the Interrupt Mapping
Table).
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1
AND
PRIORITY
5.7 NON MASKABLE INTERRUPT
This interrupt is triggered when a falling edge oc-
curs on the NMI pin regardless of the state of the
GEN bit in the IOR register. An interrupt request
on NMI vector #0 is latched by a flip flop which is
automatically reset by the core at the beginning of
the NMI service routine.
5.8 PERIPHERAL INTERRUPTS
Different peripheral interrupt flags in the peripheral
control registers are able to cause an interrupt
when they are active if both:
– The GEN bit of the IOR register is set
table).
– The corresponding enable bit is set in the periph-
eral control register.
Peripheral interrupts are linked to vectors #3 and
#4. Interrupt requests are flagged by a bit in their
corresponding control register. This means that a
request cannot be lost, because the flag bit must
be cleared by user software.