IC MCU 8BIT OTP 4K 20 PDIP

ST62T20CB6

Manufacturer Part NumberST62T20CB6
DescriptionIC MCU 8BIT OTP 4K 20 PDIP
ManufacturerSTMicroelectronics
SeriesST6
ST62T20CB6 datasheet
 


Specifications of ST62T20CB6

Core ProcessorST6Core Size8-Bit
Speed8MHzPeripheralsLVD, POR, WDT
Number Of I /o12Program Memory Size4KB (4K x 8)
Program Memory TypeOTPRam Size64 x 8
Voltage - Supply (vcc/vdd)3 V ~ 6 VData ConvertersA/D 8x8b
Oscillator TypeInternalOperating Temperature-40°C ~ 85°C
Package / Case20-DIP (0.300", 7.62mm)Controller Family/seriesST6
No. Of I/o's12Ram Memory Size64Byte
Cpu Speed8MHzNo. Of Timers1
Rohs CompliantYesProcessor SeriesST62T2x
CoreST6Data Bus Width8 bit
Data Ram Size64 BMaximum Clock Frequency8 MHz
Number Of Programmable I/os12Number Of Timers2
Operating Supply Voltage3 V to 6 VMaximum Operating Temperature+ 85 C
Mounting StyleThrough HoleDevelopment Tools By SupplierST622XC-KIT/110, ST62GP-EMU2, ST62E2XC-EPB/110, ST62E6XC-EPB/US, STREALIZER-II
Minimum Operating Temperature- 40 COn-chip Adc8 bit
Lead Free Status / RoHS StatusLead free / RoHS CompliantEeprom Size-
Connectivity-Other names497-2098-5
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
Page 21
22
Page 22
23
Page 23
24
Page 24
25
Page 25
26
Page 26
27
Page 27
28
Page 28
29
Page 29
30
Page 30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
Page 30/104

Download datasheet (2Mb)Embed
PrevNext
ST6208C/ST6209C/ST6210C/ST6220C
5.10 INTERRUPT HANDLING PROCEDURE
The interrupt procedure is very similar to a call pro-
cedure, in fact the user can consider the interrupt
as an asynchronous call procedure. As this is an
asynchronous event, the user cannot know the
context and the time at which it occurred. As a re-
sult, the user should save all Data space registers
which may be used within the interrupt routines.
The following list summarizes the interrupt proce-
dure:
When an interrupt request occurs, the following
actions are performed by the MCU automatically:
– The core switches from the normal flags to the
interrupt flags (or the NMI flags).
– The PC contents are stored in the top level of the
stack.
– The normal interrupt lines are inhibited (NMI still
active).
– The internal latch (if any) is cleared.
– The associated interrupt vector is loaded in the PC.
When an interrupt request occurs, the following
actions must be performed by the user software:
– User selected registers have to be saved within
the interrupt service routine (normally on a soft-
ware stack).
– The source of the interrupt must be determined
by polling the interrupt flags (if more than one
source is associated with the same vector).
– The RETI (RETurn from Interrupt) instruction
must end the interrupt service routine.
After the RETI instruction is executed, the MCU re-
turns to the main routine.
Caution: When a maskable interrupt occurs while
the ST6 core is in NORMAL mode and during the
execution of an “ldi IOR, 00h” instruction (disabling
all maskable interrupts): if the interrupt request oc-
curs during the first 3 cycles of the “ldi” instruction
(which is a 4-cycle instruction) the core will switch
to interrupt mode BUT the flags CN and ZN will
NOT switch to the interrupt pair CI and ZI.
5.10.1 Interrupt Response Time
This is defined as the time between the moment
when the Program Counter is loaded with the in-
terrupt vector and when the program has jump to
the interrupt subroutine and is ready to execute
the code. It depends on when the interrupt occurs
while the core is processing an instruction.
30/104
1
Figure 18. Interrupt Processing Flow Chart
INSTRUCTION
FETCH
INSTRUCTION
EXECUTE
INSTRUCTION
WAS
NO
THE INSTRUCTION
A RETI?
YES
IS THE CORE
YES
ALREADY IN
NORMAL MODE?
NO
ENABLE
MASKABLE INTERRUPTS
SELECT
NORMAL FLAGS
“POP”
THE STACKED PC
NO
IS THERE AN
AN INTERRUPT REQUEST
AND INTERRUPT MASK?
YES
*)
If a latch is present on the interrupt source line
Table 7. Interrupt Response Time
Minimum
6 CPU cycles
Maximum
11 CPU cycles
One CPU cycle is 13 external clock cycles thus 11
CPU cycles = 11 x (13 /8M) = 17.875 µs with an 8
MHz external quartz.
LOAD PC FROM
INTERRUPT VECTOR
CLEAR
*)
INTERNAL LATCH
DISABLE
MASKABLE INTERRUPT
PUSH THE
PC INTO THE STACK
SELECT
INTERRUPT FLAGS