IC MCU 8BIT OTP 4K 20 PDIP

ST62T20CB6

Manufacturer Part NumberST62T20CB6
DescriptionIC MCU 8BIT OTP 4K 20 PDIP
ManufacturerSTMicroelectronics
SeriesST6
ST62T20CB6 datasheet
 

Specifications of ST62T20CB6

Core ProcessorST6Core Size8-Bit
Speed8MHzPeripheralsLVD, POR, WDT
Number Of I /o12Program Memory Size4KB (4K x 8)
Program Memory TypeOTPRam Size64 x 8
Voltage - Supply (vcc/vdd)3 V ~ 6 VData ConvertersA/D 8x8b
Oscillator TypeInternalOperating Temperature-40°C ~ 85°C
Package / Case20-DIP (0.300", 7.62mm)Controller Family/seriesST6
No. Of I/o's12Ram Memory Size64Byte
Cpu Speed8MHzNo. Of Timers1
Rohs CompliantYesProcessor SeriesST62T2x
CoreST6Data Bus Width8 bit
Data Ram Size64 BMaximum Clock Frequency8 MHz
Number Of Programmable I/os12Number Of Timers2
Operating Supply Voltage3 V to 6 VMaximum Operating Temperature+ 85 C
Mounting StyleThrough HoleDevelopment Tools By SupplierST622XC-KIT/110, ST62GP-EMU2, ST62E2XC-EPB/110, ST62E6XC-EPB/US, STREALIZER-II
Minimum Operating Temperature- 40 COn-chip Adc8 bit
Lead Free Status / RoHS StatusLead free / RoHS CompliantEeprom Size-
Connectivity-Other names497-2098-5
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5.11 REGISTER DESCRIPTION
INTERRUPT OPTION REGISTER (IOR)
Address: 0C8h — Write Only
Reset status: 00h
7
-
LES
ESB
GEN
-
Caution: This register is write-only and cannot be
accessed by single-bit operations (SET, RES,
DEC,...).
Bit 7 =Reserved, must be cleared.
Bit 6 = LES Level/Edge Selection bit.
0: Falling edge sensitive mode is selected for inter-
rupt vector #1
Table 8. Interrupt Mapping
Vector
Source
Block
number
RESET
Reset
Vector #0
NMI
Non Maskable Interrupt
Vector #1
Port A
Ext. Interrupt Port A
Vector #2
Port B
Ext. Interrupt Port B
Vector #3
TIMER
Timer underflow
Vector #4
ADC*
End Of Conversion
* Depending on device. See device summary on page 1.
ST6208C/ST6209C/ST6210C/ST6220C
1: Low level sensitive mode is selected for inter-
rupt vector #1
Bit 5 = ESB Edge Selection bit.
0
0: Falling edge mode on interrupt vector #2
1: Rising edge mode on interrupt vector #2
-
-
-
Bit 4 = GEN Global Enable Interrupt.
0: Disable all maskable interrupts
1: Enable all maskable interrupts
Note: When the GEN bit is cleared, the NMI inter-
rupt is active but cannot be used to exit from STOP
or WAIT modes.
Bits 3:0 = Reserved, must be cleared.
Register
Description
Label
N/A
N/A
NOT USED
N/A
N/A
TSCR
ADCR
Exit
Vector
Flag
from
Address
STOP
N/A
yes
FFEh-FFFh
N/A
yes
FFCh-FFDh
FFAh-FFBh
FF8h-FF9h
N/A
yes
FF6h-FF7h
N/A
yes
FF4h-FF5h
TMZ
yes
FF2h-FF3h
EOC
no
FF0h-FF1h
Priority
Order
Highest
Priority
Lowest
Priority
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