IC MCU 8BIT OTP 4K 20 PDIP

ST62T20CB6

Manufacturer Part NumberST62T20CB6
DescriptionIC MCU 8BIT OTP 4K 20 PDIP
ManufacturerSTMicroelectronics
SeriesST6
ST62T20CB6 datasheet
 

Specifications of ST62T20CB6

Core ProcessorST6Core Size8-Bit
Speed8MHzPeripheralsLVD, POR, WDT
Number Of I /o12Program Memory Size4KB (4K x 8)
Program Memory TypeOTPRam Size64 x 8
Voltage - Supply (vcc/vdd)3 V ~ 6 VData ConvertersA/D 8x8b
Oscillator TypeInternalOperating Temperature-40°C ~ 85°C
Package / Case20-DIP (0.300", 7.62mm)Controller Family/seriesST6
No. Of I/o's12Ram Memory Size64Byte
Cpu Speed8MHzNo. Of Timers1
Rohs CompliantYesProcessor SeriesST62T2x
CoreST6Data Bus Width8 bit
Data Ram Size64 BMaximum Clock Frequency8 MHz
Number Of Programmable I/os12Number Of Timers2
Operating Supply Voltage3 V to 6 VMaximum Operating Temperature+ 85 C
Mounting StyleThrough HoleDevelopment Tools By SupplierST622XC-KIT/110, ST62GP-EMU2, ST62E2XC-EPB/110, ST62E6XC-EPB/US, STREALIZER-II
Minimum Operating Temperature- 40 COn-chip Adc8 bit
Lead Free Status / RoHS StatusLead free / RoHS CompliantEeprom Size-
Connectivity-Other names497-2098-5
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I/O PORTS (Cont’d)
7.2.5 Instructions NOT to be used to access
Port Data registers (SET, RES, INC and DEC)
DO NOT USE READ-MODIFY-WRITE INSTRUC-
TIONS (SET, RES, INC and DEC) ON PORT
DATA REGISTERS IF ANY PIN OF THE PORT IS
CONFIGURED IN INPUT MODE.
These instructions make an implicit read and write
back of the entire register. In port input mode,
however, the data register reads from the input
pins directly, and not from the data register latch-
es. Since data register information in input mode is
used to set the characteristics of the input pin (in-
terrupt, pull-up, analog input), these may be unin-
tentionally reprogrammed depending on the state
of the input pins.
As a general rule, it is better to only use single bit
instructions on data registers when the whole (8-
bit) port is in output mode. In the case of inputs or
of mixed inputs and outputs, it is advisable to keep
a copy of the data register in RAM. Single bit in-
structions may then be used on the RAM copy, af-
ter which the whole copy register can be written to
the port data register:
SET bit, datacopy
LD a, datacopy
LD DRA, a
7.2.6 Recommendations
1. Safe I/O State Switching Sequence
Switching the I/O ports from one state to another
should be done in a sequence which ensures that
no unwanted side effects can occur. The recom-
mended safe transitions are illustrated in
The Interrupt Pull-up to Input Analog transition
(and vice-vesra) is potentially risky and should be
avoided when changing the I/O operating mode.
Figure 24. Diagram showing Safe I/O State Transitions
Interrupt
pull-up
Input
pull-up (Reset
state)
Output
Open Drain
Output
Push-pull
Note *. xxx = DDR, OR, DR Bits respectively
ST6208C/ST6209C/ST6210C/ST6220C
2. Handling Unused Port Bits
On ports that have less than 8 external pins con-
nected:
– Leave the unbonded pins in reset state and do
not change their configuration.
– Do not use instructions that act on a whole port
register (INC, DEC, or read operations). Unavail-
able bits must be masked by software (AND in-
struction). Thus, when a read operation
performed on an incomplete port is followed by a
comparison, use a mask.
3. High Impedance Input
On any CMOS device, it is not recommended to
connect high impedance on input pins. The choice
of these impedance has to be done with respect to
the maximum leakage current defined in the da-
tasheet. The risk is to be close or out of specifica-
tion on the input levels applied to the device.
7.3 LOW POWER MODES
The WAIT and STOP instructions allow the
ST62xx to be used in situations where low power
consumption is needed. The lowest power con-
sumption is achieved by configuring I/Os in output
push-pull low mode.
Mode
No effect on I/O ports. External interrupts
WAIT
cause the device to exit from WAIT mode.
No effect on I/O ports. External interrupts
STOP
cause the device to exit from STOP mode.
Figure 24
7.4 INTERRUPTS
The external interrupt event generates an interrupt
if the corresponding configuration is selected with
DDR, DR and OR registers (see
GEN-bit in the IOR register is set.
010*
011
000
001
100
101
110
111
Description
Table
9) and the
Input
Analog
Input
Output
Open Drain
Output
Push-pull
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