IC MCU 8BIT OTP 4K 20 PDIP

ST62T20CB6

Manufacturer Part NumberST62T20CB6
DescriptionIC MCU 8BIT OTP 4K 20 PDIP
ManufacturerSTMicroelectronics
SeriesST6
ST62T20CB6 datasheet
 


Specifications of ST62T20CB6

Core ProcessorST6Core Size8-Bit
Speed8MHzPeripheralsLVD, POR, WDT
Number Of I /o12Program Memory Size4KB (4K x 8)
Program Memory TypeOTPRam Size64 x 8
Voltage - Supply (vcc/vdd)3 V ~ 6 VData ConvertersA/D 8x8b
Oscillator TypeInternalOperating Temperature-40°C ~ 85°C
Package / Case20-DIP (0.300", 7.62mm)Controller Family/seriesST6
No. Of I/o's12Ram Memory Size64Byte
Cpu Speed8MHzNo. Of Timers1
Rohs CompliantYesProcessor SeriesST62T2x
CoreST6Data Bus Width8 bit
Data Ram Size64 BMaximum Clock Frequency8 MHz
Number Of Programmable I/os12Number Of Timers2
Operating Supply Voltage3 V to 6 VMaximum Operating Temperature+ 85 C
Mounting StyleThrough HoleDevelopment Tools By SupplierST622XC-KIT/110, ST62GP-EMU2, ST62E2XC-EPB/110, ST62E6XC-EPB/US, STREALIZER-II
Minimum Operating Temperature- 40 COn-chip Adc8 bit
Lead Free Status / RoHS StatusLead free / RoHS CompliantEeprom Size-
Connectivity-Other names497-2098-5
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Opcode Map Summary (Continued)
LOW
8
9
1000
1001
HI
2
JRNZ 4
JP 2
0
e
abc
0000
1
pcr 2
ext 1
2
JRNZ 4
JP 2
1
e
abc
0001
1
pcr 2
ext 1
2
JRNZ 4
JP 2
2
e
abc
0010
1
pcr 2
ext 1
2
JRNZ 4
JP 2
3
e
abc
0011
1
pcr 2
ext 1
2
JRNZ 4
JP 2
4
e
abc
0100
1
pcr 2
ext 1
2
JRNZ 4
JP 2
5
e
abc
0101
1
pcr 2
ext 1
2
JRNZ 4
JP 2
6
e
abc
0110
1
pcr 2
ext 1
2
JRNZ 4
JP 2
7
e
abc
0111
1
pcr 2
ext 1
2
JRNZ 4
JP 2
8
e
abc
1000
1
pcr 2
ext 1
2
JRNZ 4
JP 2
9
e
abc
1001
1
pcr 2
ext 1
2
JRNZ 4
JP 2
A
e
abc
1010
1
pcr 2
ext 1
2
JRNZ 4
JP 2
B
e
abc
1011
1
pcr 2
ext 1
2
JRNZ 4
JP 2
C
e
abc
1100
1
pcr 2
ext 1
2
JRNZ 4
JP 2
D
e
abc
1101
1
pcr 2
ext 1
2
JRNZ 4
JP 2
E
e
abc
1110
1
pcr 2
ext 1
2
JRNZ 4
JP 2
F
e
abc
1111
1
pcr 2
ext 1
Abbreviations for Addressing Modes: Legend:
dir
Direct
sd
Short Direct
imm
Immediate
inh
Inherent
ext
Extended
b.d
Bit Direct
bt
Bit Test
pcr
Program Counter Relative
ind
Indirect
ST6208C/ST6209C/ST6210C/ST6220C
A
B
C
1010
1011
1100
JRNC 4
RES 2
JRZ 4
e
b0,rr
e
pcr 2
b.d 1
pcr 3
JRNC 4
SET 2
JRZ 4
e
b0,rr
e
pcr 2
b.d 1
pcr 1
JRNC 4
RES 2
JRZ 4
e
b4,rr
e
pcr 2
b.d 1
pcr
JRNC 4
SET 2
JRZ 4
e
b4,rr
e
pcr 2
b.d 1
pcr 1
JRNC 4
RES 2
JRZ 2
e
b2,rr
e
pcr 2
b.d 1
pcr 1
JRNC 4
SET 2
JRZ 4
e
b2,rr
e
pcr 2
b.d 1
pcr 1
JRNC 4
RES 2
JRZ 2
e
b6,rr
e
pcr 2
b.d 1
pcr 1
JRNC 4
SET 2
JRZ 4
e
b6,rr
e
pcr 2
b.d 1
pcr 1
JRNC 4
RES 2
JRZ
e
b1,rr
e
pcr 2
b.d 1
pcr
JRNC 4
SET 2
JRZ 4
e
b1,rr
e
pcr 2
b.d 1
pcr 1
JRNC 4
RES 2
JRZ 4
e
b5,rr
e
pcr 2
b.d 1
pcr 1
JRNC 4
SET 2
JRZ 4
e
b5,rr
e
pcr 2
b.d 1
pcr 1
JRNC 4
RES 2
JRZ 2
e
b3,rr
e
pcr 2
b.d 1
pcr 1
JRNC 4
SET 2
JRZ 4
e
b3,rr
e
pcr 2
b.d 1
pcr 1
JRNC 4
RES 2
JRZ 2
e
b7,rr
e
pcr 2
b.d 1
pcr 1
JRNC 4
SET 2
JRZ 4
e
b7,rr
e
pcr 2
b.d 1
pcr 1
#
Indicates Illegal Instructions
e
5-bit Displacement
b
3-bit Address
rr
1-byte Data space address
nn
1-byte immediate data
abc
12-bit address
ee
8-bit Displacement
D
E
F
1101
1110
1111
LDI 2
JRC 4
LD
rr,nn
e
a,(y)
imm 1
prc 1
ind
DEC 2
JRC 4
LD
x
e
a,rr
sd 1
prc 2
dir
COM 2
JRC 4
CP
a
e
a,(y)
1
prc 1
ind
LD 2
JRC 4
CP
x,a
e
a,rr
sd 1
prc 2
dir
RETI 2
JRC 4
ADD
e
a,(y)
inh 1
prc 1
ind
DEC 2
JRC 4
ADD
y
e
a,rr
sd 1
prc 2
dir
STOP 2
JRC 4
INC
e
(y)
inh 1
prc 1
ind
LD 2
JRC 4
INC
y,a
e
rr
sd 1
prc 2
dir
2
JRC 4
LD
#
e
(y),a
1
prc 1
ind
DEC 2
JRC 4
LD
v
e
rr,a
sd 1
prc 2
dir
RCL 2
JRC 4
AND
a
e
a,(y)
inh 1
prc 1
ind
LD 2
JRC 4
AND
v,a
e
a,rr
sd 1
prc 2
dir
RET 2
JRC 4
SUB
e
a,(y)
inh 1
prc 1
ind
DEC 2
JRC 4
SUB
w
e
a,rr
sd 1
prc 2
dir
WAIT 2
JRC 4
DEC
e
(y)
inh 1
prc 1
ind
LD 2
JRC 4
DEC
w,a
e
rr
sd 1
prc 2
dir
Cycles
2
JRC
Operands
e
Bytes
1
prc
Addressing Mode
LOW
HI
0
0000
1
0001
2
0010
3
0011
4
0100
5
0101
6
0110
7
0111
8
1000
9
1001
A
1010
B
1011
C
1100
D
1101
E
1110
F
1111
Mnemonic
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