IC MCU 8BIT OTP 4K 20 PDIP

ST62T20CB6

Manufacturer Part NumberST62T20CB6
DescriptionIC MCU 8BIT OTP 4K 20 PDIP
ManufacturerSTMicroelectronics
SeriesST6
ST62T20CB6 datasheet
 

Specifications of ST62T20CB6

Core ProcessorST6Core Size8-Bit
Speed8MHzPeripheralsLVD, POR, WDT
Number Of I /o12Program Memory Size4KB (4K x 8)
Program Memory TypeOTPRam Size64 x 8
Voltage - Supply (vcc/vdd)3 V ~ 6 VData ConvertersA/D 8x8b
Oscillator TypeInternalOperating Temperature-40°C ~ 85°C
Package / Case20-DIP (0.300", 7.62mm)Controller Family/seriesST6
No. Of I/o's12Ram Memory Size64Byte
Cpu Speed8MHzNo. Of Timers1
Rohs CompliantYesProcessor SeriesST62T2x
CoreST6Data Bus Width8 bit
Data Ram Size64 BMaximum Clock Frequency8 MHz
Number Of Programmable I/os12Number Of Timers2
Operating Supply Voltage3 V to 6 VMaximum Operating Temperature+ 85 C
Mounting StyleThrough HoleDevelopment Tools By SupplierST622XC-KIT/110, ST62GP-EMU2, ST62E2XC-EPB/110, ST62E6XC-EPB/US, STREALIZER-II
Minimum Operating Temperature- 40 COn-chip Adc8 bit
Lead Free Status / RoHS StatusLead free / RoHS CompliantEeprom Size-
Connectivity-Other names497-2098-5
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Page 72/104

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ST6208C/ST6209C/ST6210C/ST6220C
10.5 CLOCK AND TIMING CHARACTERISTICS
Subject to general operating conditions for V
10.5.1 General Timings
Symbol
Parameter
t
Instruction cycle time
c(INST)
Interrupt reaction time
t
= Δt
v(IT)
t
+ 6
v(IT)
c(INST)
10.5.2 External Clock Source
Symbol
Parameter
V
OSC
input pin high level voltage
OSCINH
IN
V
OSC
input pin low level voltage
OSCINL
IN
I
OSCx Input leakage current
L
Notes:
1. Data based on typical application software.
2. Time measured between interrupt event and interrupt vector fetch. Δt
the current instruction execution.
Figure 49. Typical Application with an External Clock Source
V
OSCINH
V
OSCINL
Not connected
EXTERNAL
CLOCK SOURCE
72/104
1
, f
, and T
DD
OSC
A
Conditions
f
=8 MHz
CPU
2)
f
=8 MHz
CPU
Conditions
See
Figure 49
≤V
≤V
V
SS
IN
DD
90%
10%
OSC
OUT
OSC
IN
.
1)
Min
Typ
Max
2
4
5
3.25
6.5
8.125
6
11
9.75
17.875
Min
Typ
Max
0.7xV
V
DD
DD
V
0.3xV
SS
± 2
is the number of t
cycles needed to finish
c(INST)
CPU
f
OSC
I
L
ST62XX
Unit
t
CPU
μs
t
CPU
μs
Unit
V
DD
μA