ST10F269Z2Q3 STMicroelectronics, ST10F269Z2Q3 Datasheet
ST10F269Z2Q3
Specifications of ST10F269Z2Q3
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ST10F269Z2Q3 Summary of contents
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BYTE FLASH MEMORY AND 12K BYTE RAM ■ HIGH PERFORMANCE MHZ CPU WITH DSP FUNCTION – 16-bit CPU With 4-stage Pipeline – 50ns (or 62.5ns) Instruction Cycle Time at 40MHz (or 32MHz) Max CPU ...
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TABLE OF CONTENTS ST10F269 1 - Introduction ................................................................................................................. Pin Data ...................................................................................................................... Functional Description .............................................................................................. Memory Organization ............................................................................................... Internal Flash Memory .............................................................................................. 17 5.1 - OVERVIEW ................................................................................................................... 17 5.2 ...
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ST10F269 TABLE OF CONTENTS 8.4 - EXCEPTION AND ERROR TRAPS LIST ..................................................................... Capture/Compare (CAPCOM) Units ......................................................................... General Purpose Timer Unit ..................................................................................... 52 10.1 - GPT1 ............................................................................................................................. 52 10.2 - GPT2 ............................................................................................................................. ...
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TABLE OF CONTENTS 16 - Real Time Clock ..................................................................................................... 105 16.1 - RTC REGISTERS ....................................................................................................... 106 16.1.1 - RTCCON: RTC Control Register ................................................................. 106 16.1.2 - RTCPH & RTCPL: RTC PRESCALER Registers ....................................... 108 16.1.3 - RTCDH & RTCDL: RTC ...
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ST10F269 TABLE OF CONTENTS 21.4.7 - Phase Locked Loop ..................................................................................... 149 21.4.8 - External Clock Drive XTAL1 ........................................................................ 150 21.4.9 - Memory Cycle Variables ............................................................................. 151 21.4.10 - Multiplexed Bus ........................................................................................... 152 21.4.11 - Demultiplexed Bus ...................................................................................... 160 21.4.12 - ...
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... The Multiply/Accumulate unit is available as standard. This MAC unit adds powerful DSP functions to the ST10 architecture, but maintains full compatibility for existing code. – Flash control interface is now based on STMicroelectronics third stand-alone Flash memories, with an embedded Erase/Program Controller. This completely Figure 1 : Logic Symbol ...
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ST10F269 2 - PIN DATA Figure 2 : Pin Configuration (top view) 1 P6.0/CS0 2 P6.1/CS1 3 P6.2/CS2 4 P6.3/CS3 5 P6.4/CS4 6 P6.5/HOLD 7 P6.6/HLDA 8 P6.7/BREQ 9 P8.0/CC16IO 10 P8.1/CC17IO 11 P8.2/CC18IO 12 P8.3/CC19IO 13 P8.4/CC20IO 14 P8.5/CC21IO ...
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PIN DATA Symbol Pin Type P6 ... ... P8.0 - P8.7 9-16 I/O 9 I/O ... ... 16 I/O P7.0 - P7.7 ...
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ST10F269 Symbol Pin Type P2.0 - P2.7 47-54 I/O P2.8 - P2.15 57-64 47 I/O ... ... 54 I/O 57 I/O I ... ... 64 I P3.0 - P3.5 65-70, I/O P3.6 - P3.13, 73-80, I/O P3.15 81 ...
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PIN DATA Symbol Pin Type P4.0 –P4.7 85-92 I WR/WRL 96 O READY ...
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ST10F269 Symbol Pin Type P0L.0 - P0L.7, 100-107, I/O P0H.0 108, P0H.1 - P0H.7 111-117 P1L.0 - P1L.7 118-125 I/O P1H.0 - P1H.7 128-135 132 I 133 I 134 I 135 I XTAL1 138 I XTAL2 137 O RSTIN 140 ...
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PIN DATA Symbol Pin Type V 46, 72 82,93, 109, 126, 136, 144 V 18,45 55,71, 83,94, 110, 127, 139, 143 DC1 56 - DC2 17 - 12/184 Digital Supply Voltage ...
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ST10F269 3 - FUNCTIONAL DESCRIPTION The architecture of the ST10F269 combines advantages of both RISC and CISC processors and an advanced peripheral subsystem. The Figure 3 : Block Diagram 128K/256K Byte Flash Memory 10K Byte XRAM P4.5 CAN1_RXD CAN1 P4.6 ...
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MEMORY ORGANIZATION 4 - MEMORY ORGANIZATION The memory space of the ST10F269 is configured in a unified memory architecture. Code memory, data memory, registers and I/O ports are organized within the same linear address space of 16M Bytes. ...
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ST10F269 Figure 4 : ST10F269 On-chip Memory Mapping 14 05’0000 04’0000 10 0C 03’0000 02’0000 01’8000 05 04 01’0000 03 00’C000 02 00’6000 01 00’4000 00 00’0000 Data Absolute Page Memory Number Address *Reserved area for 128K ...
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MEMORY ORGANIZATION XPERCON (F024h / 12h CAN1EN CAN1 Enable Bit ‘0’: Accesses to the on-chip CAN1 XPeripheral and its functions are disabled. P4.5 and P4.6 pins ...
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ST10F269 5 - INTERNAL FLASH MEMORY 5.1 - Overview – 128K or 256K Byte on-chip Flash memory – Two possibilities of Flash mapping into the CPU address space – Flash memory can be used for code and data storage – ...
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INTERNAL FLASH MEMORY Instructions and Commands All operations besides normal read operations are initiated and controlled by command sequences written to the Flash Command Interface (CI). The Command Interface (CI) interprets words written to the Flash memory and ...
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ST10F269 be temporarily unlocked for update (write) operations. With the two possibilities for write protection - whole memory or block specific - a flexible installation of write protection is supported to protect the Flash memory or parts of it from ...
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INTERNAL FLASH MEMORY Flash Status (see note for address FSB.7 Flash Status bit 7: Data Polling Bit Programming Operation: this bit outputs the complement of the bit 7 ...
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ST10F269 5.3.5 - Flash Protection Register The Flash Protection register is a non-volatile register that contains the protection status. This register can be read by using the Read Protection Status (RP) command, and programmed by using the dedi- cated Set ...
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INTERNAL FLASH MEMORY the time-out is running; if FSB.3 is ‘1’, the time-out has expired and the EPC is erasing the block(s). 22/184 ST10F269 ...
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ST10F269 If the second command given is not an erase confirm or if the coded cycles are wrong, the instruction aborts, and the device is reset to Read Mode not necessary to program the block with 0000h as ...
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INTERNAL FLASH MEMORY Protection Status will return the new PR value only after a reset. Block Temporary Unprotection (BTU). This Instruction can be used to temporary unprotect all the blocks from Program / Erase protection. The Unprotection is ...
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ST10F269 Table 3 : Instructions Instruction Mne Cycle Read/Reset RD 1+ Read/Reset RD 3+ Program Word PW 4 Block Erase BE 6 Chip Erase CE 6 Erase Suspend ES 1 Erase Resume ER 1 Set Block/Code Protection SP 4 Read ...
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INTERNAL FLASH MEMORY 8. MEM = any address inside the Flash memory space. Absolute addressing mode must be used (MOV MEM, Rn), and instruction must be executed from Flash memory space. 9. Odd word address = 4n-2 where ...
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ST10F269 5.5.2 - Basic Flash Access Control When accessing the Flash all command write addresses have to be located within the active Flash memory space. The active Flash memory space is that logical address range which is covered by the ...
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INTERNAL FLASH MEMORY 5.5.3 - Programming Examples Most of the microcontroller programs are written in the C language where the data page pointers are automatically set by the compiler. But because the C compiler may use the not ...
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ST10F269 EXTS R11, #1 MOV [R12], R13 Data_Polling: EXTS R11, #1 MOV R7, [R12] MOV R6, R7 XOR R7, R13 JNB R7.7, Prog_OK JNB R6.5, Data_Polling EXTS R11, #1 MOV R7, [R12] XOR R7, R13 JNB R7.7, Prog_OK Prog_Error: MOV ...
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INTERNAL FLASH MEMORY Example 3 Performing the Block Erase command We assume that in the initialization phase the lowest 32K Bytes of Flash memory (sector 0) have been mapped to segment 1.The registers R11/R12 contain an address related ...
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ST10F269 .... 5.6 - Bootstrap Loader The built-in bootstrap loader (BSL) of the ST10F269 provides a mechanism to load the startup program through the serial interface after reset. In this case, no external memory or internal Flash memory is required ...
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INTERNAL FLASH MEMORY When the ST10F269 has entered BSL mode, the following configuration is automatically set (values that deviate from the normal reset values, are marked): Watchdog Timer: Disabled Context Pointer CP: FA00h Stack Pointer SP: FA40h Register ...
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ST10F269 Figure 7 : Memory Configuration after Reset Segment 255 Test Flash BSL mode active EA pin Code fetch from internal Flash area Data fetch from internal Flash area 5.6.3 - Loading the Startup Code After sending ...
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INTERNAL FLASH MEMORY 5.6.5 - Choosing the Baud Rate for the BSL The calculation of the serial Baud rate for ASC0 from the length of the first zero Byte that is received, allows the operation of the bootstrap ...
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ST10F269 6 - CENTRAL PROCESSING UNIT (CPU) The CPU includes a 4-stage instruction pipeline, a 16-bit arithmetic and logic unit (ALU) and dedi- cated SFRs. Additional hardware has been added for a separate multiply and divide unit, a bit-mask generator ...
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CENTRAL PROCESSING UNIT (CPU) The System Configuration Register SYSCON This bit-addressable register provides general system configuration and control functions. The reset value for register SYSCON depends on the state of the PORT0 pins during reset. SYSCON (FF12h / ...
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ST10F269 6.1.1 - Features 6.1.1.1 - Enhanced Addressing Capabilities – New addressing modes including a double indi- rect addressing mode with pointer post-modifi- cation. – Parallel Data Move: this mechanism allows one operand move during Multiply-Accumulate in- structions without penalty. ...
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CENTRAL PROCESSING UNIT (CPU) 6.2 - Instruction Set Summary The Table 4 lists the instructions of the ST10F269. The various addressing modes, instruction operation, parameters for conditional execution of instructions, opcodes and a detailed description of each instruc- ...
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ST10F269 Table 4 : Instruction Set Summary Mnemonic JNBS Jump relative and set bit if direct bit is not set CALLA, CALLI, CALLR Call absolute/indirect/relative subroutine if condition is met CALLS Call absolute subroutine in any code segment PCALL Push ...
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CENTRAL PROCESSING UNIT (CPU) Mnemonic CoMUL CoMULu CoMULus CoMULsu CoMUL- CoMULu- CoMULus- CoMULsu- CoMUL, rnd CoMULu, rnd CoMULus, rnd CoMULsu, rnd CoMAC CoMACu CoMACus CoMACsu CoMAC- CoMACu- CoMACus- CoMACsu- CoMAC, rnd CoMACu, rnd CoMACus, rnd CoMACsu, rnd CoMACR ...
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ST10F269 Mnemonic CoMACM CoMACMu CoMACMus CoMACMsu CoMACM- CoMACMu- CoMACMus- CoMACMsu- CoMACM, rnd CoMACMu, rnd CoMACMus, rnd CoMACMsu, rnd CoMACMR CoMACMRu CoMACMRus CoMACMRsu CoMACMR, rnd CoMACMRu, rnd CoMACMRus, rnd CoMACMRsu, rnd CoADD CoADD2 CoSUB CoSUB2 CoSUBR CoSUB2R CoMAX CoMIN CoLOAD CoLOAD- ...
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CENTRAL PROCESSING UNIT (CPU) The Table 5 shows the various combinations of pointer post-modification for each of these 2 new address- ing modes. In this document the symbols “[Rw Table 5 : Pointer Post-modification Combinations for IDXi and ...
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ST10F269 7 - EXTERNAL BUS CONTROLLER All of the external memory accesses are performed by the on-chip external bus controller. The EBC can be programmed to single chip mode when no external memory is required one of four ...
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EXTERNAL BUS CONTROLLER Figure 11 : Chip Select Delay Normal Demultiplexed Segment (P4) Address (P1) ALE Normal CSx Unlatched CSx BUS (P0) RD BUS (P0) WR 44/184 ALE Lengthen Demultiplexed Bus Cycle Data Data Read/Write Delay ST10F269 Bus ...
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ST10F269 8 - INTERRUPT SYSTEM The interrupt response time for internal program execution is from 125ns to 300ns at 40MHz CPU clock on PQFP144 devices and 156.25ns to 375ns at 32MHz of CPU clock on TQFP144 devices. The ST10F269 architecture ...
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INTERRUPT SYSTEM 8.2 - Interrupt Registers and Vectors Location List Table 7 shows all the available ST10F269 interrupt sources and the corresponding hardware-related interrupt flags, vectors, vector locations and trap (interrupt) numbers: Table 7 : Interrupt Sources Source ...
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ST10F269 Table 7 : Interrupt Sources (continued) Source of Interrupt or PEC Service Request CAPCOM Timer 1 CAPCOM Timer 7 CAPCOM Timer 8 GPT1 Timer 2 GPT1 Timer 3 GPT1 Timer 4 GPT2 Timer 5 GPT2 Timer 6 GPT2 CAPREL ...
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INTERRUPT SYSTEM xxIC (yyyyh / zzh Bit GLVL Group Level Defines the internal order for simultaneous requests of the same priority. 3: Highest group priority 0: Lowest group ...
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ST10F269 9 - CAPTURE/COMPARE (CAPCOM) UNITS The ST10F269 has two 16 channels CAPCOM units as described in Figure 12. These support generation and control of timing sequences channels with a maximum resolution of 200ns at 40MHz ...
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CAPTURE/COMPARE (CAPCOM) UNITS * The CAPCOM2 unit provides 16 capture inputs, but only 12 compare outputs. CC24I to CC27I are inputs only. Figure 13 : Block Diagram of CAPCOM Timers T0 and T7 Txl Input Control CPU X ...
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ST10F269 Table 9 : Compare Modes Compare Modes Mode 0 Interrupt-only compare mode; several compare interrupts per timer period are possible Mode 1 Pin toggles on each compare match; several compare events per timer period are possible Mode 2 Interrupt-only ...
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GENERAL PURPOSE TIMER UNIT 10 - GENERAL PURPOSE TIMER UNIT The GPT unit is a flexible multifunctional timer/ counter structure which is used for time related tasks such as event timing and counting, pulse width and duty cycle ...
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ST10F269 Table 13 : GPT1 Timer Input Frequencies, Resolution and Periods (TQFP144 devices 32MHz CPU 000b Pre-scaler factor 8 Input Freq 4MHz Resolution 250ns Period maximum 16.4ms Figure 15 : Block Diagram of GPT1 T2EUD CPU Clock n ...
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GENERAL PURPOSE TIMER UNIT Resolution and Period (TQFP144 devices) list the timer input frequencies, resolution and periods for each pre-scaler option at 40MHz (or 32MHz) CPU clock. This also applies to the Gated Timer Mode of T6 and ...
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ST10F269 Figure 16 : Block Diagram of GPT2 T5EUD CPU Clock n 2 n=2...9 T5IN CAPIN T6IN CPU Clock n 2 n=2...9 T6EUD 10 - GENERAL PURPOSE TIMER UNIT U/D T5 GPT2 Timer T5 Mode Control Clear Capture GPT2 CAPREL ...
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PWM MODULE 11 - PWM MODULE The pulse width modulation module can generate up to four PWM output signals using edge-aligned or centre-aligned PWM. In addition, the PWM module can generate PWM burst signals and Figure 17 : ...
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ST10F269 12 - PARALLEL PORTS 12.1 - Introduction The ST10F269 MCU provides up to 111 I/O lines with programmable features. These capabilities bring very flexible adaptation of this MCU to wide range of applications. ST10F269 has 9 groups of I/O ...
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PARALLEL PORTS Figure 18 : SFRs and Pins Associated with the Parallel Ports 58/184 ST10F269 ...
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ST10F269 12.2 - I/O’s Special Features 12.2.1 - Open Drain Mode Some of the I/O ports of ST10F269 support the open drain capability. This programmable feature may be used with an external pull-up resistor, in order to get an AND ...
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PARALLEL PORTS Figure 20 : Hysteresis for Special Input Thresholds Hysteresis Input level Bit state 12.2.3 - Output Driver Control The port output control registers POCONx allow to select the port output driver characteristics of a port. The ...
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ST10F269 The table lists the defined POCON registers and the allocation of control bit-fields and port pins. Table 18 : Port Control Register Allocation Control Physical Register Address Address POCON0L F080h POCON0H F082h POCON1L F084h POCON1H F086h POCON2 F088h POCON3 ...
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PARALLEL PORTS 12.2.4 - Alternate Port Functions Each port line has one associated programmable alternate input or output function. – PORT0 and PORT1 may be used as address and data lines when accessing external memory. – Port 2, ...
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ST10F269 12.3 - PORT0 The two 8-bit ports P0H and P0L represent the higher and lower part of PORT0, respectively. Both halves of PORT0 can be written (via a PEC transfer) without effecting the other half. P0L (FF00h / 80h) ...
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PARALLEL PORTS 12.3.1 - Alternate Functions of PORT0 When an external bus is enabled, PORT0 is used as data bus or address/data bus. Note that an external 8-bit demultiplexed bus only uses P0L, while P0H is free for ...
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ST10F269 When an external bus mode is enabled, the direction of the port pin and the loading of data into the port output latch are controlled by the bus controller hardware. The input of the port output Buffer is disconnected ...
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PARALLEL PORTS 12.4 - PORT1 The two 8-bit ports P1H and P1L represent the higher and lower part of PORT1, respectively. Both halves of PORT1 can be written (via a PEC transfer) without effecting the other half. If ...
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ST10F269 Figure 23 : PORT1 I/O and Alternate Functions Alternate Function P1H.7 P1H.6 P1H.5 P1H.4 P1H P1H.3 P1H.2 P1H.1 P1H.0 PORT1 P1L.7 P1L.6 P1L.5 P1L.4 P1L P1L.3 P1L.2 P1L.1 P1L.0 General Purpose Input/Output When an external bus mode is enabled, ...
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PARALLEL PORTS 12.5 - Port 2 If this 16-bit port is used for general purpose I/O, the direction of each line can be configured via the corresponding direction register DP2. Each port line can be switched into push/pull ...
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ST10F269 the output latch is clocked by the signal “Compare Trigger”. The direction of the pin should be set to output by the user, otherwise the pin will be in the high-impedance state and will not reflect the state of ...
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PARALLEL PORTS Figure 25 : Port 2 I/O and Alternate Functions Alternate Function P2.15 P2.14 P2.13 P2.12 P2.11 P2.10 P2.9 P2.8 Port 2 P2.7 P2.6 P2.5 P2.4 P2.3 P2.2 P2.1 P2.0 General Purpose Input / Output Capture Input ...
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ST10F269 The pins of Port 2 combine internal bus data with alternate data output before the port latch input. Figure 26 : Block Diagram of a Port 2 Pin Write ODP2.y Open Drain Latch Read ODP2.y Write DP2.y Direction Latch ...
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PARALLEL PORTS (pins P3.15, P3.14 and P3.12 do not support open drain mode). P3 (FFC4h / E2h P3.15 - P3.13 P3.12 P3.11 P3.10 P3 P3.y Port Data Register ...
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ST10F269 12.6.1 - Alternate Functions of Port 3 The pins of Port 3 serve for various functions which include external timer control lines, the two serial interfaces and the control lines BHE/WRH and CLKOUT. Table 20 : Port 3 Alternative ...
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PARALLEL PORTS When the on-chip peripheral associated with a Port 3 pin is configured to use both the alternate input and output function, the descriptions above apply to the respective current operating mode. The direction must be set ...
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ST10F269 Pin P3.12 (BHE/WRH) is another pin with an alternate output function, however, its structure is slightly different. After reset the BHE or WRH function must be used depending on the configuration. In either of these cases, there is no ...
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PARALLEL PORTS 12.7 - Port 4 If this 8-bit port is used for general purpose I/O, the direction of each line can be configured via the corresponding direction register DP4. P4 (FFC8h / E4h ...
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ST10F269 12.7.1 - Alternate Functions of Port 4 During external bus cycles that use segmentation (address space above 64K Bytes) a number of Port 4 pins may output the segment address lines. The number of pins that is used for ...
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PARALLEL PORTS Figure 31 : Block Diagram of a Port 4 Pin Write DP4.y Direction Latch Read DP4.y Write P4.y Port Output Latch Read P4.y 78/184 1 “1” MUX 0 Alternate Function Enable Alternate Data 1 Output MUX ...
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ST10F269 Figure 32 : Block Diagram of P4.4 and P4.5 Pins Write DP4.x Direction Latch Read DP4.x Write P4.x Port Output Latch Read P4.x CANy.RxD XPERCON.a (CANyEN) XPERCON.b (CANzEN) 1 “1” MUX 0 “0” 1 MUX Alternate Function 0 Enable ...
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PARALLEL PORTS Figure 33 : Block Diagram of P4.6 and P4.7 Pins Write ODP4.x Open Drain Latch Read ODP4.x Write DP4.x Direction Latch Read DP4.x Write P4.x Port Output Latch Read P4.x CANy.TxD Data output XPERCON.a (CANyEN) XPERCON.b ...
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ST10F269 12.8.1 - Alternate Functions of Port 5 Each line of Port 5 is also connected to one of the multiplexer of the Analog/Digital Converter. All port lines (P5.15...P5.0) can accept analog signals (AN15...AN0 converted by the ADC. ...
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PARALLEL PORTS Port 5 pins have a special port structure (see Figure 35), first because input only port, and second because the analog input channels are directly connected to the pins rather than to the ...
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ST10F269 DP6.y Port Direction Register DP6 Bit y DP6 Port line P6 input (high impedance) DP6 Port line P6 output ODP6 (F1CEH / E7H ...
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PARALLEL PORTS The chip select lines of Port 6 have an internal weak pull-up device. This device is switched on during reset. This feature is implemented to drive the chip select lines high during reset in order to ...
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ST10F269 Figure 38 : Block Diagram of Pin P6.5 (HOLD) Write ODP6.5 Open Drain Latch Read ODP6.5 Write DP6.5 Direction Latch Read DP6.5 Write P6.5 Port Output Latch Read P6.5 Alternate Data Input Clock 1 MUX Input 0 Latch 12 ...
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PARALLEL PORTS 12.10 - Port 7 If this 8-bit port is used for general purpose I/O, the direction of each line can be configured via the corresponding direction register DP7. Each port line can be switched into push-pull ...
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ST10F269 12.10.1 - Alternate Functions of Port 7 The upper 4 lines of Port 7 (P7.7...P7.4) serve as capture inputs or compare (CC31IO...CC28IO) for the CAPCOM2 unit. The usage of the port lines by the CAPCOM unit, its accessibility via ...
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PARALLEL PORTS The structure of Port 7 differs in the way the output latches are connected to the internal bus and to the pin driver. Pins P7.3...P7.0 (POUT3...POUT0) Figure 40 : Block Diagram of Port 7 Pins P7.3...P7.0 ...
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ST10F269 Figure 41 : Block Diagram of Port 7 Pins P7.7...P7.4 Write ODP7.y Open Drain Latch Read ODP7.y Write DP7.y Direction Latch Read DP7.y 1 MUX Alternate Data 0 Output Write Port P7.y Compare Trigger Read P7.y Output Latch 1 ...
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PARALLEL PORTS 12.11 - Port 8 If this 8-bit port is used for general purpose I/O, the direction of each line can be configured via the P8 (FFD4h / EAh ...
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ST10F269 12.11.1 - Alternate Functions of Port 8 The 8 lines of Port 8 serve as capture inputs or as compare outputs (CC23IO...CC16IO) for the CAPCOM2 unit. The usage of the port lines by the CAPCOM unit, its accessibility via ...
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PARALLEL PORTS The structure of Port 8 differs in the way the output latches are connected to the internal bus and to the pin driver (see Figure 43). Pins P8.7...P8.0 Figure 43 : Block Diagram of Port 8 ...
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ST10F269 13 - A/D CONVERTER A 10-bit A/D converter with 16 multiplexed input channels and a sample and hold circuit is integrated on-chip. The sample time (for loading the capacitors) and the conversion time is programmable and can be adjusted ...
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A/D CONVERTER Table 27 : ADC Sample Clock and Conversion Clock (TQFP144 devices) Conversion Clock t ADCON 15/14 ADCTC 1 TCL = 1 TCL Reserved, do not use 10 TCL x 96 ...
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ST10F269 14 - SERIAL CHANNELS Serial communication with other microcontrollers, microprocessors, terminals or external peripheral components is provided by two serial interfaces: the asynchronous / synchronous serial channel (ASCO) and the high-speed synchronous serial channel (SSC). Two dedicated generators set ...
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SERIAL CHANNELS Asynchronous Mode Baud rates For asynchronous operation, the Baud rate generator provides a clock with 16 times the rate of the established Baud rate. Every received bit is sampled at the 7th, 8th and 9th cycle ...
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ST10F269 Table 29 : Commonly Used Baud Rates by Reload Value and Deviation Errors (TQFP144 devices) S0BRS = ‘0’, f CPU Baud Rate (Baud) Deviation Error 1000 000 0.0% 56000 +5.0% / -0.8% 38400 +0.2% / -3.5% 19200 +0.2% / ...
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SERIAL CHANNELS 14.1.2 - ASCO in Synchronous Mode In synchronous mode, data are transmitted or received synchronously to a shift clock which is generated by the ST10F269. Half-duplex communication Baud (at 40MHz f possible in ...
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ST10F269 Synchronous Mode Baud Rates For synchronous operation, the Baud rate generator provides a clock with 4 times the rate of the established Baud rate. The Baud rate for synchronous operation of serial channel ASC0 can be determined by the ...
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SERIAL CHANNELS Table 31 : Commonly Used Baud Rates by Reload Value and Deviation Errors (TQFP144 devices) S0BRS = ‘0’, f CPU Baud Rate (Baud) Deviation Error 4 000 000 0.0% 224 000 +5.0% / -0.8% 112 000 ...
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ST10F269 14.2 - High Speed Synchronous Serial Channel (SSC) The High-Speed Synchronous Serial Interface SSC provides flexible communication between the ST10F269 and other microcontrollers, microprocessors or external peripherals. The SSC supports full-duplex and half-duplex synchronous communication. The serial clock signal ...
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SERIAL CHANNELS Baud Rate Generation The Baud rate generator is clocked by f timer is counting downwards and can be started or stopped through the global enable bit SSCEN in register SSCCON. Register SSCBR is the dual-function Baud ...
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ST10F269 15 - CAN MODULES The two integrated CAN modules (CAN1 and CAN2) are identical and handle the completely autonomous transmission and reception of CAN frames according to the CAN specification V2.0 part B (active). Each on-chip CAN module can ...
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CAN MODULES The ST10F269 also supports single CAN Bus multiple (dual) interfaces using the open drain option of the CANx_TxD output as shown in Figure 48. Thanks to the OR-Wired Connection, only one transceiver is required. In this ...
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ST10F269 16 - REAL TIME CLOCK The Real Time Clock is an independent timer, which clock is directly derived from the clock oscillator on XTAL1 input so that it can keep on running even in Idle or Power down mode ...
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REAL TIME CLOCK Figure 51 : RTC Block Diagram AlarmIT Programmable ALARM Register RTCAH RTCH 32 bit COUNTER 16.1 - RTC registers 16.1.1 - RTCCON: RTC Control Register The functions of the RTC are controlled by the RTCCON ...
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ST10F269 mode. 2. All the bit of RTCCON are active high REAL TIME CLOCK 107/184 ...
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REAL TIME CLOCK 16.1.2 - RTCPH & RTCPL: RTC PRESCALER Registers The 20-bit programmable prescaler divider is loaded with 2 registers. The 4 most significant bit are stored into RTCPH and the 16 Less significant bit are stored ...
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ST10F269 When RTCD increments to reach 00000h, The 20-bit word stored into RTCPH, RTCPL registers is loaded in RTCD. Figure 53 : DIVIDER Counters RTCDH ...
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REAL TIME CLOCK 16.1.5 - RTCAH & RTCAL: RTC ALARM Registers When the programmable counters reach the 32-bit value stored into RTCAH & RTCAL registers, an alarm is triggered and the interrupt request RTAIR is generated. Those registers ...
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ST10F269 Interrupt control registers are common with CAPCOM1 Unit: CC10IC (RTCSI) and CC11IC (RTCAI). CCxIC CC10IC: FF8Ch/C6h CC11IC: FF8Eh/C7h Source of interrupt Request Flag External interrupt 2 CC10IR External interrupt ...
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WATCHDOG TIMER 17 - WATCHDOG TIMER The Watchdog Timer is a fail-safe mechanism which prevents the microcontroller malfunctioning for long periods of time. The Watchdog Timer is always enabled after a reset of the chip and can only ...
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ST10F269 The PONR flag of WDTCON register is set if the output voltage of the internal 3.3V supply falls below the threshold (typically 2V) of the power-on detection circuit. This circuit is efficient to detect major failures of the external ...
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SYSTEM RESET 18 - SYSTEM RESET System reset initializes the MCU in a predefined state. There are five ways to activate a reset state. Reset Source Power-on reset Long Hardware reset (synchronous & asynchronous) Short Hardware reset (synchronous ...
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ST10F269 Figure 55 : Asynchronous Reset Sequence Internal Fetch CPU Clock Asynchronous Reset Condition RSTIN RPD RSTOUT PORT0 PLL factor latch command Internal reset signal INTERNAL FETCH Flash read signal Note: 1) RSTIN rising edge to internal latch of PORT0 ...
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SYSTEM RESET low. The reset is processed as an asynchronous reset. Figure 56 : Synchronous Reset Sequence External Fetch (RSTIN pulse > 1040 TCL) 4 TCL 12 TCL min. max. CPU Clock RSTIN RPD 200 A Discharge RSTOUT ...
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ST10F269 maximum of 1038 TCL (4 TCL + 10 TCL + 1024 TCL). The system configuration is latched from PORT0 after a duration of 8 TCL / 4 CPU clocks (6 TCL / 3 CPU clocks if PLL is bypassed) ...
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SYSTEM RESET programmed wait states. When READY is sampled inactive (high) after the programmed wait states the running external bus cycle is aborted. Then the internal reset sequence (1024 TCL) is started. The microcontroller behaviour is the same ...
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ST10F269 Depending on the delay of the next applied reset, the MCU can enter a synchronous reset or an asynchronous reset. If RPD pin is below 2.5V an asynchronous reset starts, if RPD pin is above 2.5V a synchronous reset ...
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SYSTEM RESET Figure 59 : Minimum External Reset Circuitry V DD ST10F269 R0 RPD + C0 Figure 60 : External Reset Hardware Circuitry V DD RSTOUT R0 ST10F269 RPD + C0 Table 38 : PORT0 Latched Configuration for ...
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ST10F269 3. Indirectly depend on PORT0. 4. Bits set if EA pin SYSTEM RESET 121/184 ...
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POWER REDUCTION MODES 19 - POWER REDUCTION MODES Two different power reduction modes with different levels of power reduction have been implemented in the ST10F269. In Idle mode only CPU is stopped, while peripheral still operate. In Power ...
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ST10F269 EXIxES(x=7...0) External Interrupt x Edge Selection Field (x=7... Interrupt on positive edge (rising) Enter Power Down mode if EXiIN = ‘0’, exit if EXxIN = ‘1’ (referred as ‘high’ active level Interrupt on negative edge ...
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POWER REDUCTION MODES Figure 62 : Simplified Powerdown Exit Circuitry enter PowerDown external interrupt reset Figure 63 : Powerdown Exit Sequence When Using an External Interrupt (PLL x 2) XTAL1 CPU clk Internal Powerdown signal External Interrupt RPD ...
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ST10F269 20 - SPECIAL FUNCTION REGISTER OVERVIEW The following table lists all SFRs which are implemented in the ST10F269 in alphabetical order. Bit-addressable SFRs are marked with the letter “b” in column “Name”. SFRs within the Extended SFR-Space (ESFRs) are ...
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SPECIAL FUNCTION REGISTER OVERVIEW Table 40 : Special Function Registers Listed by Name (continued) Physical Name address CC9 FE92h CC9IC b FF8Ah CC10 FE94h CC10IC b FF8Ch CC11 FE96h CC11IC b FF8Eh CC12 FE98h CC12IC b FF90h CC13 ...
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ST10F269 Table 40 : Special Function Registers Listed by Name (continued) Physical Name address CC30 FE7Ch CC30IC b F18Ch E CC31 FE7Eh CC31IC b F194h E CCM0 b FF52h CCM1 b FF54h CCM2 b FF56h CCM3 b FF58h CCM4 b ...
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SPECIAL FUNCTION REGISTER OVERVIEW Table 40 : Special Function Registers Listed by Name (continued) Physical Name address MDL FE0Eh MRW b FFDAh MSW b FFDEh ODP2 b F1C2h E ODP3 b F1C6h E ODP4 b F1CAh E ODP6 ...
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ST10F269 Table 40 : Special Function Registers Listed by Name (continued) Physical Name address PP0 F038h E PP1 F03Ah E PP2 F03Ch E PP3 F03Eh E PSW b FF10h PT0 F030h E PT1 F032h E PT2 F034h E PT3 F036h ...
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SPECIAL FUNCTION REGISTER OVERVIEW Table 40 : Special Function Registers Listed by Name (continued) Physical Name address T0IC b FF9Ch T0REL FE54h T1 FE52h T1IC b FF9Eh T1REL FE56h T2 FE40h T2CON b FF40h T2IC b FF60h T3 ...
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... A manufacturer identifier, – A chip identifier, with its revision, – A internal memory and size identifier and pro- gramming voltage description. 1 IDMANUF (F07Eh / 3Fh MANUF Manufacturer Identifier - 020h: STMicroelectronics Manufacturer (JTAG worldwide normalization). 1 IDCHIP (F07Ch / 3Eh REVID Device Revision Identifier CHIPID Device Identifier - 10Dh: ST10F269 identifier. ...
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SPECIAL FUNCTION REGISTER OVERVIEW 20.2 - System Configuration Registers The ST10F269 has registers used for different configuration of the overall system. These registers are described below. SYSCON (FF12h / 89h STKSZ ROMS1 ...
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ST10F269 ‘0’: Pins WR and BHE retain their normal function ‘1’: Pin WR acts as WRL, pin BHE acts as WRH. CLKEN System Clock Output Enable (CLKOUT) ‘0’: CLKOUT disabled: pin may be used for general purpose I/O ‘1’: CLKOUT ...
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SPECIAL FUNCTION REGISTER OVERVIEW BUSCON4 (FF1Ah / 8Dh CSWEN4 CSREN4 RDYPOL4 RDYEN4 Notes: 1. BTYP (bit 6 and 7) are set according to the configuration of the bit l6 and l7 of ...
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ST10F269 RP0H (F108h / 84h Write Configuration Control WRC ‘0’: Pin WR acts as WRL, pin BHE acts as WRH ‘1’: Pins WR and BHE retain their normal function ...
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SPECIAL FUNCTION REGISTER OVERVIEW EXICON (F1C0h / E0h EXI7ES EXI6ES RW RW EXIxES(x=7...0) External Interrupt x Edge Selection Field (x=7... Fast external interrupts disabled: standard mode EXxIN pin not taken in ...
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ST10F269 xxIC (yyyyh / zzh Bit GLVL Group Level Defines the internal order for simultaneous requests of the same priority. 3: Highest group priority 0: Lowest group priority ILVL Interrupt ...
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SPECIAL FUNCTION REGISTER OVERVIEW ’1’: The on-chip Real Time Clock is enabled and can be accessed. When both CAN are disabled via XPERCON setting, then any access in the address range 00’EE00h - 00’EFFFh will be directed to ...
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ST10F269 21 - ELECTRICAL CHARACTERISTICS 21.1 - Absolute Maximum Ratings Symbol V Voltage on V pins with respect to ground Voltage on any pin with respect to ground IO V Voltage on V pin with respect to ...
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ELECTRICAL CHARACTERISTICS Symbol V CC Output low voltage (all other outputs) OL1 Output high voltage (PORT0, PORT1, Port4 ALE, RD, WR, BHE, CLKOUT, RSTOUT Output high voltage (all other outputs) OH1 I CC ...
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ST10F269 Symbol Power-down mode supply current (Real time I PD2 clock enabled, oscillator enabled) Notes: 1. ST10F269 pins are equipped with low-noise output drivers which significantly improve the device’s EMI performance. These low-noise drivers deliver their maximum current only until ...
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ELECTRICAL CHARACTERISTICS Figure 64 : Supply / Idle Current as a Function of Operating Frequency (PQFP144 devices) I [mA] 100 142/184 120mA 60mA 20 30 ST10F269 I CCmax I CCtyp I IDmax I IDtyp 40 ...
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ST10F269 Figure 65 : Supply / Idle Current as a Function of Operating Frequency (TQFP144 devices) I [mA] 100 ELECTRICAL CHARACTERISTICS CCmax 93.6mA I CCtyp 52mA I IDmax I IDtyp 30 f ...
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A/D Converter Characteristics ± 10 0.2V AGND SS Table 41 : A/D Converter Characteristics Symbol V SR Analog Reference voltage AREF V SR Analog input ...
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ST10F269 21.3.2 - Conversion Timing Control When a conversion is capacitances of the converter are loaded via the respective analog input pin to the current analog input voltage. The time to load the capacitances is referred to as the sample ...
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Table 43 : ADC Sampling and Conversion Timing (TQFP144 devices) Conversion Clock t ADCON.15/14 ADCTC TCL = 1 TCL Reserved, do not use 10 TCL TCL complete conversion ...
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ST10F269 between two consecutive edges of the CPU clock, called “TCL”. The CPU clock signal can be generated by different mechanisms. The duration of TCL and its variation (and also the derived external timing) The mechanism used to generate the ...
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Clock Generation Modes The Table 44 associates the combinations of these three bits with the respective clock generation mode. Table 44 : CPU Frequency Generation (PQFP144 devices) P0H.7 P0H.6 P0H.5 CPU Frequency ...
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ST10F269 21.4.4 - Prescaler Operation When pins P0.15-13 (P0H.7-5) equal ’001’ during reset, the CPU clock is derived from the internal oscillator (input clock signal 2:1 prescaler. The frequency half the frequency of CPU f ...
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The real minimum value for TCL depends on the jitter of the PLL. The PLL tunes f locked The relative deviation of TCL is XTAL the maximum when it is referred to one TCL period. It decreases ...
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ST10F269 10 0V Parameter Symbol Oscillator period t SR OSC High time Low time Rise time Fall time ...
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Multiplexed Bus 10 0V ALE cycle time = 6 TCL + Table 46 : Multiplexed Bus Characteristics (PQFP144 devices) Symbol Parameter t CC ALE high time ...
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ST10F269 Table 46 : Multiplexed Bus Characteristics (PQFP144 devices) Symbol Parameter t CC ALE fall. edge to RdCS, WrCS 42 (with RW delay ALE fall. edge to RdCS, WrCS 43 (no RW delay Address float after ...
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Symbol Parameter t ALE falling edge to RD, WR (no 9 RW-delay Address float after RD (with RW-delay Address float after RD (no RW-delay RD, WR low time 12 (with ...
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ST10F269 Symbol Parameter t Address float after RdCS, 44 WrCS (with RW delay Address float after RdCS, 45 WrCS (no RW delay RdCS to Valid Data In 46 (with RW delay RdCS to Valid ...
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Figure 71 : External Memory Cycle: Multiplexed Bus, With / Without Read / Write Delay, Normal ALE CLKOUT ALE t 6 CSx A23-A16 (A15-A8) BHE Read Cycle Address/Data Bus (P0) RD Write Cycle Address/Data Bus (P0) WR WRL WRH 156/184 ...
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ST10F269 Figure 72 : External Memory Cycle: Multiplexed Bus, With / Without Read / Write Delay, Extended ALE CLKOUT t 5 ALE t 6 CSx t 6 A23-A16 (A15-A8) BHE Read Cycle t 6 Address/Data Bus (P0) RD Write Cycle ...
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Figure 73 : External Memory Cycle: Multiplexed Bus, With / Without Read / Write Delay, Normal ALE, Read / Write Chip Select CLKOUT ALE t A23-A16 (A15-A8) BHE Read Cycle Address/Data Bus (P0) RdCSx Write Cycle Address/Data Bus (P0) WrCSx ...
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ST10F269 Figure 74 : External Memory Cycle: Multiplexed Bus, With / Without Read / Write Delay, Extended ALE, Read / Write Chip Select CLKOUT t ALE t 6 A23-A16 (A15-A8) BHE Read Cycle t 6 Address/Data Bus (P0) RdCSx Write ...
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Demultiplexed Bus 10 0V 50pF, Table 48 : Demultiplexed Bus Characteristics (PQFP144 devices) Symbol Parameter t CC ALE high time Address setup to ALE 6 ...
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ST10F269 Table 48 : Demultiplexed Bus Characteristics (PQFP144 devices) Symbol Parameter t CC Latched CS hold after RD Address setup to RdCS, WrCS 82 (with RW-delay Address setup to RdCS, WrCS 83 (no RW-delay) ...
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Symbol Parameter t CC Address/Unlatched CS setup 81 to RD, WR (no RW-delay RD, WR low time 12 (with RW-delay RD, WR low time 13 (no RW-delay valid data in 14 (with ...
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ST10F269 Symbol Parameter t CC RdCS, WrCS Low Time 48 (with RW-delay RdCS, WrCS Low Time 49 (no RW-delay Data valid to WrCS Data hold after RdCS Data float after ...
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Figure 75 : External Memory Cycle: Demultiplexed Bus, With / Without Read / Write Delay, Normal ALE CLKOUT ALE CSx A23-A16 A15-A0 (P1) BHE Read Cycle Data Bus (P0) (D15-D8) D7-D0 RD Write Cycle Data Bus (P0) (D15-D8) D7-D0 WR ...
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ST10F269 Figure 76 : External Memory Cycle: Demultiplexed Bus, With / Without Read / Write Delay, Extended ALE CLKOUT t ALE t CSx A23-A16 A15-A0 (P1) BHE Read Cycle Data Bus (P0) (D15-D8) D7-D0 RD Write Cycle Data Bus (P0) ...
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Figure 77 : External Memory Cycle: Demultiplexed Bus, With / Without Read / Write Delay, Normal ALE, Read / Write Chip Select CLKOUT ALE A23-A16 A15-A0 (P1) BHE Read Cycle Data Bus (P0) (D15-D8) D7-D0 RdCSx Write Cycle Data Bus ...
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ST10F269 Figure 78 : External Memory Cycle: Demultiplexed Bus, no Read / Write Delay, Extended ALE, Read / Write Chip Select CLKOUT t ALE A23-A16 A15-A0 (P1) BHE Read Cycle Data Bus (P0) (D15-D8) D7-D0 RdCSx Write Cycle Data Bus ...
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CLKOUT and READY 10 0V Table 50 : CLKOUT and READY Characteristics (PQFP144 devices) Symbol Parameter t CC CLKOUT cycle time CLKOUT high time ...
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ST10F269 10 0V Table 51 : CLKOUT and READY Characteristics (TQFP144 devices) Symbol Parameter t CC CLKOUT cycle time CLKOUT high time CLKOUT low time 31 ...
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Figure 79 : CLKOUT and READY t 32 CLKOUT ALE RD, WR Synchronous READY t 58 Asynchronous READY 3) Notes: 1. Cycle as programmed, including MCTC wait states (Example shows 0 MCTC WS). 2. The leading edge of the respective ...
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ST10F269 21.4.13 - External Bus Arbitration 10 0V Symbol Parameter t HOLD input setup time CLKOUT t CLKOUT to HLDA high BREQ low delay t CLKOUT ...
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Figure 80 : External Bus Arbitration (Releasing the Bus) CLKOUT t 61 HOLD HLDA BREQ CSx (P6.x) Others Notes: 1. The ST10F269 will complete the currently running bus cycle before granting bus access. 2. This is the first possibility ...
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ST10F269 Figure 81 : External Bus Arbitration (Regaining the Bus) CLKOUT HOLD HLDA t 62 BREQ CSx (On P6.x) Other Signals Notes: 1. This is the last chance for BREQ to trigger the indicated regain-sequence. Even if BREQ is activated ...
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High-Speed Synchronous Serial Interface (SSC) Timing 21.4.14.1 Master Mode ±10 0V, CPU clock = 40MHz Symbol Parameter t CC SSC clock cycle time 300 t CC SSC clock high time ...
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ST10F269 Symbol Parameter t SR Read data hold time after latch edge, 318 phase error detection off (SSCPEN = 0) Note: 1. Timing guaranteed by design. The formula for SSC Clock Cycle time Where <SSCBR> represents the ...
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Symbol Parameter SR Read data setup time before latch t 317 edge, phase error (SSCPEN = Read data hold time after latch edge, 318 phase error (SSCPEN = 0) The formula for SSC Clock Cycle time is: ...
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ST10F269 Figure 83 : SSC Slave Timing t 310 1) SCLK t 315 MRST 1st Out Bit t 317 1st.In Bit MTSR Notes: 1. The phase and polarity of shift and latch edge of SCLK is programmable. This figure uses ...
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PACKAGE MECHANICAL DATA 22 - PACKAGE MECHANICAL DATA Figure 84 : Package Outline PQFP144 (28 x 28mm) 144 Dimensions Minimum A A1 0.25 A2 3.17 B 0.22 c 0.13 D 30.95 D1 27. ...
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ST10F269 Figure 85 : Package Outline TQFP144 ( 1.40 mm) 144 Dimensions Minimum A A1 0.05 A2 1.35 B 0. ...
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... ORDERING INFORMATION 23 - ORDERING INFORMATION Flash Program Salestype ST10F269Z2Q3 ST10F269Z2Q6 ST10F269Z2T3 ST10F269Z2T6 ST10F269Z1Q3 ST10F269Z1Q6 ST10F269Z1T3 ST10F269Z1T6 180/184 Memory Temperature range (Bytes) 256K -40°C to +125°C 256K -40°C to +85°C 256K -40°C to +125°C 256K -40°C to +85°C 128K -40°C to +125°C 128K -40° ...
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DESCRIPTION This Errata sheet describes the functional and electrical problems known in the D revision of the ST10F269Zxxx. The revision number can be found in the third line on the ST10F269 package. It looks like: ’xxxxxxxxx D’ where ...
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FUNCTIONAL PROBLEMS 2.2 - MAC.9 - CoCMP Instruction Inverted Operands The ST10 Family Programming Manual describes the CoCMP instruction as: subtracts a 40-bit signed operand from th 40-bit accumulator content (acc - op2\op1), and updates the N, Z ...
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ST10F269 2.4 - ST_PORT.3 - Bad Behavior of Hysteresis Function on Input Falling Edge In the following conditions, a slow falling edge on a ST10F269 input may generate multiple events : – A falling edge is occuring. – AND the ...
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... No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without the express written approval of STMicroelectronics ...