MC908JB8ADWE Freescale Semiconductor, MC908JB8ADWE Datasheet

Page 1

MC68HC908JB8 MC68HC08JB8 MC68HC08JT8 Technical Data M68HC08 Microcontrollers MC68HC908JB8/D Rev. 2.3 9/2005 freescale.com ...

Page 2

...

Page 3

... For your convenience, the page number designators have been linked to the appropriate location. Freescale and the Freescale logo are registered trademarks of Freescale Semiconductor, Inc. This product incorporates SuperFlash® technology licensed from SST. © Freescale Semiconductor, Inc., 2005. All rights reserved. ...

Page 4

... Table 12-1 . Port Control Register Bits Characteristics. Appendix A. MC68HC08JB8 — ROM part. Appendix B. MC68HC08JT8 — low-voltage ROM part. MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3 Page Number(s) 267, 284 Throughout 61 149, 150 153 263 28, 210, 217 146 159 177 Summary. 201 256 266 269 277 Freescale Semiconductor ...

Page 5

... Section 16. Low Voltage Inhibit (LVI 243 Section 17. Break Module (BREAK 245 Section 18. Electrical Specifications 253 Section 19. Mechanical Specifications . . . . . . . . . . . . . 263 Section 20. Ordering Information . . . . . . . . . . . . . . . . . 267 Appendix A. MC68HC08JB8 . . . . . . . . . . . . . . . . . . . . . . 269 Appendix B. MC68HC08JT8 . . . . . . . . . . . . . . . . . . . . . . 277 MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3 Freescale Semiconductor List of Sections List of Sections Technical Data 5 ...

Page 6

... List of Sections Technical Data 6 MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3 List of Sections Freescale Semiconductor ...

Page 7

... MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3 Freescale Semiconductor Section 1. General Description Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Power Supply Pins (V DD Voltage Regulator Out (V Oscillator Pins (OSC1 and OSC2 External Reset Pin (RST External Interrupt Pins (IRQ, PTE4/D– ...

Page 8

... FLASH Block Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . . 56 FLASH Mass Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . . 57 FLASH Program Operation .58 FLASH Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 FLASH Block Protect Register . . . . . . . . . . . . . . . . . . . . . . . 60 ROM-Resident Routines Variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 ERASE Routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 PROGRAM Routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 VERIFY Routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Section 5. Configuration Register (CONFIG) Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3 Table of Contents Freescale Semiconductor ...

Page 9

... MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3 Freescale Semiconductor Section 6. Central Processor Unit (CPU) Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Condition Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Arithmetic/Logic Unit (ALU Low-Power Modes ...

Page 10

... Interrupt Status Registers 108 Interrupt Status Register 109 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Status Flag Protection in Break Mode . . . . . . . . . . . . . . . . 110 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112 SIM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3 Table of Contents Freescale Semiconductor ...

Page 11

... MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3 Freescale Semiconductor Break Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 Reset Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 Break Flag Control Register . . . . . . . . . . . . . . . . . . . . . . .116 Section 9. Universal Serial Bus Module (USB) Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 Pin Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 Functional Description ...

Page 12

... End-of-Packet Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 Section 10. Monitor ROM (MON) Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .163 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .164 Entering Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 Baud Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .169 Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 Echoing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 Break Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3 Table of Contents Freescale Semiconductor ...

Page 13

... TIM Counter Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 11.10.3 TIM Counter Modulo Registers . . . . . . . . . . . . . . . . . . . . . 193 11.10.4 TIM Channel Status and Control Registers . . . . . . . . . . . . 194 11.10.5 TIM Channel Registers 198 MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3 Freescale Semiconductor Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 Security 175 Section 11. Timer Interface Module (TIM) Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .177 Introduction ...

Page 14

... Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .220 IRQ Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 PTE4/D– Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 IRQ Module During Break Interrupts . . . . . . . . . . . . . . . . . . . 223 IRQ Status and Control Register . . . . . . . . . . . . . . . . . . . . . . 224 IRQ Option Control Register 225 MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3 Table of Contents Freescale Semiconductor ...

Page 15

... MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3 Freescale Semiconductor Section 14. Keyboard Interrupt Module (KBI) Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .227 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228 Pin Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .230 Keyboard Initialization 231 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .232 Stop Mode ...

Page 16

... Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .248 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .249 Break Module Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 Break Status and Control Register 249 Break Address Registers . . . . . . . . . . . . . . . . . . . . . . . . . . 250 Break Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 Break Flag Control Register (BFCR 252 MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3 Table of Contents Freescale Semiconductor ...

Page 17

... MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3 Freescale Semiconductor Section 18. Electrical Specifications Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .253 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . 254 Functional Operating Range 255 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 256 Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257 Oscillator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257 USB DC Electrical Characteristics ...

Page 18

... Reserved Register Bit 281 Reserved Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281 Monitor ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .282 Universal Serial Bus Module 282 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . 282 Functional Operating Range . . . . . . . . . . . . . . . . . . . . . . .283 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . .283 Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284 Memory Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 284 MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3 Table of Contents Freescale Semiconductor ...

Page 19

... MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3 Freescale Semiconductor Title MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 44-Pin QFP Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . 32 28-pin SOIC Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . 33 20-pin PDIP and SOIC Pin Assignments . . . . . . . . . . . . . . . . . 33 Power Supply Bypassing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Regulator Supply Capacitor Configuration . . . . . . . . . . . . . . . . 35 Memory Map Control, Status, and Data Registers ...

Page 20

... Supported Transaction Types Per Endpoint 125 Supported USB Packet Types . . . . . . . . . . . . . . . . . . . . . . . . 126 Sync Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 SOP, Sync Signaling, and Voltage Levels . . . . . . . . . . . . . . . 127 EOP Transaction Voltage Levels . . . . . . . . . . . . . . . . . . . . . . 129 EOP Width Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 External Low-Speed Device Configuration . . . . . . . . . . . . . . . 132 MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3 List of Figures Page Freescale Semiconductor ...

Page 21

... CHxMAX Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .197 11-9 TIM Channel Registers (TCH0H/L:TCH1H/L 198 12-1 I/O Port Register Summary .200 12-2 Port A Data Register (PTA 202 12-3 Data Direction Register A (DDRA 203 MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3 Freescale Semiconductor Title List of Figures List of Figures Page Technical Data ...

Page 22

... Break Status and Control Register (BRKSCR 249 17-4 Break Address Register High (BRKH 250 17-5 Break Address Register Low (BRKL 250 17-6 Break Status Register (BSR 251 17-7 Break Flag Control Register High (BFCR 252 Technical Data 22 MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3 List of Figures Freescale Semiconductor ...

Page 23

... SOIC (Case #751D 266 A-1 A-2 B-1 B-2 B-3 MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3 Freescale Semiconductor Title MC68HC08JB8 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . 271 MC68HC08JB8 Memory Map 272 MC68HC08JT8 Block Diagram . . . . . . . . . . . . . . . . . . . . . . .279 MC68HC08JT8 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . 280 Power Supply Bypassing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281 List of Figures ...

Page 24

... List of Figures Technical Data 24 MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3 List of Figures Freescale Semiconductor ...

Page 25

... IREAD (Indexed Read) Command . . . . . . . . . . . . . . . . . . . . . 173 10-7 IWRITE (Indexed Write) Command . . . . . . . . . . . . . . . . . . . . 173 10-8 READSP (Read Stack Pointer) Command . . . . . . . . . . . . . . . 174 10-9 RUN (Run User Program) Command . . . . . . . . . . . . . . . . . . . 174 MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3 Freescale Semiconductor Title Summary of Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Vector Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 ROM-Resident Routines ROM-Resident Routine Variables ...

Page 26

... I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .229 20-1 MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267 A-1 A-2 B-1 B-2 Technical Data 26 Summary of MC68HC08JB8 and MC68HC908JB8 Differences 270 MC68HC08JB8 Order Numbers . . . . . . . . . . . . . . . . . . . . . . . 275 Summary of MC68HC08JT8 and MC68HC908JB8 Differences 278 MC68HC08JT8 Order Numbers . . . . . . . . . . . . . . . . . . . . . . . 284 MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3 List of Tables Freescale Semiconductor ...

Page 27

... M68HC08 Family of 8-bit microcontroller units (MCUs). All MCUs in the family use the enhanced M68HC08 central processor unit (CPU08) and are available with a variety of modules, memory sizes and types, and package types. MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3 Freescale Semiconductor Section 1. General Description Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Pin Assignments ...

Page 28

... Endpoint 2 with 8-byte transmit buffer and 8-byte receive buffer 1. No security feature is absolutely secure. However, Freescale’s strategy is to make reading or copying the FLASH difficult for unauthorized users. Technical Data 28 1 (with USB module disabled) MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3 General Description Freescale Semiconductor ...

Page 29

... MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3 Freescale Semiconductor System protection features: – Optional computer operating properly (COP) reset – Optional low-voltage detection with reset – Illegal opcode detection with reset – Illegal address detection with reset ...

Page 30

... Fast 16/8 divide instruction • Binary-coded decimal (BCD) instructions • Optimization for controller applications • Efficient C language support 1.4 MCU Block Diagram Figure 1-1 Technical Data 30 shows the structure of the MC68HC908JB8. MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3 General Description Freescale Semiconductor ...

Page 31

M68HC08 CPU CPU ARITHMETIC/LOGIC REGISTERS UNIT (ALU) CONTROL AND STATUS REGISTERS — 64 BYTES USER FLASH MEMORY — 8,192 BYTES USER RAM — 256 BYTES MONITOR ROM — 976 BYTES USER FLASH VECTORS — 16 BYTES OSC1 OSCILLATOR OSC2 SYSTEM ...

Page 32

... Pin Assignments Technical Data REG PTB2 3 PTB1 4 PTB0 5 PTD0 6 PTD1 7 PTD2 8 PTD3 9 PTD4 10 PTE1/TCH0 11 Figure 1-2. 44-Pin QFP Pin Assignments MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3 General Description PTA2/KBA2 33 PTA3/KBA3 32 31 PTC7 PTC6 30 PTC5 29 PTC4 28 PTE0/TCLK 27 PTE2/TCH1 26 PTA4/KBA4 25 PTA5/KBA5 24 PTA6/KBA6 23 Freescale Semiconductor ...

Page 33

... NOTE: In 20-pin package, the PTD0 and PTD1 internal pads are bonded together to PTD0/1 pin. MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3 Freescale Semiconductor RST PTA0/KBA0 OSC1 2 27 PTA1/KBA1 OSC2 3 26 PTA2/KBA2 REG PTA3/KBA3 PTE0/TCLK PTD0 6 23 PTE2/TCH1 PTD1 7 22 PTA4/KBA4 PTD2 8 21 ...

Page 34

... NOTE: Values shown are typical values. Figure 1-5. Power Supply Bypassing ) REG pin requires an external bulk capacitor 4.7µF REG MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3 General Description Figure 1-5 . BYPASS used REG Figure 1-6 shows. pin as possible. REG Freescale Semiconductor ...

Page 35

... External Interrupt Pins (IRQ, PTE4/D–) IRQ is an asynchronous external interrupt pin. IRQ is also the pin to enter monitor mode. The IRQ pin contains a software configurable pullup device to V (See MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3 Freescale Semiconductor V REG V REG Figure 1-6. Regulator Supply Capacitor Configuration ...

Page 36

... Each pin contains a software when the pin is configured as an REG 12.8 Port Options.) Section 12. Input/Output Ports MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3 General Description (I/O).) Each pin contains a when the pin is configured Section 14. Keyboard when the pin is REG (I/O).) 12.8 Port Options.) Freescale Semiconductor ...

Page 37

... I/O port. PTB0–PTB7 Each pin has programmable internal pullup to V configured as input. MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3 Freescale Semiconductor (TIM), Section 9. Universal Serial Bus Module and Section 12. Input/Output Ports Table 1-1. Summary of Pin Functions PIN DESCRIPTION and schmitt trigger input ...

Page 38

... MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3 General Description IN/OUT VOLTAGE LEVEL V IN/OUT REG V IN REG V IN REG OUT REG OUT REG OUT REG DD V IN/OUT REG V IN/OUT REG V IN REG V IN/OUT REG V IN/OUT REG OUT REG IN/OUT REG V IN/OUT REG Freescale Semiconductor ...

Page 39

... Introduction The CPU08 can address 64 Kbytes of memory space. The memory map, shown in • • • • MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3 Freescale Semiconductor Section 2. Memory Map Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 I/O Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Monitor ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 Figure 2-1, includes: 8,192 bytes of user FLASH memory ...

Page 40

... Break Status and Control Register (BRKSCR) $FE0F Reserved $FE10 Monitor ROM 2 ↓ 464 Bytes $FFDF $FFE0 Reserved ↓ 16 Bytes $FFEF $FFF0 FLASH Vectors ↓ 16 Bytes $FFFF Figure 2-1. Memory Map MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3 Memory Map Freescale Semiconductor ...

Page 41

... ROM addresses that contain the instructions for the monitor functions. (See (MON).) MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3 Freescale Semiconductor $FE00; break status register, BSR $FE01; reset status register, RSR $FE02; reserved $FE03; break flag control register, BFCR $FE04 ...

Page 42

... PTB3 PTB2 PTB1 PTB0 PTC3 PTC2 PTC1 PTC0 PTD3 PTD2 PTD1 PTD0 DDRA3 DDRA2 DDRA1 DDRA0 DDRB3 DDRB2 DDRB1 DDRB0 DDRC3 DDRC2 DDRC1 DDRC0 DDRD3 DDRD2 DDRD1 DDRD0 PTE3 PTE2 PTE1 PTE0 DDRE3 DDRE2 DDRE1 DDRE0 Reserved U = Unaffected by reset Freescale Semiconductor ...

Page 43

... TIM Channel 0 $0012 Register Low Write: (TCH0L) Reset: Read: TIM Channel 1 Status and $0013 Control Register Write: (TSC1) Reset: Figure 2-2. Control, Status, and Data Registers (Sheet MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3 Freescale Semiconductor Bit TOF 0 TOIE TSTOP 0 TRST Bit15 ...

Page 44

... Bit10 Bit9 Bit8 Bit3 Bit2 Bit1 Bit0 KEYF 0 IMASKK MODEK ACKK KBIE3 KBIE2 KBIE1 KBIE0 TDX1FR TXD0FR RXD0FR RESUMFR TP2SIZ3 TP2SIZ2 TP2SIZ1 TP2SIZ0 PULLEN ENABLE2 ENABLE1 FUSBO FDP FDM PTE4IF PTE4IE IRQPD PTE3P PCP PBP PAP Reserved U = Unaffected by reset Freescale Semiconductor ...

Page 45

... Read: UE0R67 USB Endpoint 0 Data $0026 Register 6 Write: UE0T67 (UE0D6) Reset: Read: UE0R77 USB Endpoint 0 Data $0027 Register 7 Write: UE0T77 (UE0D7) Reset: Figure 2-2. Control, Status, and Data Registers (Sheet MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3 Freescale Semiconductor Bit URSTD LVID ...

Page 46

... UE1T33 UE1T32 UE1T31 UE1T30 UE1T43 UE1T42 UE1T41 UE1T40 UE1T53 UE1T52 UE1T51 UE1T50 UE1T63 UE1T62 UE1T61 UE1T60 UE1T73 UE1T72 UE1T71 UE1T70 UE2R03 UE2R02 UE2R01 UE2R00 UE2T03 UE2T02 UE2T01 UE2T00 UE2R13 UE2R12 UE2R11 UE2R10 UE2T13 UE2T12 UE2T11 UE2T10 = Reserved U = Unaffected by reset Freescale Semiconductor ...

Page 47

... USB Interrupt Register 1 $003A Write: (UIR1) Reset: Read: USB Control Register 0 $003B Write: (UCR0) Reset: Figure 2-2. Control, Status, and Data Registers (Sheet MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3 Freescale Semiconductor Bit UE2R26 UE2R25 UE2R24 UE2T26 UE2T25 UE2T24 Unaffected by reset UE2R36 UE2R35 ...

Page 48

... COP ILOP BCFE IF6 IF5 IF4 IF3 Unimplemented R MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3 Memory Map Bit 0 TP1SIZ2 TP1SIZ1 TP1SIZ0 RP0SIZ3 RP0SIZ2 RP0SIZ1 RP0SIZ0 RP2SIZ3 RP2SIZ2 RP2SIZ1 RP2SIZ0 SBSW See note 0 ILAD USB LVI IF2 IF1 Reserved U = Unaffected by reset Freescale Semiconductor ...

Page 49

... Break Address low $FE0D Register Write: (BRKL) Reset: Read: Break Status and Control $FE0E Register Write: (BRKSCR) Reset: Read: COP Control Register $FFFF Write: (COPCTL) Reset: Figure 2-2. Control, Status, and Data Registers (Sheet MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3 Freescale Semiconductor Bit ...

Page 50

... IRQ Vector (Low) $FFFA USB Vector (High) IF2 $FFFB USB Vector (Low) $FFFC SWI Vector (High) — $FFFD SWI Vector (Low) $FFFE Reset Vector (High) — $FFFF Reset Vector (Low) MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3 Memory Map Vector Freescale Semiconductor ...

Page 51

... Before processing an interrupt, the CPU uses five bytes of the stack to save the contents of the CPU registers. NOTE: For M6805 Family compatibility, the H register is not stacked. MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3 Freescale Semiconductor Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 Random-Access Memory (RAM) Technical Data ...

Page 52

... The stack pointer decrements during pushes and increments during pulls. NOTE: Be careful when using nested subroutines. The CPU may overwrite data in the RAM during a subroutine or during the interrupt stacking operation. Technical Data 52 MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3 Random-Access Memory (RAM) Freescale Semiconductor ...

Page 53

... This memory can be read, programmed, and erased from a single external supply. The program and erase operations are enabled through the use of an internal charge pump. MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3 Freescale Semiconductor Section 4. FLASH Memory Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 FLASH Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 FLASH Block Erase Operation ...

Page 54

... No security feature is absolutely secure. However, Freescale’s strategy is to make reading or copying the FLASH difficult for unauthorized users. Technical Data 54 Bit BPR7 BPR6 BPR5 BPR4 MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3 FLASH Memory Bit 0 HVEN MASS ERASE PGM BPR3 BPR2 BPR1 BPR0 erased bit The FLASH 1 Freescale Semiconductor ...

Page 55

... PGM bit should not be set the same time. PGM — Program Control Bit This read/write bit configures the memory for program operation. This bit and the ERASE bit should not be set the same time. MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3 Freescale Semiconductor $FE08 Bit ...

Page 56

... Technical Data 56 (5 µs). nvs (2 ms). erase (5 µs). nvh (1 µs), the memory can be accessed in read mode rcv MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3 FLASH Memory Freescale Semiconductor ...

Page 57

... Programming and erasing of FLASH locations cannot be performed by code being executed from the FLASH memory. While these operations must be performed in the order as shown, but other unrelated operations may occur between the steps. MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3 Freescale Semiconductor register. $FFE0–$FFFF. (5 µs). nvs (2 ms) ...

Page 58

... FLASH memory. Technical Data 58 (5 µs). nvs (10 µs). pgs (20 µs). PROG (5 µs). nvh (1 µs), the memory can be accessed in read mode rcv Characteristics). shows a flowchart representation for programming the MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3 FLASH Memory maximum (see 18.13 PROG Freescale Semiconductor ...

Page 59

... PROG This row program algorithm assumes the row programmed are initially erased. Figure 4-3. FLASH Programming Flowchart MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3 Freescale Semiconductor 1 Set PGM bit 2 Write any data to any FLASH address within the row address range desired ...

Page 60

... Technical Data 60 $FE09 Bit BPR7 BPR6 BPR5 BPR4 Figure 4-4. FLASH Block Protect Register (FLBPR) Figure 4-5. FLASH Block Protect Start Address MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3 FLASH Memory Bit 0 BPR3 BPR2 BPR1 BPR0 16-bit memory address BPR[7:1] Freescale Semiconductor ...

Page 61

... ROM-resident routines can be called by a program running in user mode or in monitor mode (see programming, erasing, and verifying. The range of the FLASH memory must be unprotected (see erase or programming routine. MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3 Freescale Semiconductor BPR[7:0] $00 to $DC $DE (1101 1110) $E0 (1110 0000) $E2 (1110 0010) $E4 (1110 0100) and so on ...

Page 62

... Data buffer for programming and verifying. Table 4-3. ERASE Routine ERASE $FC06 5 Bytes CPUSPD — CPU speed HX — Contains any address in the range to be erased CTRLBYT — Mass erase Mass erase if bit MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3 FLASH Memory Description Freescale Semiconductor ...

Page 63

... VERIFY Routine The VERIFY routine reads and verifies a range of FLASH memory. MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3 Freescale Semiconductor Table 4-4. PROGRAM Routine Routine PROGRAM Calling Address $FC09 ...

Page 64

... FLASH Memory Technical Data 64 MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3 FLASH Memory Freescale Semiconductor ...

Page 65

... This section describes the configuration register (CONFIG). This write- once-after-reset register controls the following options: • • • • • • MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3 Freescale Semiconductor Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 USB reset Low voltage inhibit Stop mode recovery time (2048 or 4096 OSCXCLK cycles) 18 COP timeout period (2 – 2 ...

Page 66

... Stop mode recovery after 2048×OSCXCLK cycles 0 = Stop mode recovery after 4096×OSCXCLK cycles Technical Data 66 $001F Bit URSTD LVID Unimplemented Figure 5-1. Configuration Register (CONFIG) MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3 Configuration Register (CONFIG Bit 0 SSREC COPRS STOP COPD Freescale Semiconductor ...

Page 67

... STOP enables the STOP instruction. COPD — COP Disable Bit COPD disables the COP module. (See Operating Properly MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3 Freescale Semiconductor 1 = COP timeout period = ( COP timeout period = ( STOP instruction enabled 0 = STOP instruction treated as illegal opcode (COP).) ...

Page 68

... Configuration Register (CONFIG) Technical Data 68 MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3 Configuration Register (CONFIG) Freescale Semiconductor ...

Page 69

... MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3 Freescale Semiconductor Section 6. Central Processor Unit (CPU) Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Condition Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Arithmetic/Logic Unit (ALU Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Wait Mode ...

Page 70

... Enhanced binary-coded decimal (BCD) data handling • Modular architecture with expandable internal bus definition for extension of addressing range beyond 64-Kbytes • Low-power stop and wait modes Technical Data 70 MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3 Central Processor Unit (CPU) Freescale Semiconductor ...

Page 71

... Accumulator The accumulator is a general-purpose 8-bit register. The CPU uses the accumulator to hold operands and the results of arithmetic/logic operations. Read: Write: Reset: MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3 Freescale Semiconductor shows the five CPU registers. CPU registers are not part ...

Page 72

... The CPU uses the contents of the stack pointer to determine the conditional address of the operand. Read: Write: Reset: Technical Data 72 Bit Indeterminate Figure 6-3. Index Register (H:X) Bit Figure 6-4. Stack Pointer (SP) MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3 Central Processor Unit (CPU) Bit Bit Freescale Semiconductor ...

Page 73

... During reset, the program counter is loaded with the reset vector address located at $FFFE and $FFFF. The vector address is the address of the first instruction to be executed after exiting the reset state. Read: Write: Reset: MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3 Freescale Semiconductor Bit ...

Page 74

... H and C flags to determine the appropriate correction factor Carry between bits 3 and carry between bits 3 and 4 Technical Data 74 Bit Indeterminate Figure 6-6. Condition Code Register (CCR) MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3 Central Processor Unit (CPU Bit Freescale Semiconductor ...

Page 75

... Z — Zero flag The CPU sets the zero flag when an arithmetic operation, logic operation, or data manipulation produces a result of $00. MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3 Freescale Semiconductor 1 = Interrupts disabled 0 = Interrupts enabled 1 = Negative result 0 = Non-negative result 1 = Zero result ...

Page 76

... Clears the interrupt mask (I bit) in the condition code register, enabling interrupts. After exit from wait mode by interrupt, the I bit remains clear. After exit by reset, the I bit is set. • Disables the CPU clock Technical Data 76 MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3 Central Processor Unit (CPU) Freescale Semiconductor ...

Page 77

... MCU to normal operation if the break interrupt has been deasserted. MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3 Freescale Semiconductor Clears the interrupt mask (I bit) in the condition code register, enabling external interrupts. After exit from stop mode by external interrupt, the I bit remains clear. After exit by reset, the I bit is set. ...

Page 78

... EXT IX2 – IX1 SP1 9EEB ff 4 SP2 9EDB IMM DIR EXT IX2 – IX1 SP1 9EE4 ff 4 SP2 9ED4 DIR INH 48 1 INH 58 1 IX1 SP1 9E68 ff 5 DIR INH 47 1 INH 57 1 IX1 SP1 9E67 ff 5 Freescale Semiconductor ...

Page 79

... Branch if Less Than (Signed Operands) BMC rel Branch if Interrupt Mask Clear BMI rel Branch if Minus BMS rel Branch if Interrupt Mask Set MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3 Freescale Semiconductor Description PC ← (PC rel ? ( ← ← (PC rel ? ( ← (PC rel ? ( ← (PC rel ? (N ⊕ ← (PC rel ? ( ⊕ ← ...

Page 80

... MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3 Central Processor Unit (CPU) CCR DIR (b0 DIR (b1 DIR (b2 DIR (b3 DIR (b4 DIR (b5 DIR (b6 DIR (b7 DIR (b0 DIR (b1 DIR (b2 DIR (b3 DIR (b4 DIR (b5 DIR (b6 DIR (b7 DIR (b0 DIR (b1 DIR (b2 DIR (b3 DIR (b4 DIR (b5 DIR (b6 DIR (b7 DIR IMM IMM IX1 IX SP1 9E61 Freescale Semiconductor ...

Page 81

... DBNZ opr,SP,rel DEC opr DECA DECX Decrement DEC opr,X DEC ,X DEC opr,SP DIV Divide MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3 Freescale Semiconductor Description M ← $00 A ← $00 X ← $00 H ← $00 M ← $00 M ← $00 M ← $00 (A) – (M) M ← (M) = $FF – (M) A ← ...

Page 82

... FC 2 DIR EXT IX2 IX1 IMM DIR EXT IX2 – IX1 SP1 9EE6 ff 4 SP2 9ED6 IMM – DIR IMM DIR EXT IX2 – IX1 SP1 9EEE ff 4 SP2 9EDE DIR INH 48 1 INH 58 1 IX1 SP1 9E68 ff 5 Freescale Semiconductor ...

Page 83

... PULH Pull H from Stack PULX Pull X from Stack ROL opr ROLA ROLX Rotate Left through Carry ROL opr,X ROL ,X ROL opr,SP MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3 Freescale Semiconductor Description ← (M) (M) Destination Source H:X ← (H: (IX+D, DIX+) X:A ← (X) × (A) M ← ...

Page 84

... INH 56 1 IX1 SP1 9E66 INH IMM DIR EXT IX2 IX1 SP1 9EE2 ff 4 SP2 9ED2 DIR EXT IX2 – IX1 SP1 9EE7 ff 4 SP2 9ED7 – DIR DIR EXT IX2 – IX1 SP1 9EEF ff 4 SP2 9EDF Freescale Semiconductor ...

Page 85

... TST opr,SP TSX Transfer SP to H:X TXA Transfer TXS Transfer H MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3 Freescale Semiconductor Description A ← (A) – (M) PC ← (PC Push (PCL) SP ← (SP) – 1; Push (PCH) SP ← (SP) – 1; Push (X) SP ← (SP) – 1; Push (A) SP ← (SP) – 1; Push (CCR) SP ← ...

Page 86

... Logical AND | Logical OR ⊕ Logical EXCLUSIVE Contents of –( ) Negation (two’s complement) # Immediate value « Sign extend ← Loaded with ? If : Concatenated with Set or cleared — Not affected 6-2. MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3 Central Processor Unit (CPU) Effect on CCR Freescale Semiconductor ...

Page 87

Bit Manipulation Branch Read-Modify-Write DIR DIR REL DIR INH MSB LSB BRSET0 BSET0 BRA NEG NEGA 3 DIR 2 DIR 2 REL 2 DIR 1 INH ...

Page 88

... Central Processor Unit (CPU) Technical Data 88 MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3 Central Processor Unit (CPU) Freescale Semiconductor ...

Page 89

... Figure 7-1 various external components. MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3 Freescale Semiconductor Section 7. Oscillator (OSC) Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Oscillator External Connections . . . . . . . . . . . . . . . . . . . . . . . .90 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Crystal Amplifier Input Pin (OSC1 Crystal Amplifier Output Pin (OSC2) ...

Page 90

... DOUBLER OSC1 OSC2 can be 0 (shorted) when used with higher frequency crystals. Refer to manufacturer’s data. Figure 7-1. Oscillator External Connections MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3 Oscillator (OSC) 7-1. This figure shows only TO SIM TO SIM OSCXCLK OSCOUT ÷ 2 Freescale Semiconductor ...

Page 91

... The duty cycle of OSCXCLK is unknown and may depend on the crystal and other external factors. Also, the frequency and amplitude of OSCXCLK can be unstable at startup. MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3 Freescale Semiconductor ) is included in the diagram to follow strict Pierce S ). Figure 7-1 ...

Page 92

... SIM module. 7.5.2 Stop Mode The STOP instruction disables the OSCXCLK output. 7.6 Oscillator During Break Mode The oscillator continues to drive OSCXCLK when the chip enters the break state. Technical Data 92 MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3 Oscillator (OSC) Freescale Semiconductor ...

Page 93

... MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3 Freescale Semiconductor Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 SIM Bus Clock Control and Generation . . . . . . . . . . . . . . . . . . 96 Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Clock Startup from POR or LVI Reset . . . . . . . . . . . . . . . . . 97 Clocks in Stop Mode and Wait Mode . . . . . . . . . . . . . . . . . . 97 Reset and System Initialization External Pin Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Active Resets from Internal Sources ...

Page 94

... Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112 SIM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 Break Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 Reset Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 Break Flag Control Register . . . . . . . . . . . . . . . . . . . . . . .116 Figure 8-1. Figure 8-2 MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3 System Integration Module (SIM summary of the SIM Freescale Semiconductor ...

Page 95

... Internal address bus IDB Internal data bus PORRST Signal from the power-on reset module to the SIM IRST Internal reset signal R/W Read/write signal MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3 Freescale Semiconductor STOP/WAIT CONTROL SIM COUNTER ÷2 CLOCK CLOCK GENERATORS CONTROL POR CONTROL ...

Page 96

... OSCXCLK SIM COUNTER DOUBLER FROM CLOCK OSCOUT ÷ 2 DOUBLER SIM Figure 8-3. SIM Clock Signals MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3 System Integration Module (SIM Bit 0 SBSW See note 0 ILAD USB LVI IF2 IF1 Figure 8-3. BUS CLOCK GENERATORS Freescale Semiconductor ...

Page 97

... MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3 Freescale Semiconductor Power-on reset module (POR) External reset pin (RST) Computer operating properly module (COP) Illegal opcode Illegal address Universal serial bus module (USB) Low-voltage inhibit module (LVI) ...

Page 98

... Table 8-2. PIN Bit Set Timing Reset Type Number of Cycles Required to Set PIN POR/LVI All others VECT H MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3 System Integration Module (SIM) 8.5 SIM Counter), but an Registers.) Figure 8-4 shows the 4163 (4096 + ( VECT L Freescale Semiconductor ...

Page 99

... The COP reset is asynchronous to the bus clock. The active reset feature allows the part to issue a reset to peripherals and other chips within a system built around the MCU. MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3 Freescale Semiconductor Reset.) 8-5. IRST RST PULLED LOW BY MCU ...

Page 100

... The POR bit of the reset status register (RSR) is set and all other bits in the register are cleared. OSC1 PORRST 4096 CYCLES OSCXCLK OSCOUT RST IAB Technical Data 100 32 32 CYCLES CYCLES Figure 8-7. POR Recovery MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3 System Integration Module (SIM) $FFFE $FFFF Freescale Semiconductor ...

Page 101

... MCU. A data fetch from an unmapped address does not generate a reset. The SIM actively pulls down the RST pin for all internal reset sources. MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3 Freescale Semiconductor 12 4 – 2 OSCXCLK cycles, drives the COP counter. The COP + V while the MCU is in monitor mode ...

Page 102

... Technical Data 102 voltage falls to the LVI reset voltage, V Section 5. Configuration Register MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3 System Integration Module (SIM) . The LVI bit in the TRIP µ s treats that Table 8-3 shows the Freescale Semiconductor ...

Page 103

... The power-on reset module (POR) detects power applied to the MCU. At power-on, the POR circuit asserts the signal PORRST. Once the SIM is initialized, it enables the oscillator to drive the bus clock state machine. MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3 Freescale Semiconductor Table 8-3. Registers not Affected by Normal Reset Bits Registers ...

Page 104

... An interrupt temporarily changes the sequence of program execution to respond to a particular event. system interrupts. Technical Data 104 Figure 8-8 MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3 System Integration Module (SIM) 8.7.2 Stop Mode for counter control and flow charts the handling of Freescale Semiconductor ...

Page 105

... YES MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3 Freescale Semiconductor FROM RESET YES BREAK INTERRUPT ? NO I BIT SET? I BIT SET? NO YES IRQ INTERRUPT ? NO YES USB INTERRUPT ? NO OTHER YES INTERRUPTS ? NO LOAD PC WITH INTERRUPT VECTOR FETCH NEXT INSTRUCTION SWI YES INSTRUCTION ? NO RTI YES INSTRUCTION ...

Page 106

... SP – – CCR Figure 8-9. Interrupt Entry SP – – – –1 [15:8] PC – 1[7:0] Figure 8-10. Interrupt Recovery MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3 System Integration Module (SIM) Figure VECT H VECT L START ADDR V DATA H V DATA L OPCODE OPCODE OPERAND Freescale Semiconductor ...

Page 107

... If the interrupt service routine modifies the H register or uses the indexed addressing mode, software should save the H register and then restore it prior to exiting the routine. MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3 Freescale Semiconductor CLI LDA #$FF INT1 ...

Page 108

... IF4 TOIE IF5 IMASKK IF6 MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3 System Integration Module (SIM) (2) Vector Address Priority 0 $FFFC–$FFFD 1 $FFFA–$FFFB 2 $FFF8–$FFF9 3 $FFF6–$FFF7 4 $FFF4–$FFF5 5 $FFF2–$FFF3 6 $FFF0–$FFF1 Freescale Semiconductor ...

Page 109

... Section 17. Break Module break state by forcing it to the SWI vector location. Refer to the break interrupt subsection of each module to see how each module is affected by the break state. MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3 Freescale Semiconductor $FE04 Bit IF6 ...

Page 110

... Some modules can be programmed to be active in wait mode. Technical Data 110 Figure 8-13 shows the timing for wait mode entry. MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3 System Integration Module (SIM) Freescale Semiconductor ...

Page 111

... If the COP disable bit, COPD, in the mask option register is logic 0, then the computer operating properly module (COP) is enabled and remains active in wait mode. Figure 8-14 OSCXCLK MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3 Freescale Semiconductor IAB WAIT ADDR WAIT ADDR + 1 IDB PREVIOUS DATA ...

Page 112

... Figure 8-16 shows stop mode entry timing. IAB STOP ADDR STOP ADDR + 1 IDB PREVIOUS DATA NEXT OPCODE instruction. Figure 8-16. Stop Mode Entry Timing MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3 System Integration Module (SIM) SAME SAME SAME SAME Freescale Semiconductor ...

Page 113

... SBSW — SIM Break Stop/Wait This status bit is useful in applications requiring a return to wait or stop mode after exiting from a break interrupt. Clear SBSW by writing a logic 0 to it. Reset clears SBSW. MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3 Freescale Semiconductor STOP RECOVERY PERIOD STOP +1 STOP + 2 STOP + 2 ...

Page 114

... See if wait mode or stop mode was exited ; by break RETURNLO is not zero, ; then just decrement low byte. ; Else deal with high byte, too. ; Point to WAIT/STOP opcode. ; Restore H register. MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3 System Integration Module (SIM) at that time, then the PIN IH Freescale Semiconductor ...

Page 115

... An illegal opcode reset has occurred since the last read of the RSR ILAD — Illegal Address Reset Bit (opcode fetches only) USB — Universal Serial Bus Reset Bit LVI — Low voltage inhibit Reset Bit MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3 Freescale Semiconductor $FE01 Bit ...

Page 116

... BCFE bit must be set Status bits clearable during break 0 = Status bits not clearable during break Technical Data 116 $FE03 Bit BCFE Reserved Figure 8-20. Break Flag Control Register (BFCR) MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3 System Integration Module (SIM Bit Freescale Semiconductor ...

Page 117

... MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3 Freescale Semiconductor Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 Pin Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .124 USB Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 Sync Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 Packet Identifier Field . . . . . . . . . . . . . . . . . . . . . . . . . . 127 Address Field (ADDR 128 Endpoint Field (ENDP) ...

Page 118

... USB Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 USB End-of-Transaction Interrupt . . . . . . . . . . . . . . . . . . . 157 Receive Control Endpoint 158 Transmit Control Endpoint 160 Transmit Endpoint 161 Transmit Endpoint 162 Receive Endpoint 162 Resume Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 End-of-Packet Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3 Universal Serial Bus Module (USB) Freescale Semiconductor ...

Page 119

... MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3 Freescale Semiconductor Full Universal Serial Bus Specification 1.1 low-speed functions 1.5 Mbps data rate On-chip 3.3V regulator Endpoint 0 with 8-byte transmit buffer and 8-byte receive buffer Endpoint 1 with 8-byte transmit buffer ...

Page 120

... Universal Serial Bus Module (USB) D+ D– PTE3/D+ PTE4/D– Bit TXD1FR TXD0FR RXD0FR RESUMFR TP2SIZ3 TP2SIZ2 TP2SIZ1 TP2SIZ0 PULLEN ENABLE2 ENABLE1 FUSBO FDP FDM UE0R03 UE0R02 UE0R01 UE0R00 UE0T03 UE0T02 UE0T01 UE0T00 UE0R13 UE0R12 UE0R11 UE0R10 UE0T13 UE0T12 UE0T11 UE0T10 U = Unaffected by reset Freescale Semiconductor ...

Page 121

... Register 2 Write: UE1T27 (UE1D2) Reset: $002B Read: USB Endpoint 1 Data Register 3 Write: UE1T37 (UE1D3) Reset: Figure 9-1. USB I/O Register Summary (Sheet MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3 Freescale Semiconductor Bit UE0R26 UE0R25 UE0R24 UE0T26 UE0T25 UE0T24 Unaffected by reset UE0R36 UE0R35 ...

Page 122

... UE2R10 UE2T13 UE2T12 UE2T11 UE2T10 UE2R23 UE2R22 UE2R21 UE2R20 UE2T23 UE2T22 UE2T21 UE2T20 UE2R33 UE2R32 UE2R31 UE2R30 UE2T33 UE2T32 UE2T31 UE2T30 UE2R43 UE2R42 UE2R41 UE2R40 UE2T43 UE2T42 UE2T41 UE2T40 UE2R53 UE2R52 UE2R51 UE2R50 UE2T53 UE2T52 UE2T51 UE2T50 U = Unaffected by reset Freescale Semiconductor ...

Page 123

... USB Status Register 0 Read: R0SEQ (USR0) Write: Reset: $003E USB Status Register 1 Read: R2SEQ (USR1) Write: Reset: Figure 9-1. USB I/O Register Summary (Sheet MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3 Freescale Semiconductor Bit UE2R66 UE2R65 UE2R64 UE2T66 UE2T65 UE2T64 Unaffected by reset UE2R76 UE2R75 ...

Page 124

... USB module. The USB Description). RCV VPIN USB VMIN CONTROL LOGIC VPOUT VMOUT USB REGISTERS Figure 9-2. USB Block Diagram MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3 Universal Serial Bus Module (USB USB UPSTREAM PORT D – Freescale Semiconductor ...

Page 125

... SETUP DATA0 ENDPOINTS 1 & 2 TRANSACTIONS: Interrupt IN DATA0/1 Bulk Transmit IN DATA0/1 Figure 9-3. Supported Transaction Types Per Endpoint MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3 Freescale Semiconductor shows the various transaction types supported by the USB ACK OUT DATA0 ACK ACK IN DATA0 ACK ACK ...

Page 126

... Figure 9-5 SYNC PATTERN Idle Figure 9-5. Sync Pattern MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3 Universal Serial Bus Module (USB) Figure 9-4. Token packets ADDR ENDP CRC5 EOP DATA CRC16 EOP 0 – 8 Bytes EOP is used as a synchronization PID0 PID1 Freescale Semiconductor ...

Page 127

... The packet identifier field is an 8-bit number comprised of the 4-bit packet identification and its complement. The field follows the sync pattern and determines the direction and type of transaction on the bus. Table 9-2 types. MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3 Freescale Semiconductor (min.) (max) (min.) (min.) V ...

Page 128

... D+ and D– output drivers are placed in their high-impedance state. The bus termination resistors hold the bus in the idle state. end-of-packet transaction. Technical Data 128 Figure 9-7 shows the data signaling and voltage levels for an MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3 Universal Serial Bus Module (USB) Freescale Semiconductor ...

Page 129

... A USB sourced reset will hold the MCU in reset for the duration of the reset on the USB bus. The USB bit in the reset status register (RSR) will be set after the internal reset is removed. Refer to Register detailed in MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3 Freescale Semiconductor (min.) (max) (min.) (min Figure 9-7 ...

Page 130

... USB module has been placed in the suspend state. Technical Data 130 for more detail. (CONFIG)). When a USB reset is detected, the supply when in the suspend state. DD MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3 Universal Serial Bus Module (USB) 9.8.3 USB Interrupt Section 5. Freescale Semiconductor ...

Page 131

... Refer to the register definitions (see more information about how the force resume (FRESUM) bit can be used to initiate the remote wakeup feature. MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3 Freescale Semiconductor Universal Serial Bus Module (USB) Universal Serial Bus Module (USB) Functional Description 9 ...

Page 132

... D– line. V (3.3V) REG 1.5 kΩ MCU D+ D– Figure 9-9. External Low-Speed Device Configuration ± 1.5% (15,000 ppm). This tolerance includes MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3 Universal Serial Bus Module (USB) USB LOW-SPEED CABLE Freescale Semiconductor ...

Page 133

... USB Transceiver The USB transceiver provides the physical interface to the USB D+ and D– data lines. The transceiver is composed of two parts: an output drive circuit and a receiver. MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3 Freescale Semiconductor 4.0V – 5.5V 3.3V USB DATA LINES REGULATOR ...

Page 134

... The OH ONE BIT TIME (1.5 Mb/s) REFLECTIONS AND RINGING Figure 9-11. Receiver Characteristics MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3 Universal Serial Bus Module (USB) ± 20% to minimize SIGNAL PINS PASS OUTPUT SPEC LEVELS WITH MINIMAL Freescale Semiconductor ...

Page 135

... The data jitter is measured with the same capacitive load used for maximum rise and fall times and is measured at the crossover points of the data lines as shown in MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3 Freescale Semiconductor Figure Differential Input voltage Range Differential Output 0.0 ...

Page 136

... LOW SPEED: 75ns at C Figure 9-14. Data Signal Rise and Fall Time MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3 Universal Serial Bus Module (USB) CROSSOVER POINTS ± ± 25ns and within 10ns for ) of L FALL TIME 90% 90% 10 200pF, 300ns 600 Freescale Semiconductor ...

Page 137

... MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3 Freescale Semiconductor USB address register (UADDR) USB control registers 0–4 (UCR0–UCR4) USB status registers 0–1 (USR0–USR1) USB interrupt registers 0–2 (UIR0–UIR2) USB endpoint 0 data registers 0–7 (UE0D0–UE0D7) USB endpoint 1 data registers 0– ...

Page 138

... These bits specify the USB address of the device. Reset clears these bits. Technical Data 138 $0038 Bit USBEN UADD6 UADD5 UADD4 Figure 9-15. USB Address Register (UADDR) interrupt MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3 Universal Serial Bus Module (USB Bit 0 UADD3 UADD2 UADD1 UADD0 Freescale Semiconductor ...

Page 139

... TXD2IE — Endpoint 2 Transmit Interrupt Enable This read/write bit enables the transmit endpoint 2 to generate CPU interrupt requests when the TXD2F bit becomes set. Reset clears the TXD2IE bit. MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3 Freescale Semiconductor $0039 Bit EOPIE ...

Page 140

... RXD0F bit becomes set. Reset clears the RXD0IE bit Receive endpoint 0 can generate a CPU interrupt request 0 = Receive endpoint 0 cannot generate a CPU interrupt request Technical Data 140 MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3 Universal Serial Bus Module (USB) Freescale Semiconductor ...

Page 141

... ACK handshake packet from the host is received. Once the next set of data is ready in the transmit buffers, software must clear this flag by writing a logic 1 to the TXD2FR bit. MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3 Freescale Semiconductor $003A Bit 7 6 ...

Page 142

... RESUMFR bit. Reset clears this bit. Writing a logic 0 to RESUMF has no effect USB bus activity has been detected USB bus activity has been detected Technical Data 142 MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3 Universal Serial Bus Module (USB) Freescale Semiconductor ...

Page 143

... USB will respond with a NAK handshake to any endpoint 0 OUT tokens; but does not respond to a SETUP token. Reset clears this bit. Writing to RXD0F has no effect. MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3 Freescale Semiconductor 1 = Transmit on endpoint 0 has occurred 0 = Transmit on endpoint 0 has not occurred 1 = Receive on endpoint 0 has occurred ...

Page 144

... Writing a logic 0 to RXD0FR has no effect. Reset clears this bit. Technical Data 144 $0018 Bit EOPFR RSTFR TXD2FR RXD2FR Figure 9-18. USB Interrupt Register 2 (UIR2) MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3 Universal Serial Bus Module (USB Bit TXD1FR TXD0FR RXD0FR RESUMFR Freescale Semiconductor ...

Page 145

... If this bit the RXD0F is set, the USB will respond with a NAK handshake to any endpoint 0 OUT tokens; but does not respond to a SETUP token. Reset clears this bit. MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3 Freescale Semiconductor $003B Bit ...

Page 146

... It must be cleared by software when no more data needs to be transmitted. Technical Data 146 $003C Bit T1SEQ STALL1 TX1E FRESUM TP1SIZ3 Figure 9-20. USB Control Register 1 (UCR1) MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3 Universal Serial Bus Module (USB Bit 0 TP1SIZ2 TP1SIZ1 TP1SIZ0 Freescale Semiconductor ...

Page 147

... DATA1) will be sent during the next IN transaction directed to endpoint 2. Toggling of this bit must be controlled by software. Reset clears this bit. MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3 Freescale Semiconductor 1 = Data is ready to be sent 0 = Data is not ready. Respond with NAK 1 = Force data lines to K state ...

Page 148

... TP2SIZ3–TP2SIZ0 — Endpoint 2 Transmit Data Packet Size These read/write bits store the number of transmit data bytes for the next IN token request for endpoint 2. These bits are cleared by reset. Technical Data 148 MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3 Universal Serial Bus Module (USB) Freescale Semiconductor ...

Page 149

... OSTALL0 — Endpoint 0 Force STALL Bit for OUT token This read/write bit causes endpoint 0 to return a STALL handshake when polled by an OUT token by the USB host controller. Reset clears this bit. MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3 Freescale Semiconductor $001A Bit ...

Page 150

... This read/write bit enables endpoint 1 and allows the USB to respond to IN packets addressed to endpoint 1. Reset clears this bit Endpoint 1 is enabled and can respond token 0 = Endpoint 1 is disabled Technical Data 150 MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3 Universal Serial Bus Module (USB) Freescale Semiconductor ...

Page 151

... FUSBO and the USBEN bits are set, the USB module is in output mode and it will not recognize any USB signals including the USB reset signal. The UCR4 register is used for some special applications. Customers are not normally expected to use this register. MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3 Freescale Semiconductor $001B Bit ...

Page 152

... OUT or SETUP transaction for endpoint 0. Technical Data 152 $003D Bit R0SEQ SETUP 0 0 Unaffected by reset = Unimplemented Figure 9-24. USB Status Register 0 (USR0) MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3 Universal Serial Bus Module (USB Bit 0 RP0SIZ3 RP0SIZ2 RP0SIZ1 RP0SIZ0 Freescale Semiconductor ...

Page 153

... This bit is updated at the end of the EP0 data transmission. RP2SIZ3–RP2SIZ0 — Endpoint 2 Receive Data Packet Size These read-only bits store the number of data bytes received for the last OUT transaction for endpoint 2. MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3 Freescale Semiconductor $003E Bit ...

Page 154

... UE0D7 UE0R76 UE0R75 UE0R74 UE0T76 UE0T75 UE0T74 Unaffected by reset MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3 Universal Serial Bus Module (USB Bit 0 UE0R03 UE0R02 UE0R01 UE0R00 UE0T03 UE0T02 UE0T01 UE0T00 ↓ UE0R73 UE0R72 UE0R71 UE0R70 UE0T73 UE0T72 UE0T71 UE0T70 Freescale Semiconductor ...

Page 155

... Figure 9-27. USB Endpoint 1 Data Registers (UE1D0–UE1D7) UE1Tx7–UE1Tx0 — Endpoint 1 Transmit or Receive Data Buffer These write-only buffers are loaded by software with data to be sent on the USB bus on the next IN token directed at endpoint 1. MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3 Freescale Semiconductor $0028 UE1D0 Bit 7 6 ...

Page 156

... UE2D7 UE2R76 UE2R75 UE2R74 UE2T76 UE2T75 UE2T74 Unaffected by reset MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3 Universal Serial Bus Module (USB Bit 0 UE2R03 UE2R02 UE2R01 UE2R00 UE2T03 UE2T02 UE2T01 UE2T00 ↓ UE2R73 UE2R72 UE2R71 UE2R70 UE2T73 UE2T72 UE2T71 UE2T70 Freescale Semiconductor ...

Page 157

... There are five possible end-of-transaction interrupts: • • End-of-transaction interrupts occur as detailed in the following sections. MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3 Freescale Semiconductor End-of-transaction interrupts signify either a completed transaction receive or transmit transaction. Resume interrupts signify that the USB bus is reactivated after having been suspended. ...

Page 158

... INTERRUPT ENABLED? (RXD0IE = 1) Y VALID TRANSACTION MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3 Universal Serial Bus Module (USB) TIMEOUT NO RESPONSE FROM USB FUNCTION NO RESPONSE FROM USB FUNCTION SEND STALL HANDSHAKE SEND NAK HANDSHAKE IGNORE TRANSACTION NO RESPONSE FROM USB FUNCTION NO INTERRUPT Freescale Semiconductor ...

Page 159

... SETUP transactions cannot be stalled by the USB function. A SETUP received by a control endpoint will clear the ISTALL0 and OSTALL0 bits. The conditions for receiving a SETUP interrupt are shown in Figure ENDPOINT 0 RECEIVE READY TO RECEIVE? MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3 Freescale Semiconductor 9-30. VALID SETUP TOKEN RECEIVED FOR ENDPOINT ...

Page 160

... ACK RECEIVED AND SET TXD0F TO 1 TRANSMIT ENDPOINT N INTERRUPT ENABLED? (TXD0IE = 1) Y VALID TRANSACTION MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3 Universal Serial Bus Module (USB) NO RESPONSE FROM USB FUNCTION SEND STALL HANDSHAKE SEND NAK HANDSHAKE NO RESPONSE FROM USB FUNCTION NO INTERRUPT Freescale Semiconductor ...

Page 161

... TXD1F in the UIR1 register. The conditions necessary for the interrupt to occur are shown in Figure TRANSMIT ENDPOINT NOT STALLED TRANSMIT ENDPOINT READY TO TRANSFER? (TX1E = 1) AND (TXD1F = 0) AND (UE1TR = 0) MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3 Freescale Semiconductor 9-32. VALID IN TOKEN RECEIVED FOR ENDPOINT USB MODULE ENABLED? ...

Page 162

... Upon detection of an end-of-packet signal, the USB module sets the EOPF bit and will generate a CPU interrupt if the EOPIE bit in the UIR0 register is set. Technical Data 162 MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3 Universal Serial Bus Module (USB) Freescale Semiconductor ...

Page 163

... Monitor mode entry can be achieved without use of the higher voltage thus reducing the hardware requirements for in-circuit programming. MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3 Freescale Semiconductor Section 10. Monitor ROM (MON) Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .164 Entering Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 Baud Rate ...

Page 164

... No security feature is absolutely secure. However, Freescale’s strategy is to make reading or copying the FLASH difficult for unauthorized users. Technical Data 164 1 Figure 10-1 shows a example circuit used to enter monitor MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3 Monitor ROM (MON reset vector applied DD HI Freescale Semiconductor ...

Page 165

... SW2: Position D — Low-voltage entry to monitor mode (with blank reset vector). See Section 18 for IRQ voltage level requirements. 3. SW3: Position E — OSC1 directly driven by external oscillator. SW3: Position F — OSC1 driven by crystal oscillator circuit. MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3 Freescale Semiconductor 10k Ω ...

Page 166

... XCLK monitor mode. 9600 baud communication on PTA0. COP disabled. ÷ 2) Low-voltage entry to monitor mode. ÷ 2) 9600 baud communication on PTA0. COP disabled. Enters user mode. If $FFFE and $FFFF is ÷ 2) blank, MCU will encounter an illegal address reset. for monitor mode entry. HI Freescale Semiconductor ...

Page 167

... IRQ or the RST. Figure the reset vector is blank and IRQ = V required for a baud rate of 9600. MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3 Freescale Semiconductor +V is applied to IRQ and PTA3 is low upon monitor mode entry DD HI condition set 1), the bus frequency is a equal to the external ...

Page 168

... Technical Data 168 POR RESET NO IS VECTOR BLANK? YES MONITOR MODE EXECUTE MONITOR CODE POR NO TRIGGERED? YES 10.5 Security.) After the security bytes, the MCU sends a MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3 Monitor ROM (MON) NORMAL USER MODE Freescale Semiconductor ...

Page 169

... PTA3 pin is at logic zero upon entry into monitor mode, the divide by ratio is 312. Blank reset vector, MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3 Freescale Semiconductor is a summary of the vector differences between user mode Table 10-2. Monitor Mode Vector Differences Reset ...

Page 170

... MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3 Monitor ROM (MON) and Figure 10-4.) NEXT START STOP BIT 5 BIT 6 BIT 7 BIT BIT NEXT START STOP BIT 5 BIT 6 BIT 7 BIT BIT STOP NEXT BIT 5 BIT 6 BIT 7 BIT START BIT ADDR. LOW DATA RESULT Freescale Semiconductor ...

Page 171

... When the monitor receives a break signal, it drives the PTA0 pin high for the duration of two bits before echoing the break signal. 10.4.6 Commands The monitor ROM uses the following commands: • • • • • • MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3 Freescale Semiconductor MISSING STOP BIT Figure 10-6. Break Transaction ...

Page 172

... Command Sequence SENT TO MONITOR WRITE WRITE ADDR. HIGH ECHO Technical Data 172 ADDR. HIGH ADDR. HIGH ADDR. LOW ADDR. HIGH ADDR. LOW ADDR. LOW MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3 Monitor ROM (MON) ADDR. LOW DATA RESULT DATA DATA Freescale Semiconductor ...

Page 173

... MONITOR IWRITE IWRITE ECHO NOTE: A sequence of IREAD or IWRITE commands can sequentially access a block of memory over the full 64-Kbyte memory map. MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3 Freescale Semiconductor DATA DATA RESULT DATA DATA Monitor ROM (MON) Monitor ROM (MON) Functional Description ...

Page 174

... Table 10-9. RUN (Run User Program) Command Description Executes RTI instruction Operand None Data Returned None Opcode $28 Command Sequence SENT TO MONITOR RUN RUN ECHO Technical Data 174 SP HIGH SP LOW RESULT MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3 Monitor ROM (MON) Freescale Semiconductor ...

Page 175

... If the reset was not a power-on reset, security remains bypassed and security code entry is not required. (See V DD RST PTA0 NOTES: MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3 Freescale Semiconductor 4096 + 32 OSCXCLK CYCLES 24 BUS CYCLES FROM HOST 1 FROM MCU 1 = Echo delay, 2 bit times 2 = Data return delay, 2 bit times 4 = Wait 1 bit time before sending next byte ...

Page 176

... FLASH module can also be mass erased by executing an erase routine that was downloaded into internal RAM. The mass erase operation clears the security code locations so that all eight security bytes become $FF (blank). Technical Data 176 MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3 Monitor ROM (MON) Freescale Semiconductor ...

Page 177

... TIM Counter Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 11.10.3 TIM Counter Modulo Registers . . . . . . . . . . . . . . . . . . . . . 193 11.10.4 TIM Channel Status and Control Registers . . . . . . . . . . . . 194 11.10.5 TIM Channel Registers 198 MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3 Freescale Semiconductor Section 11. Timer Interface Module (TIM) Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 Pin Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 Functional Description ...

Page 178

... Full TIM Pin Names: Technical Data 178 is a block diagram of the TIM. Table 11-1. The generic pin name appear in Table 11-1. TIM Pin Name Conventions TCLK PTE0/TCLK MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3 Timer Interface Module (TIM) TCH0 TCH1 PTE2/TCH1 PTE1/TCH0 Freescale Semiconductor ...

Page 179

... COMPARATOR TMODH:TMODL CHANNEL 0 16-BIT COMPARATOR TCH0H:TCH0L 16-BIT LATCH CHANNEL 1 16-BIT COMPARATOR TCH1H:TCH1L 16-BIT LATCH MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3 Freescale Semiconductor shows the structure of the TIM. The central component of PRESCALER SELECT PS2 PS1 PS0 ELS0B ELS0A CH0F MS0A MS0B ...

Page 180

... Timer Interface Module (TIM Bit PS2 PS1 PS0 Bit11 Bit10 Bit9 Bit8 Bit3 Bit2 Bit1 Bit0 Bit11 Bit10 Bit9 Bit8 Bit3 Bit2 Bit1 Bit0 ELS0B ELS0A TOV0 CH0MAX Bit11 Bit10 Bit9 Bit8 Bit3 Bit2 Bit1 Bit0 ELS1B ELS1A TOV1 CH1MAX Freescale Semiconductor ...

Page 181

... When the counter reaches the value in the registers of an output compare channel, the TIM can set, clear, or toggle the channel pin. Output compares can generate TIM CPU interrupt requests. MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3 Freescale Semiconductor Read: Bit15 Bit14 Bit13 ...

Page 182

... Technical Data 182 11.5.3 Output Compare. The pulses are MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3 Timer Interface Module (TIM) Freescale Semiconductor ...

Page 183

... TIM to clear the channel pin on output compare if the state of the PWM pulse is logic 1. Program the TIM to set the pin if the state of the PWM pulse is logic 0. MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3 Freescale Semiconductor Figure 11-3 shows, the output compare value in the TIM channel Timer Interface Module (TIM) ...

Page 184

... WIDTH OUTPUT COMPARE Figure 11-3. PWM Period and Pulse Width 11.10.1 TIM Status and Control 11.5.4 Pulse Width Modulation MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3 Timer Interface Module (TIM) OVERFLOW OUTPUT OUTPUT COMPARE COMPARE Register). (PWM). The pulses are Freescale Semiconductor ...

Page 185

... While the MS0B bit is set, the channel 1 pin, PTE2/TCH1, is available as a general-purpose I/O pin. MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3 Freescale Semiconductor When changing to a shorter pulse width, enable channel x output compare interrupts and write the new value in the output compare interrupt routine ...

Page 186

... Write 1:0 (to clear output on compare) or 1:1 (to set output on compare) to the edge/level select bits, ELSxB:ELSxA. The output action on compare must force the output to the complement of the pulse width level. (See MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3 Timer Interface Module (TIM) Table 11-3.) Table 11-3.) Freescale Semiconductor ...

Page 187

... The WAIT and STOP instructions put the MCU in low power- consumption standby modes. MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3 Freescale Semiconductor Registers.) TIM overflow flag (TOF) — The TOF bit is set when the TIM counter reaches the modulo value programmed in the TIM counter modulo registers ...

Page 188

... BCFE is at logic 0. After the break, doing the second step clears the status bit. Technical Data 188 8.8.3 Break Flag Control MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3 Timer Interface Module (TIM) Register.) Freescale Semiconductor ...

Page 189

... I/O Registers The following I/O registers control and monitor operation of the TIM: • • • • • MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3 Freescale Semiconductor 11.10.1 TIM Status and Control or TCLK LMIN 1 ------------------------------------ - bus frequency bus frequency ÷ 2 TIM status and control register (TSC) ...

Page 190

... TIM overflow interrupts enabled 0 = TIM overflow interrupts disabled Technical Data 190 $000A Bit TOF 0 TOIE TSTOP 0 TRST Unimplemented Figure 11-4. TIM Status and Control Register (TSC) MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3 Timer Interface Module (TIM Bit 0 0 PS2 PS1 PS0 Freescale Semiconductor ...

Page 191

... These read/write bits select either the PTE0/TCLK pin or one of the seven prescaler outputs as the input to the TIM counter as Table 11-2 PS2 MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3 Freescale Semiconductor 1 = TIM counter stopped 0 = TIM counter active 1 = Prescaler and TIM counter cleared effect shows ...

Page 192

... Bit 15 Bit 14 Bit 13 Bit Address: $000D Bit Bit 7 Bit 6 Bit 5 Bit Unimplemented Figure 11-5. TIM Counter Registers (TCNTH:TCNTL) MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3 Timer Interface Module (TIM Bit 0 Bit 11 Bit 10 Bit 9 Bit Bit 0 Bit 3 Bit 2 Bit 1 Bit Freescale Semiconductor ...

Page 193

... Reset sets the TIM counter modulo registers. TMODH TMODL Figure 11-6. TIM Counter Modulo Registers (TMODH:TMODL) NOTE: Reset the TIM counter before writing to the TIM counter modulo registers. MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3 Freescale Semiconductor Address: $000E Bit Read: Bit 15 ...

Page 194

... Figure 11-7. TIM Channel Status and Control Registers Technical Data 194 Address: $0010 Bit CH0F CH0IE MS0B MS0A Address: $0013 Bit CH1F 0 CH1IE MS1A Unimplemented (TSC0:TSC1) MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3 Timer Interface Module (TIM Bit 0 ELS0B ELS0A TOV0 CH0MAX Bit 0 ELS1B ELS1A TOV1 CH1MAX Freescale Semiconductor ...

Page 195

... When ELSxB:ELSxA ≠ 0:0, this read/write bit selects either input capture operation or unbuffered output compare/PWM operation. See MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3 Freescale Semiconductor 1 = Input capture or output compare on channel input capture or output compare on channel Channel x CPU interrupt requests enabled 0 = Channel x CPU interrupt requests disabled ...

Page 196

... Pin under port control; initial output level low Capture on rising edge only Capture on falling edge only Capture on rising or falling edge Toggle output on compare Clear output on compare Set output on compare Toggle output on compare Clear output on compare Set output on compare Freescale Semiconductor ...

Page 197

... The output stays at the 100% duty cycle level until the cycle after CHxMAX is cleared. PTEx/TCHx MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3 Freescale Semiconductor 1 = Channel x pin toggles on TIM counter overflow 0 = Channel x pin does not toggle on TIM counter overflow shows, the CHxMAX bit takes effect in the cycle after it ...

Page 198

... Bit Bit 7 Bit 6 Bit 5 Bit 4 Indeterminate after reset MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3 Timer Interface Module (TIM Bit 0 Bit 11 Bit 10 Bit 9 Bit Bit 0 Bit 3 Bit 2 Bit 1 Bit Bit 0 Bit 11 Bit 10 Bit 9 Bit Bit 0 Bit 3 Bit 2 Bit 1 Bit 0 Freescale Semiconductor ...

Page 199

... Introduction Thirty-seven (37) bidirectional input-output (I/O) pins form five parallel ports. All I/O pins are programmable as inputs or outputs. MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3 Freescale Semiconductor Section 12. Input/Output Ports (I/O) Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 Port 202 Port A Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 Data Direction Register 203 Port B ...

Page 200

... Input/Output Ports (I/O) REG Bit 0 PTA3 PTA2 PTA1 PTA0 PTB3 PTB2 PTB1 PTB0 PTC3 PTC2 PTC1 PTC0 PTD3 PTD2 PTD1 PTD0 DDRA3 DDRA2 DDRA1 DDRA0 DDRB3 DDRB2 DDRB1 DDRB0 DDRC3 DDRC2 DDRC1 DDRC0 DDRD3 DDRD2 DDRD1 DDRD0 PTE3 PTE2 PTE1 PTE0 Freescale Semiconductor ...