IC MCU 8BIT 8K FLASH 16-SOIC

MC908QB8CDWE

Manufacturer Part NumberMC908QB8CDWE
DescriptionIC MCU 8BIT 8K FLASH 16-SOIC
ManufacturerFreescale Semiconductor
SeriesHC08
MC908QB8CDWE datasheet
 


Specifications of MC908QB8CDWE

Core ProcessorHC08Core Size8-Bit
Speed8MHzConnectivitySCI, SPI
PeripheralsLVD, POR, PWMNumber Of I /o13
Program Memory Size8KB (8K x 8)Program Memory TypeFLASH
Ram Size256 x 8Voltage - Supply (vcc/vdd)2.7 V ~ 5.5 V
Data ConvertersA/D 10x10bOscillator TypeInternal
Operating Temperature-40°C ~ 85°CPackage / Case16-SOIC (0.300", 7.5mm Width)
Processor SeriesHC08QBCoreHC08
Data Bus Width8 bitData Ram Size256 B
Interface TypeSCI, SPIMaximum Clock Frequency8 MHz
Number Of Programmable I/os14Number Of Timers4
Operating Supply Voltage3 V to 5 VMaximum Operating Temperature+ 85 C
Mounting StyleSMD/SMTDevelopment Tools By SupplierFSICEBASE, M68CBL05AE, DEMO908QB8, DEMO908QC16
Minimum Operating Temperature- 40 COn-chip Adc10 bit
For Use WithDEMO908QB8 - BOARD DEMO FOR MC68HC908QB8Lead Free Status / RoHS StatusLead free / RoHS Compliant
Eeprom Size-  
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MC68HC908QB8
MC68HC908QB4
MC68HC908QY8
Data Sheet
M68HC08
Microcontrollers
MC68HC908QB8
Rev. 3
04/2010
freescale.com

MC908QB8CDWE Summary of contents

  • Page 1

    MC68HC908QB8 MC68HC908QB4 MC68HC908QY8 Data Sheet M68HC08 Microcontrollers MC68HC908QB8 Rev. 3 04/2010 freescale.com ...

  • Page 2

    ...

  • Page 3

    ... Your printed copy may be an earlier revision. To verify you have the latest information available, refer to: http://freescale.com/ Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. This product incorporates SuperFlash® technology licensed from SST. © Freescale Semiconductor, Inc., 2005–2010. All rights reserved. ...

  • Page 4

    ... Changed BUSCLK4 to BUSCLK2, added — Changed CGMXCLK to — Corrected Functionality column — Corrected first sentence of listing number 1 — Changed CGMXCLK to MC68HC908QB8 Data Sheet, Rev. 3 Page Number(s) N/A — Renamed ADCSC 37 — Changed — 109 130 136 206 29, 36, 96, 101 Freescale Semiconductor ...

  • Page 5

    ... External Interrupt (IRQ Chapter 9 Keyboard Interrupt Module (KBI .83 Chapter 10 Low-Voltage Inhibit (LVI .89 Chapter 11 Oscillator Module (OSC .93 Chapter 12 Input/Output Ports (PORTS 103 Chapter 13 Enhanced Serial Communications Interface (ESCI) Module . . . . . . . . . . . . 109 Chapter 14 System Integration Module (SIM .139 Freescale Semiconductor MC68HC908QB8 Data Sheet, Rev ...

  • Page 6

    ... List of Chapters Chapter 15 Serial Peripheral Interface (SPI) Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 Chapter 16 Timer Interface Module (TIM .175 Chapter 17 Development Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 Chapter 18 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .207 Chapter 19 Ordering Information and Mechanical Specifications . . . . . . . . . . . . . . . . . 227 6 MC68HC908QB8 Data Sheet, Rev. 3 Freescale Semiconductor ...

  • Page 7

    ... Clock Select and Divide Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 3.3.2 Input Select and Pin Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 3.3.3 Conversion Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 3.3.3.1 Initiating Conversions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 3.3.3.2 Completing Conversions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 3.3.3.3 Aborting Conversions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 3.3.3.4 Total Conversion Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 3.3.4 Sources of Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 3.3.4.1 Sampling Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Freescale Semiconductor Chapter 1 General Description Chapter 2 Memory Chapter 3 MC68HC908QB8 Data Sheet, Rev ...

  • Page 8

    ... Keyboard Status and Control Register 4.6.3 Keyboard Interrupt Enable Register 4.6.4 Configuration Register 4.6.5 Configuration Register 5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 5.2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 8 Chapter 4 Auto Wakeup Module (AWU) Chapter 5 Configuration Register (CONFIG) Chapter 6 Computer Operating Properly (COP) MC68HC908QB8 Data Sheet, Rev. 3 Freescale Semiconductor ...

  • Page 9

    ... Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 7.6 CPU During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 7.7 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 7.8 Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 8.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 8.2 Features 8.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 8.3.1 MODE = 8.3.2 MODE = 8.4 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Freescale Semiconductor Chapter 7 Central Processor Unit (CPU) Chapter 8 External Interrupt (IRQ) MC68HC908QB8 Data Sheet, Rev ...

  • Page 10

    ... Forced Reset Operation 10.3.3 LVI Hysteresis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 10.3.4 LVI Trip Selection 10.4 LVI Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 10.5 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 10.5.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 10.5.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 10.6 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 10 Chapter 9 Keyboard Interrupt Module (KBI) Chapter 10 Low-Voltage Inhibit (LVI) MC68HC908QB8 Data Sheet, Rev. 3 Freescale Semiconductor ...

  • Page 11

    ... Port 106 12.3.1 Port B Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 12.3.2 Data Direction Register 107 12.3.3 Port B Input Pullup Enable Register 108 12.3.4 Port B Summary Table 108 Freescale Semiconductor Chapter 11 Oscillator Module (OSC) (INTCLK Chapter 12 Input/Output Ports (PORTS) Chapter 13 MC68HC908QB8 Data Sheet, Rev ...

  • Page 12

    ... ESCI Prescaler Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 13.9 ESCI Arbiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 13.9.1 ESCI Arbiter Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 13.9.2 ESCI Arbiter Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 13.9.3 Bit Time Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 13.9.4 Arbitration Mode 138 12 Chapter 14 System Integration Module (SIM) MC68HC908QB8 Data Sheet, Rev. 3 Freescale Semiconductor ...

  • Page 13

    ... Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 15.2 Features 155 15.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 15.3.1 Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 15.3.2 Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 15.3.3 Transmission Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 15.3.3.1 Clock Phase and Polarity Controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 15.3.3.2 Transmission Format When CPHA = 159 Freescale Semiconductor Chapter 15 MC68HC908QB8 Data Sheet, Rev ...

  • Page 14

    ... TIM During Break Interrupts 182 16.7 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 16.7.1 TIM Channel I/O Pins (TCH3:TCH0 183 16.7.2 TIM Clock Pin (TCLK 183 16.8 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 16.8.1 TIM Status and Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 14 Chapter 16 Timer Interface Module (TIM) MC68HC908QB8 Data Sheet, Rev. 3 Freescale Semiconductor ...

  • Page 15

    ... Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 18.8 3-V DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 18.9 Typical 3-V Output Drive Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 18.10 3-V Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 18.11 Oscillator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 18.12 Supply Current Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 Freescale Semiconductor Chapter 17 Development Support Chapter 18 Electrical Specifications MC68HC908QB8 Data Sheet, Rev ...

  • Page 16

    ... SPI Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 18.15 3.0-Volt SPI Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 18.16 Timer Interface Module Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 18.17 Memory Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 Ordering Information and Mechanical Specifications 19.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 19.2 MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 19.3 Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 16 Chapter 19 MC68HC908QB8 Data Sheet, Rev. 3 Freescale Semiconductor ...

  • Page 17

    ... Monitor ROM containing user callable program/erase routines (2) – FLASH security 1. See 18.11 Oscillator Characteristics 2. No security feature is absolutely secure. However, Freescale’s strategy is to make reading or copying the FLASH difficult for unauthorized users. Freescale Semiconductor 0.4 ADC 10 channel, 10 bit 10 channel, 10 bit 4 channel, 10 bit ) DD ...

  • Page 18

    ... Memory-to-memory data transfers Fast 8 × 8 multiply instruction • • Fast 16/8 divide instruction • Binary-coded decimal (BCD) instructions • Optimization for controller applications • Efficient C language support 18 MC68HC908QB8 Data Sheet, Rev. 3 Freescale Semiconductor ...

  • Page 19

    ... PTB6/TCH2 PTB7/TCH3 MC68HC908QB8 256 BYTES USER RAM POWER SUPPLY RST, IRQ: Pins have internal pull up device All port pins have programmable pull up device PTA[0:5]: Higher current sink and source capability Freescale Semiconductor M68HC08 CPU MC68HC908QB8 8192 BYTES USER FLASH Figure 1-1. Block Diagram MC68HC908QB8 Data Sheet, Rev ...

  • Page 20

    ... Figure 1-2. MCU Pin Assignments MC68HC908QB8 Data Sheet, Rev. 3 PTA1/TCH1/AD1/KBI1 1 16 PTB2 2 15 PTB3 3 14 PTA2/IRQ/KBI2/TCLK 4 13 PTA3/RST/KBI3 5 12 PTB4 6 11 PTB5 7 10 PTA4/OSC2/AD2/KBI4 8 9 16-PIN ASSIGNMENT MC68HC908QY8 TSSOP 1 16 PTA1/TCH1/AD1/KBI1 PTB2/MISO/AD6 PTB3/SS/AD7 4 13 PTA2/IRQ/KBI2/TCLK PTA3/RST/KBI3 PTB4//Rx/AD8 PTB5/Tx/AD9 PTA4/OSC2/AD2/KBI4 16-PIN ASSIGNMENT Freescale Semiconductor ...

  • Page 21

    ... MISO — SPI Master in Slave out PTB2 AD6 — A/D channel 6 input PTB3 — General-purpose I/O port SS — SPI slave select PTB3 AD7 — A/D channel 7 input Freescale Semiconductor Table 1-2. Pin Functions Description MC68HC908QB8 Data Sheet, Rev. 3 Pin Functions Input/Output Power ...

  • Page 22

    ... AD6 → MISO → PTB2 AD7 → SS → PTB3 AD8 → RxD → PTB4 AD9 → TxD → PTB5 TCH2 → PTB6 TCH3 → PTB7 MC68HC908QB8 Data Sheet, Rev. 3 Input/Output Input/Output Input/Output Input Input/Output Output Input Input/Output Input/Output Input/Output Input/Output Freescale Semiconductor ...

  • Page 23

    ... Registers between $0100 and $FFFF require non-direct page addressing modes. See Chapter 7 Central Processor Unit (CPU) addressing modes. Freescale Semiconductor MC68HC908QB8 Data Sheet, Rev. 3 Figure 2-1, Figure ...

  • Page 24

    ... Figure 2-1. Memory Map MC68HC908QB8 Data Sheet, Rev. 3 $0040 RESERVED ↓ 64 BYTES $007F $0080 RAM ↓ 128 BYTES $00FF $0100 RESERVED ↓ 64 BYTES $013F $DE00 RESERVED ↓ 4096 BYTES $EDFF $EE00 FLASH MEMORY ↓ 4096 BYTES $FDFF MC68HC908QB4 Memory Map Freescale Semiconductor ...

  • Page 25

    ... ESCI Control Register 3 $0012 (SCC3) Write: See page 125. Reset: Read: ESCI Status Register 1 $0013 (SCS1) Write: See page 126. Reset: Figure 2-2. Control, Status, and Data Registers (Sheet Freescale Semiconductor Bit AWUL R PTA5 PTA4 Unaffected by reset PTB7 PTB6 PTB5 PTB4 ...

  • Page 26

    ... IMASKK ACKK KBIE3 KBIE2 KBIE1 KBIP3 KBIP2 KBIP1 IRQF 0 IMASK ACK OSCENIN- R ESCIBDSRC STOP LVITRIP SSREC STOP ( PS2 PS1 Bit 11 Bit 10 Bit Reserved U = Unaffected Freescale Semiconductor Bit 0 RPF SCR0 0 PSSB0 0 ARD8 0 ARD0 0 MODEK 0 KBIE0 0 KBIP0 0 MODE 0 RSTEN (2) 0 COPD 0 PS0 0 Bit 8 0 ...

  • Page 27

    ... Read: TIM Channel 3 $0034 Register High (TCH3H) Write: See page 189. Reset: Read: TIM Channel 3 $0035 Register Low (TCH3L) Write: See page 189. Reset: Figure 2-2. Control, Status, and Data Registers (Sheet Freescale Semiconductor Bit Bit 7 Bit 6 Bit 5 Bit Bit 15 Bit 14 ...

  • Page 28

    ... ECGST ECFS1 ECFS0 ECGON TRIM3 TRIM2 TRIM1 TRIM0 ADCH3 ADCH2 ADCH1 ADCH0 AD9 AD8 AD3 AD2 AD1 AD0 MODE1 MODE0 ADLSMP ACLKEN SBSW ILAD MODRST LVI BDCOP IF2 IF1 IF10 IF9 IF8 IF7 IF18 IF17 IF16 IF15 Reserved U = Unaffected Freescale Semiconductor ...

  • Page 29

    ... Reset: $FFBF Reserved Read: Internal Oscillator Trim $FFC0 (Factory Programmed, Write 3.0 V) Reset: DD $FFC1 Reserved Read: COP Control Register $FFFF (COPCTL) Write: See page 63. Reset: Figure 2-2. Control, Status, and Data Registers (Sheet Freescale Semiconductor Bit Bit 15 Bit 14 Bit 13 Bit Bit 7 ...

  • Page 30

    ... TIM1 overflow vector IF4 $FFF4,5 TIM1 Channel 1 vector IF3 $FFF6,7 TIM1 Channel 0 vector IF2 — Not used IF1 $FFFA,B IRQ vector — $FFFC,D SWI vector — $FFFE,F Reset vector ;point one past RAM ;SP<-(H:X-1) MC68HC908QB8 Data Sheet, Rev. 3 Vector Freescale Semiconductor ...

  • Page 31

    ... This read/write bit configures the memory for mass erase operation Mass erase operation selected 0 = Mass erase operation unselected 1. No security feature is absolutely secure. However, Freescale’s strategy is to make reading or copying the FLASH difficult for unauthorized users. Freescale Semiconductor supply. The program and erase operations are DD NOTE 6 ...

  • Page 32

    ... FLASH memory. While these operations must be performed in the order as shown, other unrelated operations may occur between the steps. A page erase of the vector page will erase the internal oscillator trim value at $FFC0. 32 NOTE NOTE CAUTION MC68HC908QB8 Data Sheet, Rev. 3 Freescale Semiconductor ...

  • Page 33

    ... Write any data to any FLASH location within the address range desired. 4. Wait for a time NVS 5. Set the HVEN bit. 1. When in monitor mode, with security sequence failed (see stead of any FLASH address. Freescale Semiconductor (1) within the FLASH memory address range. NOTE NOTE CAUTION NOTE 17 ...

  • Page 34

    ... PGM bit, must not exceed the maximum programming time (1) . NOTE NOTE maximum, see PROG NOTE Register. Once the FLBPR is programmed with a value other than , present on the IRQ pin. This voltage also TST maximum. PROG MC68HC908QB8 Data Sheet, Rev. 3 18.17 Freescale Semiconductor ...

  • Page 35

    ... PROG This row program algorithm assumes the row programmed are initially erased. Figure 2-4. FLASH Programming Flowchart Freescale Semiconductor 1 SET PGM BIT 2 READ THE FLASH BLOCK PROTECT REGISTER 3 WRITE ANY DATA TO ANY FLASH ADDRESS ...

  • Page 36

    ... FLBPR, internal oscillator trim value, and vectors are protected The entire FLASH memory is not protected. MC68HC908QB8 Data Sheet, Rev Bit 0 BPR2 BPR1 BPR0 Freescale Semiconductor ...

  • Page 37

    ... REFH a 8-bit representation. If ADVIN is equal to or less than V Input voltages between V REFH Input voltage must not exceed the analog supply voltages. Freescale Semiconductor REFL and V are straight-line linear conversions. REFL NOTE MC68HC908QB8 Data Sheet, Rev ...

  • Page 38

    ... MC68HC908QB8 Data Sheet, Rev. 3 CLOCK GENERATOR KEYBOARD INTERRUPT MODULE EXTERNAL INTERRUPT MODULE AUTO WAKEUP MODULE LOW-VOLTAGE INHIBIT 4-CHANNEL 16-BIT TIMER MODULE COP MODULE 10-CHANNEL 10-BIT ADC ENHANCED SERIAL COMMUNICATIONS INTERFACE MODULE SERIAL PERIPHERAL INTERFACE DEVELOPMENT SUPPORT MONITOR ROM BREAK MODULE Freescale Semiconductor ...

  • Page 39

    ... This clock is selected when ADICLK and ACLKEN are both low. • The bus clock — This clock source is equal to the bus frequency. This clock is selected when ADICLK is high and ACLKEN is low. Freescale Semiconductor ADCLK ADCK CLOCK CONTROL SEQUENCER ...

  • Page 40

    ... A write to ADSCR occurs (the current conversion will be aborted and a new conversion will be initiated, if ADCH are not all 1s). • A write to ADCLK occurs. • The MCU is reset. • The MCU enters stop mode with ACLK not enabled. 40 MC68HC908QB8 Data Sheet, Rev. 3 Freescale Semiconductor ...

  • Page 41

    ... MHz, then the conversion time for a single 10-bit conversion is: Maximum Conversion time = Number of bus cycles = 11.25 μ MHz = 45 cycles The ADCK frequency must be between f maximum to meet A/D specifications. Freescale Semiconductor ACLKEN 0 1 ≥ ...

  • Page 42

    ... REFH REFL to V (if available). DDA SSA at a quiet point in the ground plane. SS noise but will increase effective conversion time DD MC68HC908QB8 Data Sheet, Rev high (4096*I ) for less than ADVIN Leak or V (if available). This will REFL SSA , one-time error. LSB Freescale Semiconductor ...

  • Page 43

    ... Non-monotonicity is defined as when, except for code jitter, the converter converts to a lower code for a higher input voltage. • Missing codes are those which are never converted for any input value. In 8-bit or 10-bit mode, the ADC10 is guaranteed to be monotonic and to have no missing codes. Freescale Semiconductor –V ...

  • Page 44

    ... To protect status bits during the break state, write BCFE. With BCFE cleared (its default state), software can read and write registers during the break state without affecting status bits. Some status bits have a two-step read/write clearing procedure. If software does the first step on such a bit before the 44 sheet. MC68HC908QB8 Data Sheet, Rev. 3 Freescale Semiconductor ...

  • Page 45

    ... In some packages, REFL V is connected internally to V REFL potential There will be a brief current associated with V SSA Freescale Semiconductor ) DDA as its power pin. In some packages, V DDA pin to the same voltage potential as V DDA for good results. ...

  • Page 46

    ... The ADC10 will continue to convert until the MCU enters reset, the MCU enters stop mode (if ACLKEN is clear), ADCLK is written, or until ADSCR is written again. If stop is entered 46 pin to the same potential as V REFL AIEN ADCO ADCH4 ADCH3 Unimplemented MC68HC908QB8 Data Sheet, Rev the single point SSA 2 1 Bit 0 ADCH2 ADCH1 ADCH0 Freescale Semiconductor . SSA ...

  • Page 47

    ... ADCH4 ADCH3 any unused or reserved channels are selected, the resulting conversion will be unknown. 2. Requires LVI to be powered (LVIPWRD =0, in CONFIG1) Freescale Semiconductor 3-2. The successive approximation converter subsystem is turned off Table 3-2. Input Channel Select ADCH2 ADCH1 ADCH0 ...

  • Page 48

    ... In 8-bit mode, there is no interlocking with ADRH. Bit 7 Read: AD7 Write: Reset Unimplemented Figure 3-6. ADC10 Data Register Low (ADRL AD6 AD5 AD4 AD3 MC68HC908QB8 Data Sheet, Rev Bit Bit 0 0 AD9 AD8 Bit 0 AD2 AD1 AD0 Freescale Semiconductor ...

  • Page 49

    ... LSB Reset returns 8-bit mode 8-bit, right-justified, ADSCR software triggered mode enabled 01 = 10-bit, right-justified, ADSCR software triggered mode enabled 10 = Reserved 11 = 10-bit, right-justified, hardware triggered mode enabled Freescale Semiconductor ADIV0 ADICLK MODE1 0 ...

  • Page 50

    ... MHz if ADLPC is clear, and between 0.5 MHz and 1 MHz if ADLPC is set The asynchronous clock is selected as the input clock source (the clock generator is only enabled during the conversion ADICLK specifies the input clock source and conversions will not continue in stop mode 50 MC68HC908QB8 Data Sheet, Rev. 3 Freescale Semiconductor ...

  • Page 51

    ... Exit from low-power stop mode without external signals • Selectable timeout periods • Dedicated low-power internal oscillator separate from the main system clock sources • Option to allow bus clock source to run the AWU if enabled in STOP Freescale Semiconductor AUTOWUGEN DIV 2 SHORT DIV 2 ...

  • Page 52

    ... AWU Latch (AWUL) — The AWUL bit is set when the AWU counter overflows. The auto wakeup interrupt mask bit, AWUIE, is used to enable or disable AWU interrupt requests. The AWU shares its interrupt with the KBI vector. 52 4-1. MC68HC908QB8 Data Sheet, Rev. 3 Figure 4-1 applied Figure 4-1) has no effect on AWUL Freescale Semiconductor ...

  • Page 53

    ... There is no PTA6 port or any of the associated bits such as PTA6 data direction or pullup bits Auto wakeup interrupt request is pending 0 = Auto wakeup interrupt request is not pending PTA5–PTA0 bits are not used in conjuction with the auto wakeup feature. To see a description of these bits, see Freescale Semiconductor PTA5 ...

  • Page 54

    ... Bit 7 Read: 0 AWUIE Write: Reset Unimplemented Figure 4-4. Keyboard Interrupt Enable Register (KBIER KEYF NOTE 9.8.1 Keyboard Status and Control Register KBIE5 KBIE4 KBIE3 MC68HC908QB8 Data Sheet, Rev Bit 0 0 IMASKK MODEK ACKK Bit 0 KBIE2 KBIE1 KBIE0 Freescale Semiconductor ...

  • Page 55

    ... The configuration register 1 (CONFIG1), is used to select the period for the AWU. The timeout will be based on the COPRS bit along with the clock source for the AWU. Bit 7 Read: COPRS Write: 0 Reset: POR Unaffected Figure 4-6. Configuration Register 1 (CONFIG1) Freescale Semiconductor NOTE 9.8.2 Keyboard Interrupt Enable ESCI- 0 ...

  • Page 56

    ... Stop mode recovery after 32 BUSCLKX4 cycles 0 = Stop mode recovery after 4096 BUSCLKX4 cycles LVISTOP, LVIRST, LVIPWRD, LVITRIP and COPD bits are not used in conjuction with the auto wakeup feature. To see a description of these bits, see Chapter 5 Configuration Register (CONFIG) 56 NOTE MC68HC908QB8 Data Sheet, Rev. 3 Freescale Semiconductor ...

  • Page 57

    ... The CONFIG registers are one-time writable by the user after each reset. Upon a reset, the CONFIG registers default to predetermined settings as shown in Figure 5-1 Bit 7 6 Read: IRQPUD IRQEN Write: Reset POR Reserved R Figure 5-1. Configuration Register 2 (CONFIG2) Freescale Semiconductor NOTE and Figure 5- ESCIBDSRC OSCENINSTOP Unaffected MC68HC908QB8 Data Sheet, Rev ...

  • Page 58

    ... When the LVIPWRD bit is clear, setting the LVISTOP bit enables the LVI to operate during stop mode. Reset clears LVISTOP LVI enabled during stop mode 0 = LVI disabled during stop mode 58 DD NOTE LVIRSTD LVIPWRD LVITRIP MC68HC908QB8 Data Sheet, Rev Bit 0 SSREC STOP COPD Freescale Semiconductor ...

  • Page 59

    ... STOP instruction enabled 0 = STOP instruction treated as illegal opcode COPD — COP Disable Bit COPD disables the COP module COP module disabled 0 = COP module enabled Freescale Semiconductor for the LVI’s voltage trip points for each of the modes. DD NOTE NOTE MC68HC908QB8 Data Sheet, Rev. 3 ...

  • Page 60

    ... Configuration Register (CONFIG) 60 MC68HC908QB8 Data Sheet, Rev. 3 Freescale Semiconductor ...

  • Page 61

    ... COPEN (FROM SIM) COPD (FROM CONFIG1) RESET COPCTL WRITE COP RATE SELECT (COPRS FROM CONFIG1) 1. See Chapter 14 System Integration Module (SIM) Freescale Semiconductor SIM MODULE 12-BIT SIM COUNTER COP CLOCK COP MODULE 6-BIT COP COUNTER CLEAR COP COUNTER for more details. ...

  • Page 62

    ... The COPD signal reflects the state of the COP disable bit (COPD) in the configuration register (CONFIG). See Chapter 5 Configuration Register 62 NOTE NOTE Figure 6-1. Figure (CONFIG). MC68HC908QB8 Data Sheet, Rev. 3 14.8.1 SIM Reset Status Register. 6-2) clears the COP counter and Freescale Semiconductor ...

  • Page 63

    ... The COP control register (COPCTL) is located at address $FFFF and overlaps the reset vector. Writing any value to $FFFF clears the COP counter and starts a new timeout period. Reading location $FFFF returns the low byte of the reset vector. Bit 7 Read: Write: Reset: Figure 6-2. COP Control Register (COPCTL) Freescale Semiconductor (CONFIG). is present on the IRQ pin. TST ...

  • Page 64

    ... Computer Operating Properly (COP) 64 MC68HC908QB8 Data Sheet, Rev. 3 Freescale Semiconductor ...

  • Page 65

    ... Modular architecture with expandable internal bus definition for extension of addressing range beyond 64 Kbytes • Low-power stop and wait modes 7.3 CPU Registers Figure 7-1 shows the five CPU registers. CPU registers are not part of the memory map. Freescale Semiconductor MC68HC908QB8 Data Sheet, Rev ...

  • Page 66

    ... CONDITION CODE REGISTER (CCR) CARRY/BORROW FLAG ZERO FLAG NEGATIVE FLAG INTERRUPT MASK HALF-CARRY FLAG TWO’S COMPLEMENT OVERFLOW FLAG Figure 7-1. CPU Registers Unaffected by reset Figure 7-2. Accumulator ( Figure 7-3. Index Register (H:X) MC68HC908QB8 Data Sheet, Rev Bit 0 Bit Freescale Semiconductor ...

  • Page 67

    ... During reset, the program counter is loaded with the reset vector address located at $FFFE and $FFFF. The vector address is the address of the first instruction to be executed after exiting the reset state. Bit Read: Write: Reset: Freescale Semiconductor ...

  • Page 68

    ... N — Negative Flag The CPU sets the negative flag when an arithmetic operation, logic operation, or data manipulation produces a negative result, setting bit 7 of the result Negative result 0 = Non-negative result NOTE MC68HC908QB8 Data Sheet, Rev Bit Freescale Semiconductor ...

  • Page 69

    ... CPU instruction, the break interrupt begins immediately. A return-from-interrupt instruction (RTI) in the break routine ends the break interrupt and returns the MCU to normal operation if the break interrupt has been deasserted. Freescale Semiconductor MC68HC908QB8 Data Sheet, Rev. 3 Arithmetic/Logic Unit (ALU) ...

  • Page 70

    ... REL 27 rr – – – – – – REL – – – – – – REL 28 rr – – – – – – REL 29 rr – – – – – – REL 22 rr Freescale Semiconductor ...

  • Page 71

    ... Compare and Branch if Equal CBEQ opr,X+,rel CBEQ X+,rel CBEQ opr,SP,rel CLC Clear Carry Bit CLI Clear Interrupt Mask Freescale Semiconductor Description PC ← (PC rel ? ( ← (PC rel ? IRQ = 1 PC ← (PC rel ? IRQ = 0 (A) & (M) ⊕ PC ← (PC rel ? ( – – – – – – REL PC ← ...

  • Page 72

    ... INH 4A INH 5A – – – IX1 SP1 9E6A ff – – – – INH 52 IMM A8 ii DIR B8 dd EXT IX2 – – – IX1 SP1 9EE8 ff SP2 9ED8 ee ff DIR 3C dd INH 4C INH 5C – – – IX1 SP1 9E6C ff Freescale Semiconductor ...

  • Page 73

    ... ORA opr,X ORA ,X ORA opr,SP ORA opr,SP PSHA Push A onto Stack PSHH Push H onto Stack PSHX Push X onto Stack Freescale Semiconductor Description PC ← Jump Address PC ← (PC Push (PCL); SP ← (SP) – 1 Push (PCH); SP ← (SP) – ← Unconditional Address A ← (M) H:X ← (M ← (M) ...

  • Page 74

    ... DIR 35 dd – – 0 – – – INH 8E DIR BF dd EXT IX2 – – – IX1 SP1 9EEF ff SP2 9EDF ee ff IMM A0 ii DIR B0 dd EXT IX2 – – IX1 SP1 9EE0 ff SP2 9ED0 ee ff Freescale Semiconductor ...

  • Page 75

    ... M Memory location N Negative bit 7.8 Opcode Map See Table 7-2. Freescale Semiconductor Description PC ← (PC Push (PCL) SP ← (SP) – 1; Push (PCH) SP ← (SP) – 1; Push (X) SP ← (SP) – 1; Push (A) SP ← (SP) – 1; Push (CCR) SP ← (SP) – ← 1 PCH ← Interrupt Vector High Byte PCL ← ...

  • Page 76

    Bit Manipulation Branch Read-Modify-Write DIR DIR REL DIR INH MSB LSB BRSET0 BSET0 BRA NEG NEGA NEGX 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 5 ...

  • Page 77

    ... The external IRQ pin is falling edge sensitive out of reset and is software-configurable to be either falling edge or falling edge and low level sensitive. The MODE bit in INTSCR controls the triggering sensitivity of the IRQ pin. Freescale Semiconductor for more information on enabling the IRQ pin. MC68HC908QB8 Data Sheet, Rev. 3 ...

  • Page 78

    ... MC68HC908QB8 Data Sheet, Rev. 3 CLOCK GENERATOR KEYBOARD INTERRUPT MODULE EXTERNAL INTERRUPT MODULE AUTO WAKEUP MODULE LOW-VOLTAGE INHIBIT 4-CHANNEL 16-BIT TIMER MODULE COP MODULE 10-CHANNEL 10-BIT ADC ENHANCED SERIAL COMMUNICATIONS INTERFACE MODULE SERIAL PERIPHERAL INTERFACE DEVELOPMENT SUPPORT MONITOR ROM BREAK MODULE Freescale Semiconductor ...

  • Page 79

    ... The IRQF bit in INTSCR can be read to check for pending interrupts. The IRQF bit is not affected by IMASK, which makes it useful in applications where polling is preferred. When using the level-sensitive interrupt trigger, avoid false IRQ interrupts by masking interrupt requests in the interrupt routine. Freescale Semiconductor V DD CLR ...

  • Page 80

    ... I/O Signals The IRQ module does not share its pin with any module on this MCU. 8.7.1 IRQ Input Pins (IRQ) The IRQ pin provides a maskable external interrupt source. The IRQ pin contains an internal pullup device. 80 MC68HC908QB8 Data Sheet, Rev. 3 sheet. Freescale Semiconductor ...

  • Page 81

    ... Writing this read/write bit disables the IRQ interrupt request IRQ interrupt request disabled 0 = IRQ interrupt request enabled MODE — IRQ Edge/Level Select Bit This read/write bit controls the triggering sensitivity of the IRQ pin IRQ interrupt request on falling edges and low levels 0 = IRQ interrupt request on falling edges only Freescale Semiconductor ...

  • Page 82

    ... External Interrupt (IRQ) 82 MC68HC908QB8 Data Sheet, Rev. 3 Freescale Semiconductor ...

  • Page 83

    ... If the keyboard interrupt is edge and level sensitive, an interrupt request is present as long as any enabled keyboard interrupt input is asserted. Freescale Semiconductor MC68HC908QB8 Data Sheet, Rev. 3 Figure 9-1 for port location Figure 9-2 ...

  • Page 84

    ... MC68HC908QB8 Data Sheet, Rev. 3 CLOCK GENERATOR KEYBOARD INTERRUPT MODULE EXTERNAL INTERRUPT MODULE AUTO WAKEUP MODULE LOW-VOLTAGE INHIBIT 4-CHANNEL 16-BIT TIMER MODULE COP MODULE 10-CHANNEL 10-BIT ADC ENHANCED SERIAL COMMUNICATIONS INTERFACE MODULE SERIAL PERIPHERAL INTERFACE DEVELOPMENT SUPPORT MONITOR ROM BREAK MODULE Freescale Semiconductor ...

  • Page 85

    ... IMASKK, which makes it useful in applications where polling is preferred. Setting a keyboard interrupt enable bit (KBIEx) forces the corresponding keyboard interrupt pin input, overriding the data direction register. However, the data direction register bit must for software to read the pin. Freescale Semiconductor V DD CLR D ...

  • Page 86

    ... If software does the first step on such a bit before the break, the bit cannot change during the break state as long as BCFE is cleared. After the break, doing the second step clears the status bit. 86 MC68HC908QB8 Data Sheet, Rev. 3 sheet. Freescale Semiconductor ...

  • Page 87

    ... Writing this read/write bit prevents the output of the KBI latch from generating interrupt requests Keyboard interrupt requests disabled 0 = Keyboard interrupt requests enabled MODEK — Keyboard Triggering Sensitivity Bit This read/write bit controls the triggering sensitivity of the keyboard interrupt pins Keyboard interrupt requests on edge and level 0 = Keyboard interrupt requests on edge only Freescale Semiconductor ...

  • Page 88

    ... Each of these read/write bits enables the polarity of the keyboard interrupt detection Keyboard polarity is high level and/or rising edge 0 = Keyboard polarity is low level and/or falling edge KBIE5 KBIE4 KBIE3 NOTE Chapter 4 Auto Wakeup Module (AWU KBIP5 KBIP4 KBIP3 MC68HC908QB8 Data Sheet, Rev Bit 0 KBIE2 KBIE1 KBIE0 Bit 0 KBIP2 KBIP1 KBIP0 Freescale Semiconductor ...

  • Page 89

    ... LVI module. LVISTOP, LVIPWRD, LVITRIP, and LVIRSTD are user selectable options found in the configuration register FROM CONFIGURATION REGISTER LOW V DD DETECTOR LVITRIP FROM CONFIGURATION REGISTER Freescale Semiconductor Chapter 5 Configuration Register STOP INSTRUCTION FROM CONFIGURATION REGISTER LVIRSTD LVIPWRD > TRIPR ≤ ...

  • Page 90

    ... DD is greater than V by the typical hysteresis voltage, V TRIPR TRIPF NOTE MC68HC908QB8 Data Sheet, Rev. 3 operating range. The actual DD and 18.8 3-V DC Electrical must See Chapter 14 System TRIPR ) for the higher V TRIPF by polling DD Freescale Semiconductor HYS ...

  • Page 91

    ... The LVI status register (LVISR) contains a status bit that is useful when the LVI is enabled and LVI reset is disabled. Bit 7 Read: LVIOUT Write: Reset Unimplemented Figure 10-2. LVI Status Register (LVISR) LVIOUT — LVI Output Bit This read-only flag becomes set when the V when V voltage rises above Freescale Semiconductor voltage falls below the V DD ...

  • Page 92

    ... Low-Voltage Inhibit (LVI) 92 MC68HC908QB8 Data Sheet, Rev. 3 Freescale Semiconductor ...

  • Page 93

    ... The oscillator contains these major subsystems: • Internal oscillator circuit • Internal or external clock switch control • External clock circuit • External crystal circuit • External RC clock circuit Freescale Semiconductor for information on PTAPUEN register. MC68HC908QB8 Data Sheet, Rev. 3 Figure 11-1 for port 93 ...

  • Page 94

    ... MC68HC908QB8 Data Sheet, Rev. 3 CLOCK GENERATOR KEYBOARD INTERRUPT MODULE EXTERNAL INTERRUPT MODULE AUTO WAKEUP MODULE LOW-VOLTAGE INHIBIT 4-CHANNEL 16-BIT TIMER MODULE COP MODULE 10-CHANNEL 10-BIT ADC ENHANCED SERIAL COMMUNICATIONS INTERFACE MODULE SERIAL PERIPHERAL INTERFACE DEVELOPMENT SUPPORT MONITOR ROM BREAK MODULE Freescale Semiconductor ...

  • Page 95

    ... MHz, 2.0 MHz, or 1.0 MHz respectively. The bus clock is software selectable and defaults to the 1.0-MHz bus out of reset. Users can increase the bus frequency based on the voltage range of their application. Freescale Semiconductor Figure 11-2 shows only the logical relation of XTALCLK to OSC1 ...

  • Page 96

    ... BUSCLKX4 and also divided by two to create BUSCLKX2. In this configuration, the OSC2 pin cannot output BUSCLKX4. The OSC2EN bit will be forced clear to enable alternative functions on the pin. 96 11.8.1 Oscillator Status and Control MC68HC908QB8 Data Sheet, Rev. 3 Register. Freescale Semiconductor ...

  • Page 97

    ... Refer to the oscillator characteristics table in the Electricals section for more information. SIMOSCEN (INTERNAL SIGNAL) OR OSCENINSTOP (BIT LOCATED IN CONFIGURATION REGISTER) MCU OSC1 Figure 11-2. XTAL Oscillator External Connections Freescale Semiconductor NOTE ) is included in the diagram to follow strict Pierce S BUSCLKX4 BUSCLKX2 XTALCLK ÷ 2 ...

  • Page 98

    ... OSC2 — AVAILABLE FOR ALTERNATIVE PIN FUNCTION See the electricals section for component value. MC68HC908QB8 Data Sheet, Rev provide a clock source with EXT 11-3. value must have a tolerance of EXT . RCCLK OSCOPT = EXTERNAL RC SELECTED BUSCLKX2 BUSCLKX4 ÷ 2 ALTERNATIVE PIN FUNTION OSC2EN Freescale Semiconductor ...

  • Page 99

    ... RC, the OSC2 pin can be used to output BUSCLKX4. Option XTAL oscillator External clock Internal oscillator or RC oscillator Freescale Semiconductor Table 11-1. OSC2 Pin Function OSC2 Pin Function Inverting OSC1 General-purpose I/O or alternative pin function Controlled by OSC2EN bit OSC2EN = 0: General-purpose I/O or alternative pin function OSC2EN = 1: BUSCLKX4 output MC68HC908QB8 Data Sheet, Rev ...

  • Page 100

    ... Internal oscillator (frequency selected using ICFSx bits) 1 External oscillator clock 0 External RC 1 External crystal (range selected using ECFSx bits) ICFS0 Internal Clock Frequency 0 4.0 MHz — default reset condition 1 8.0 MHz 0 12.8 MHz 1 Reserved MC68HC908QB8 Data Sheet, Rev Bit 0 ECGST ECFS0 ECGON 11.3.2.2 Internal to External Freescale Semiconductor ...

  • Page 101

    ... The oscillator period is based on the oscillator frequency selected by the ICFS bits in OSCSC. Applications using the internal oscillator should copy the internal oscillator trim value at location $FFC0 into this register to trim the clock source. Freescale Semiconductor ECFS0 External Crystal Frequency 0 8 MHz – ...

  • Page 102

    ... Oscillator Module (OSC) 102 MC68HC908QB8 Data Sheet, Rev. 3 Freescale Semiconductor ...

  • Page 103

    ... PTA2 pin. When the IRQ function is disabled, these instructions will behave as if the PTA2 pin is a logic 1. However, reading bit 2 of PTA will read the actual logic level on the pin. Freescale Semiconductor NOTE (KBI), the 4-channel timer interface module (TIM) (see ...

  • Page 104

    ... A I/O logic. 104 PTA5 PTA4 PTA3 Unaffected by reset Figure 12-1. Port A Data Register (PTA) Chapter 4 Auto Wakeup Module DDRA5 DDRA4 DDRA3 Unimplemented NOTE MC68HC908QB8 Data Sheet, Rev Bit 0 PTA2 PTA1 PTA0 (AWU)). There is no PTA6 2 1 Bit 0 0 DDRA1 DDRA0 Freescale Semiconductor ...

  • Page 105

    ... These read/write bits are software programmable to enable pullup devices on port A pins Corresponding port A pin configured to have internal pullup if its DDRA bit is set Pullup device is disconnected on the corresponding port A pin regardless of the state of its DDRA bit Freescale Semiconductor DDRAx RESET PTAx Figure 12-3. Port A I/O Circuit ...

  • Page 106

    ... PTB5 PTB4 PTB3 Unaffected by reset Figure 12-5. Port B Data Register (PTB) MC68HC908QB8 Data Sheet, Rev. 3 Accesses to PTA Read Write Pin PTA5–PTA0 Pin PTA5–PTA0 PTA5–PTA0 PTA5–PTA0 Chapter 3 Analog-to-Digital Chapter 15 Serial Module Bit 0 PTB2 PTB1 PTB0 Freescale Semiconductor (3) (3) (5) ...

  • Page 107

    ... WRITE DDRB WRITE PTB READ PTB When DDRBx reading PTB reads the PTBx data latch. When DDRBx reading PTB reads the logic level on the PTBx pin. The data latch can always be written, regardless of the state of its data direction bit. Freescale Semiconductor DDRB5 ...

  • Page 108

    ... Writing affects data register, but does not affect the input. 108 PTBPUE5 PTBPUE4 PTBPUE3 Table 12-2. Port B Pin Functions Accesses to DDRB Read/Write (2) DDRB7–DDRB0 DDRB7–DDRB0 MC68HC908QB8 Data Sheet, Rev Bit 0 PTBPUE2 PTBPUE2 PTBPUE0 Accesses to PTB Read Write Pin PTB7–PTB0 Pin PTB7–PTB0 Freescale Semiconductor (3) ...

  • Page 109

    ... Receiver full – Idle receiver input – Receiver overrun – Noise error – Framing error – Parity error • Receiver framing error detection • Hardware parity checking • 1/16 bit-time noise detection Freescale Semiconductor MC68HC908QB8 Data Sheet, Rev. 3 Figure 13-1 for 109 ...

  • Page 110

    ... MC68HC908QB8 Data Sheet, Rev. 3 CLOCK GENERATOR KEYBOARD INTERRUPT MODULE EXTERNAL INTERRUPT MODULE AUTO WAKEUP MODULE LOW-VOLTAGE INHIBIT 4-CHANNEL 16-BIT TIMER MODULE COP MODULE 10-CHANNEL 10-BIT ADC ENHANCED SERIAL COMMUNICATIONS INTERFACE MODULE SERIAL PERIPHERAL INTERFACE DEVELOPMENT SUPPORT MONITOR ROM BREAK MODULE Freescale Semiconductor ...

  • Page 111

    ... TCIE SCRIE ILIE TE RE RWU SBK WAKEUP CONTROL BUS CLOCK ENHANCED PRESCALER BUSCLKX4 ÷ -> SCI_CLK = BUSCLK -> SCI_CLK = BUSCLKX4 Figure 13-2. ESCI Module Block Diagram Freescale Semiconductor INTERNAL BUS SCTE TC SCRF OR IDLE LOOPS RECEIVE FLAG CONTROL CONTROL BKF ENSCI RPF PRE- BAUD RATE ...

  • Page 112

    ... Figure 13-4. ESCI Transmitter MC68HC908QB8 Data Sheet, Rev. 3 Figure 13-3. NEXT BIT START BIT BIT 7 STOP BIT PARITY OR DATA NEXT BIT START BIT BIT 7 BIT 8 STOP BIT INTERNAL BUS 11-BIT TRANSMIT START TRANSMITTER CONTROL LOGIC SBK LOOPS ENSCI TE LINT Freescale Semiconductor SCI_TxD ...

  • Page 113

    ... When LINR is set in SCBR, the ESCI recognizes a break character when a start bit is followed data bits and a 0 where the stop bit should be, resulting in a total consecutive 0 data bits. Freescale Semiconductor MC68HC908QB8 Data Sheet, Rev. 3 Functional Description 113 ...

  • Page 114

    ... SCDR. The ESCI receiver full bit, SCRF, in ESCI status register 1 (SCS1) becomes set, indicating that the received byte can be read. If the ESCI receive interrupt enable bit, SCRIE, in SCC2 is also set, the SCRF bit generates a receiver interrupt request. 114 MC68HC908QB8 Data Sheet, Rev. 3 Freescale Semiconductor ...

  • Page 115

    ... BUS CLOCK M PSSB4 WAKE PSSB3 ILTY PSSB2 PSSB1 PEN PSSB0 PTY RECEIVER INTERRUPT REQUEST ERROR INTERRUPT REQUEST Figure 13-5. ESCI Receiver Block Diagram Freescale Semiconductor INTERNAL BUS SCR2 SCR1 SCR0 BAUD ÷ 16 DIVIDER DATA H RxD RECOVERY ALL ZEROS WAKEUP LOGIC PARITY CHECKING ...

  • Page 116

    ... START BIT START BIT DATA QUALIFICATION VERIFICATION SAMPLING Figure 13-6. Receiver Data Sampling Table 13-1. Start Bit Verification Start Bit Verification 000 Yes 001 Yes 010 Yes 011 No 100 Yes 101 No 110 No 111 No MC68HC908QB8 Data Sheet, Rev. 3 LSB Noise Flag Freescale Semiconductor ...

  • Page 117

    ... As the receiver samples an incoming character, it resynchronizes the RT clock on any valid falling edge within the character. Resynchronization within characters corrects misalignments between transmitter bit times and receiver bit times. Freescale Semiconductor Table 13-2. Data Bit Recovery Data Bit Determination 000 ...

  • Page 118

    ... Figure 13-7, the receiver counts 170 RT cycles at the point when 170 163 – × 100 = 4.12% ------------------------- - 170 STOP IDLE OR NEXT CHARACTER DATA SAMPLES Figure 13-8. Fast Data MC68HC908QB8 Data Sheet, Rev. 3 STOP Freescale Semiconductor ...

  • Page 119

    ... With the WAKE bit clear, setting the RWU bit after the RxD pin has been idle will cause the receiver to wake up. 13.4 Interrupts The following sources can generate ESCI interrupt requests. Freescale Semiconductor Figure 13-8, the receiver counts 154 RT cycles at the point when 154 160 – ...

  • Page 120

    ... The ESCI module remains active in wait mode. Any enabled interrupt request from the ESCI module can bring the MCU out of wait mode. If ESCI module functions are not required during wait mode, reduce power consumption by disabling the module before executing the WAIT instruction. 120 MC68HC908QB8 Data Sheet, Rev. 3 Freescale Semiconductor ...

  • Page 121

    ... ESCI baud rate register, SCBR • ESCI prescaler register, SCPSC • ESCI arbiter control register, SCIACTL • ESCI arbiter data register, SCIADAT Freescale Semiconductor MC68HC908QB8 Data Sheet, Rev. 3 ESCI During Break Interrupts sheet. Figure 13-1 for the port pins 121 ...

  • Page 122

    ... This read/write bit determines whether ESCI characters are eight or nine bits long (see Table 13-4).The ninth bit can serve as a receiver wakeup signal parity bit 9-bit ESCI characters 0 = 8-bit ESCI characters 122 TXINV M WAKE NOTE MC68HC908QB8 Data Sheet, Rev Bit 0 ILTY PEN PTY Freescale Semiconductor ...

  • Page 123

    ... SCTE bit to generate transmitter interrupt requests – TC bit to generate transmitter interrupt requests – SCRF bit to generate receiver interrupt requests – IDLE bit to generate receiver interrupt requests • Enables the transmitter Freescale Semiconductor Table 13-4. Character Format Selection Character Format Start Bits Data Bits Parity 1 8 None ...

  • Page 124

    ... RE — Receiver Enable Bit Setting this read/write bit enables the receiver. Clearing the RE bit disables the receiver but does not affect receiver interrupt flag bits Receiver enabled 0 = Receiver disabled 124 TCIE SCRIE ILIE NOTE MC68HC908QB8 Data Sheet, Rev Bit 0 RE RWU SBK Freescale Semiconductor ...

  • Page 125

    ... When the ESCI is receiving 8-bit characters copy of the eighth bit (bit 7). T8 — Transmitted Bit 8 When the ESCI is transmitting 9-bit characters the read/write ninth bit (bit 8) of the transmitted character loaded into the transmit shift register at the same time that the SCDR is loaded into the transmit shift register. Freescale Semiconductor NOTE NOTE 6 5 ...

  • Page 126

    ... ESCI transmitter interrupt request. In normal operation, clear the SCTE bit by reading SCS1 with SCTE set and then writing to SCDR 1 = SCDR data transferred to transmit shift register 0 = SCDR data not transferred to transmit shift register 126 SCRF IDLE MC68HC908QB8 Data Sheet, Rev Bit Freescale Semiconductor ...

  • Page 127

    ... This clearable, read-only bit is set when the ESCI detects noise on the RxD pin. NF generates an NF interrupt request if the NEIE bit in SCC3 is also set. Clear the NF bit by reading SCS1 and then reading the SCDR Noise detected noise detected Freescale Semiconductor MC68HC908QB8 Data Sheet, Rev. 3 Registers 127 ...

  • Page 128

    ... READ SCDR BYTE 1 BYTE 2 DELAYED FLAG CLEARING SEQUENCE BYTE 2 BYTE 3 READ SCS1 SCRF = READ SCDR BYTE 1 Figure 13-13. Flag Clearing Sequence MC68HC908QB8 Data Sheet, Rev. 3 BYTE 4 READ SCS1 SCRF = READ SCDR BYTE 3 BYTE 4 READ SCS1 SCRF = READ SCDR BYTE 3 Freescale Semiconductor ...

  • Page 129

    ... Read: R7 Write: T7 Reset: Figure 13-15. ESCI Data Register (SCDR) R7/T7:R0/T0 — Receive/Transmit Data Bits Reading SCDR accesses the read-only received data bits, R7:R0. Writing to SCDR writes the data to be transmitted, T7:T0. Do not use read-modify-write instructions on the ESCI data register. Freescale Semiconductor ...

  • Page 130

    ... LIN receiver 0 13-bit generation enabled for LIN transmitter 1 14-bit generation enabled for LIN transmitter 0 11-bit break detect/13-bit generation enabled for LIN 1 12-bit break detect/14-bit generation enabled for LIN MC68HC908QB8 Data Sheet, Rev Bit 0 SCR2 SCR1 SCR0 Freescale Semiconductor ...

  • Page 131

    ... ESCI baud rate register and one in the ESCI prescaler register. Bit 7 Read: PDS2 Write: Reset: 0 Figure 13-17. ESCI Prescaler Register (SCPSC) Freescale Semiconductor Table 13-6. ESCI Baud Rate Prescaling Baud Rate Register Prescaler Divisor (BPD Table 13-7. ESCI Baud Rate Selection ...

  • Page 132

    ... Prescaler Divisor Fine Adjust (PDFA) 0/ 1/32 = 0.03125 2/32 = 0.0625 3/32 = 0.09375 4/32 = 0.125 5/32 = 0.15625 6/32 = 0.1875 7/32 = 0.21875 8/32 = 0.25 9/32 = 0.28125 10/32 = 0.3125 11/32 = 0.34375 12/32 = 0.375 13/32 = 0.40625 14/32 = 0.4375 Continued on next page MC68HC908QB8 Data Sheet, Rev. 3 13-8. Table 13-9. Freescale Semiconductor ...

  • Page 133

    ... BPD = Baud rate register prescaler divisor BD = Baud rate divisor PD = Prescaler divisor PDFA = Prescaler divisor fine adjust Table 13-10 shows the ESCI baud rates that can be generated with a 4.9152-MHz bus frequency. Freescale Semiconductor Prescaler Divisor Fine Adjust (PDFA) 15/32 = 0.46875 16/32 = 0.5 17/32 = 0.53125 18/32 = 0.5625 19/ ...

  • Page 134

    ... Freescale Semiconductor ...

  • Page 135

    ... ESCIBDSRC bit in configuration register. AFIN— Arbiter Bit Time Measurement Finish Flag This read-only bit indicates bit time measurement has finished. Clear AFIN by writing any value to SCIACTL Bit time measurement has finished 0 = Bit time measurement not yet finished Freescale Semiconductor AFIN ...

  • Page 136

    ... ACLK = 1 leads to immediate start of the counter (see Figure 13-22). The counter will be stopped on the next rising edge of RxD. This mode is used to measure the length of a received break. 136 ARD6 ARD5 ARD4 ARD3 MC68HC908QB8 Data Sheet, Rev Bit 0 ARD2 ARD1 ARD0 Figure 13-21 RxD on Freescale Semiconductor ...

  • Page 137

    ... RXD Figure 13-20. Bit Time Measurement with ACLK = 0 RXD Figure 13-21. Bit Time Measurement with ACLK = 1, Scenario A RXD Figure 13-22. Bit Time Measurement with ACLK = 1, Scenario B Freescale Semiconductor MEASURED TIME MEASURED TIME MEASURED TIME MC68HC908QB8 Data Sheet, Rev. 3 ESCI Arbiter 137 ...

  • Page 138

    ... If SCI_TxD senses 0 without having sensed a 0 before on RxD, the counter will be reset, arbitration operation will be restarted after the next rising edge of SCI_TxD. 138 Figure 13-2), the counter is started. When the counter reaches MC68HC908QB8 Data Sheet, Rev. 3 Freescale Semiconductor ...

  • Page 139

    ... R/W 14.2 RST and IRQ Pins Initialization RST and IRQ pins come out of reset as PTA3 and PTA2 respectively. RST and IRQ functions can be activated by programing CONFIG2 accordingly. Refer to Freescale Semiconductor Figure Table 14-1. Signal Name Conventions Description Buffered clock from the internal XTAL oscillator circuit. ...

  • Page 140

    ... BUSCLKX2 (FROM OSCILLATOR) INTERNAL CLOCKS ILLEGAL OPCODE (FROM CPU) ILLEGAL ADDRESS (FROM ADDRESS MAP DECODERS) COP TIMEOUT (FROM COP MODULE) LVI RESET (FROM LVI MODULE) FORCED MON MODE ENTRY (FROM MENRST MODULE) INTERRUPT SOURCES CPU INTERFACE Figure 14-2. BUS CLOCK GENERATORS Freescale Semiconductor ...

  • Page 141

    ... Figure 14 the RSTEN bit is set in the CONFIG2 register. BUSCLKX2 RST ADDRESS BUS PC Freescale Semiconductor 14.7.2 Stop Mode. 14.5 SIM Counter), but an external reset does not. Each of shows the relative timing. The RST pin function is only available VECT H VECT L Figure 14-3. External Reset Timing MC68HC908QB8 Data Sheet, Rev ...

  • Page 142

    ... CYCLES 32 CYCLES Figure 14-4. Internal Reset Timing ILLEGAL ADDRESS RST ILLEGAL OPCODE RST COPRST INTERNAL RESET POR LVI Figure 14-5. Sources of Internal Reset Table 14-2. Reset Recovery Timing Actual Number of Cycles 4163 (4096 + MC68HC908QB8 Data Sheet, Rev. 3 VECTOR HIGH 67 ( Freescale Semiconductor ...

  • Page 143

    ... The COP module is disabled during a break interrupt with monitor mode when BDCOP bit is set in break auxiliary register (BRKAR). 14.4.2.3 Illegal Opcode Reset The SIM decodes signals from the CPU to detect illegal instructions. An illegal instruction sets the ILOP bit in the SIM reset status register (SRSR) and causes a reset. Freescale Semiconductor 4096 32 32 CYCLES ...

  • Page 144

    ... LVI trip voltage V DD rises above V DD 14.7.2 Stop Mode 14.4.2 Active Resets from Internal Sources MC68HC908QB8 Data Sheet, Rev. 3 for memory ranges. . The LVI TRIPF . Sixty-four BUSCLKX4 TRIPR for details.) The SIM counter is for counter control and Freescale Semiconductor ...

  • Page 145

    ... If the interrupt service routine modifies the H register or uses the indexed addressing mode, software should save the H register and then restore it prior to exiting the routine. Freescale Semiconductor shows interrupt recovery timing. NOTE MC68HC908QB8 Data Sheet, Rev. 3 ...

  • Page 146

    ... I BIT SET? NO YES IRQ INTERRUPT? NO YES TIMER INTERRUPT? NO LOAD PC WITH INTERRUPT VECTOR FETCH NEXT INSTRUCTION SWI YES INSTRUCTION? NO RTI YES UNSTACK CPU REGISTERS INSTRUCTION? NO Figure 14-7. Interrupt Processing MC68HC908QB8 Data Sheet, Rev. 3 STACK CPU REGISTERS SET I BIT EXECUTE INSTRUCTION Freescale Semiconductor ...

  • Page 147

    ... I BIT ADDRESS BUS DUMMY SP DATA BUS DUMMY R/W MODULE INTERRUPT I BIT ADDRESS BUS SP – 4 DATA BUS R/W INT1 INT2 Figure 14-10 Freescale Semiconductor SP – – – – – 1[7:0] PC – 1[15: Figure 14-8 Interrupt Entry SP – – – 1 CCR – 1[7:0] PC – 1[15:8] OPCODE Figure 14-9 ...

  • Page 148

    ... IF6 $FFF0–$FFF1 IF7 $FFEE–$FFEF IF9 $FFEA–$FFEB IF10 $FFE8–$FFE9 IF11 $FFE6–$FFE7 IF12 $FFE4–$FFE5 IF13 $FFE2–$FFE3 IF14 $FFE0–$FFE1 IF15 $FFDE–$FFDF Freescale Semiconductor ...

  • Page 149

    ... Interrupt Status Register 3 Bit 7 Read: IF22 Write: R Reset Reserved Figure 14-13. Interrupt Status Register 3 (INT3) IF15–I 22 — Interrupt Flags F These flags indicate the presence of interrupt requests from the sources shown Interrupt request present interrupt request present Freescale Semiconductor IF5 IF4 IF3 ...

  • Page 150

    ... Stacking for the interrupt begins one cycle after the WAIT instruction during which the interrupt occurred. 150 Support.) The SIM puts the CPU into the break WAIT ADDR + 1 SAME PREVIOUS DATA NEXT OPCODE Figure 14-14. Wait Mode Entry Timing MC68HC908QB8 Data Sheet, Rev. 3 Figure 14-14 shows SAME SAME SAME Freescale Semiconductor ...

  • Page 151

    ... This is ideal for the internal oscillator, RC oscillator, and external oscillator options which do not require long start-up times from stop mode. External crystal applications should use the full stop recovery time by clearing the SSREC bit. Freescale Semiconductor show the timing for wait recovery. $6E0B $6E0C ...

  • Page 152

    ... PREVIOUS DATA NEXT OPCODE Figure 14-17. Stop Mode Entry Timing STOP RECOVERY PERIOD STOP +1 STOP + 2 STOP + PIN COP ILOP ILAD MC68HC908QB8 Data Sheet, Rev. 3 shows stop mode entry timing and SAME SAME SAME SP SP – – – Bit 0 MODRST LVI Freescale Semiconductor ...

  • Page 153

    ... This read/write bit enables software to clear status bits by accessing status registers while the MCU break state. To clear status bits during the break state, the BCFE bit must be set Status bits clearable during break 0 = Status bits not clearable during break Freescale Semiconductor ...

  • Page 154

    ... System Integration Module (SIM) 154 MC68HC908QB8 Data Sheet, Rev. 3 Freescale Semiconductor ...

  • Page 155

    ... SPRF (SPI receiver full) – SPTE (SPI transmitter empty) • Mode fault error flag with interrupt capability • Overflow error flag with interrupt capability • Programmable wired-OR mode Freescale Semiconductor MC68HC908QB8 Data Sheet, Rev. 3 Figure 15-1 for port location 155 ...

  • Page 156

    ... MC68HC908QB8 Data Sheet, Rev. 3 CLOCK GENERATOR KEYBOARD INTERRUPT MODULE EXTERNAL INTERRUPT MODULE AUTO WAKEUP MODULE LOW-VOLTAGE INHIBIT 4-CHANNEL 16-BIT TIMER MODULE COP MODULE 10-CHANNEL 10-BIT ADC ENHANCED SERIAL COMMUNICATIONS INTERFACE MODULE SERIAL PERIPHERAL INTERFACE DEVELOPMENT SUPPORT MONITOR ROM BREAK MODULE Freescale Semiconductor ...

  • Page 157

    ... The following paragraphs describe the operation of the SPI module. BUSCLK ÷ 2 ÷ 8 CLOCK DIVIDER ÷ 32 ÷ 128 CLOCK SPMSTR SPE SELECT SPR1 TRANSMITTER INTERRUPT REQUEST RECEIVER/ERROR INTERRUPT REQUEST Freescale Semiconductor INTERNAL BUS TRANSMIT DATA REGISTER SHIFT REGISTER RECEIVE DATA REGISTER SPR0 SPMSTR MODFEN ...

  • Page 158

    ... SPI configured as a slave does not have to correspond to any SPI baud rate. The baud rate only 158 NOTE Figure 15-3. MISO MISO MOSI MOSI SPSCK SPSCK Register.) Through the SPSCK pin, the baud rate generator of the MC68HC908QB8 Data Sheet, Rev. 3 15.8.1 SPI SLAVE MCU SHIFT REGISTER 15.3.6.2 Mode Fault Error. Freescale Semiconductor ...

  • Page 159

    ... Therefore, the SPI data register of the slave must be loaded with transmit data before the falling edge of SS. Any data written after the falling edge is stored in the transmit data register and transferred to the shift register after the current transmission. Freescale Semiconductor 15.3.3 Transmission NOTE NOTE MC68HC908QB8 Data Sheet, Rev ...

  • Page 160

    ... Therefore, the slave uses the first SPSCK edge as a start transmission signal. The SS pin can 160 MSB BIT 6 BIT 5 BIT 4 BIT 3 MSB BIT 6 BIT 5 BIT 4 BIT 3 15.3.6.2 Mode Fault BYTE 1 BYTE 2 Figure 15-5. CPHA/SS Timing MC68HC908QB8 Data Sheet, Rev BIT 2 BIT 1 LSB BIT 2 BIT 1 LSB Error.) When CPHA = 0, the first BYTE 3 Freescale Semiconductor ...

  • Page 161

    ... Figure 15-7. This delay is no longer than a single SPI bit time. That is, the maximum delay is two MCU bus cycles for DIV2, eight MCU bus cycles for DIV8, 32 MCU bus cycles for DIV32, and 128 MCU bus cycles for DIV128. Freescale Semiconductor ...

  • Page 162

    ... POSSIBLE START POINTS LATEST SPSCK = BUS CLOCK ÷ 8; EARLIEST 8 POSSIBLE START POINTS EARLIEST SPSCK = BUS CLOCK ÷ 32; 32 POSSIBLE START POINTS SPSCK = BUS CLOCK ÷ 128; EARLIEST 128 POSSIBLE START POINTS MC68HC908QB8 Data Sheet, Rev. 3 BIT 6 BIT LATEST LATEST LATEST Freescale Semiconductor ...

  • Page 163

    ... For an already active slave, the load of the shift register cannot occur until the transmission is completed. This implies that a back-to-back write to the transmit data register is not possible. SPTE indicates when the next write can occur. Freescale Semiconductor 3 8 ...

  • Page 164

    ... OVRF bit can be set in between the time that SPSCR and SPDR are read. 164 Figure 15-4 and Figure MC68HC908QB8 Data Sheet, Rev. 3 15-6 overflow occurs, all data Figure 15-11 not possible Figure 15-9 shows how it is Freescale Semiconductor ...

  • Page 165

    ... READ SPSCR WITH SPRF BIT SET AND OVRF BIT CLEAR. 3 READ BYTE 1 IN SPDR, CLEARING SPRF BIT. 4 READ SPSCR AGAIN TO CHECK OVRF BIT. Figure 15-10. Clearing SPRF When OVRF Interrupt Is Not Enabled Freescale Semiconductor Figure 15-10 illustrates this process. Generally, to avoid this second BYTE 2 BYTE ...

  • Page 166

    ... MSB) for CPHA = 0. When CPHA = 1, a slave can be selected and then later unselected with no transmission occurring. Therefore, MODF does not occur because a transmission was never begun. 166 NOTE NOTE MC68HC908QB8 Data Sheet, Rev. 3 Figure 15-11 not possible Freescale Semiconductor ...

  • Page 167

    ... The SPI receiver interrupt enable bit (SPRIE) enables SPRF to generate receiver interrupt requests, regardless of the state of SPE. See ERRIE MODF OVRF Figure 15-11. SPI Interrupt Request Generation Freescale Semiconductor NOTE Table 15-1. SPI Interrupts Request SPI transmitter interrupt request (SPTIE = 1, SPE = 1) ...

  • Page 168

    ... If software does the first step on such a bit before the break, the bit cannot change during the break state as long as BCFE is cleared. After the break, doing the second step clears the status bit. 168 15.4 Interrupts. MC68HC908QB8 Data Sheet, Rev. 3 sheet. Freescale Semiconductor ...

  • Page 169

    ... Formats.) Because it is used to indicate the start of a transmission, SS must be toggled high and low between each byte transmitted for the CPHA = 0 format. However, it can remain low between transmissions for the CPHA = 1 format. See Freescale Semiconductor Figure 15-12. MC68HC908QB8 Data Sheet, Rev. 3 ...

  • Page 170

    ... Table 15-2. SPI Configuration MODFEN SPI Configuration X Not enabled X Slave 0 Master without MODF 1 Master with MODF MC68HC908QB8 Data Sheet, Rev. 3 BYTE 3 Error.) For the state Function of SS Pin General-purpose I/O; SS ignored by SPI Input-only to SPI General-purpose I/O; SS ignored by SPI Input-only to SPI Freescale Semiconductor ...

  • Page 171

    ... Wired-OR SPSCK, MOSI, and MISO pins 0 = Normal push-pull SPSCK, MOSI, and MISO pins SPE — SPI Enable This read/write bit enables the SPI module. Clearing SPE causes a partial reset of the SPI. (See Resetting the SPI SPI module enabled 0 = SPI module disabled Freescale Semiconductor SPMSTR CPOL ...

  • Page 172

    ... Clear the OVRF bit by reading the SPI status and control register with OVRF set and then reading the receive data register Overflow overflow 172 OVRF MODF SPTE MC68HC908QB8 Data Sheet, Rev Bit 0 MODFEN SPR1 SPR0 Freescale Semiconductor ...

  • Page 173

    ... SPR1 and SPR0 — SPI Baud Rate Select Bits In master mode, these read/write bits select one of four baud rates as shown in SPR0 have no effect in slave mode. Table 15-3. SPI Master Baud Rate Selection SPR1 and SPR0 Use this formula to calculate the SPI baud rate: Freescale Semiconductor NOTE Baud Rate Divisor (BD ...

  • Page 174

    ... R7–R0/T7–T0 — Receive/Transmit Data Bits Do not use read-modify-write instructions on the SPI data register because the register read is not the same as the register written. 174 Figure Unaffected by reset Figure 15-15. SPI Data Register (SPDR) NOTE MC68HC908QB8 Data Sheet, Rev. 3 15- Bit Freescale Semiconductor ...

  • Page 175

    ... The TIM clock source is one of the seven prescaler outputs or the external clock input pin, TCLK if available. The prescaler generates seven clock rates from the internal bus clock. The prescaler select bits, PS[2:0], in the TIM status and control register (TSC) select the clock source. Freescale Semiconductor Figure 16-1 MC68HC908QB8 Data Sheet, Rev. 3 ...

  • Page 176

    ... MC68HC908QB8 Data Sheet, Rev. 3 CLOCK GENERATOR KEYBOARD INTERRUPT MODULE EXTERNAL INTERRUPT MODULE AUTO WAKEUP MODULE LOW-VOLTAGE INHIBIT 4-CHANNEL 16-BIT TIMER MODULE COP MODULE 10-CHANNEL 10-BIT ADC ENHANCED SERIAL COMMUNICATIONS INTERFACE MODULE SERIAL PERIPHERAL INTERFACE DEVELOPMENT SUPPORT MONITOR ROM BREAK MODULE Freescale Semiconductor ...

  • Page 177

    ... TCH3H:TCH3L 16-BIT LATCH 16.3.3 Output Compare With the output compare function, the TIM can generate a periodic pulse with a programmable polarity, duration, and frequency. When the counter reaches the value in the registers of an output compare Freescale Semiconductor PRESCALER SELECT PS2 PS1 PS0 ...

  • Page 178

    ... TIM channel 3 status and control register (TSC3) is unused. While the MS2B bit is set, the channel 3 pin, TCH3, is available as a general-purpose I/O pin. In buffered output compare operation, do not write new output compare values to the currently active channel registers. User software should track 178 NOTE MC68HC908QB8 Data Sheet, Rev. 3 16.3.3 Freescale Semiconductor ...

  • Page 179

    ... Also, using a TIM overflow interrupt routine to write a new, smaller pulse width value may cause the compare to be missed. The TIM may pass the new value before it is written to the timer channel (TCHxH:TCHxL). Freescale Semiconductor 16.8.1 TIM Status and Control OVERFLOW PERIOD ...

  • Page 180

    ... In buffered PWM signal generation, do not write new pulse width values to the currently active channel registers. User software should track the currently active channel to prevent writing a new value to the active channel. Writing to the active channel registers is the same as generating unbuffered PWM signals. 180 NOTE NOTE MC68HC908QB8 Data Sheet, Rev. 3 Freescale Semiconductor ...

  • Page 181

    ... The result duty cycle output. Setting the channel x maximum duty cycle bit (CHxMAX) and setting the TOVx bit generates a 100% duty cycle output. See 16.8.4 TIM Channel Status and Control Freescale Semiconductor NOTE Registers. MC68HC908QB8 Data Sheet, Rev. 3 Functional Description Table 16-2 ...

  • Page 182

    ... If software does the first step on such a bit before the break, the bit cannot change during the break state as long as BCFE is cleared. After the break, doing the second step clears the status bit. 182 MC68HC908QB8 Data Sheet, Rev. 3 sheet. Freescale Semiconductor ...

  • Page 183

    ... This read/write flag is set when the counter reaches the modulo value programmed in the TIM counter modulo registers. Clear TOF by reading the TSC register when TOF is set and then writing TOF. If another TIM overflow occurs before the clearing sequence is complete, then writing 0 to TOF has no Freescale Semiconductor Register.) The minimum TCLK pulse width is specified in 6 ...

  • Page 184

    ... PS1 PS0 TIM Clock Source Internal bus clock ÷ Internal bus clock ÷ Internal bus clock ÷ Internal bus clock ÷ Internal bus clock ÷ Internal bus clock ÷ Internal bus clock ÷ TCLK (if available) MC68HC908QB8 Data Sheet, Rev. 3 Freescale Semiconductor ...

  • Page 185

    ... Bit15 Write: Reset: 1 Figure 16-7. TIM Counter Modulo High Register (TMODH) Bit 7 Read: Bit7 Write: Reset: 1 Figure 16-8. TIM Counter Modulo Low Register (TMODL) Reset the counter before writing to the TIM counter modulo registers. Freescale Semiconductor NOTE Bit 14 Bit 13 Bit 12 Bit ...

  • Page 186

    ... Therefore, an interrupt request cannot be lost due to inadvertent clearing of CHxF. 186 MS0B MS0A ELS0B MS1A ELS1B MS2B MS2A ELS2B MS3A ELS3B MC68HC908QB8 Data Sheet, Rev Bit 0 ELS0A TOV0 CH0MAX Bit 0 ELS1A TOV1 CH1MAX Bit 0 ELS2A TOV2 CH2MAX Bit 0 ELS3A TOV3 CH3MAX Freescale Semiconductor ...

  • Page 187

    ... Freescale Semiconductor Table 16-2. NOTE ELSxA Mode Pin under port control; initial 0 0 output level high Output preset Pin under port control; initial 0 0 output level low 0 1 Capture on rising edge only 1 0 Input capture Capture on falling edge only 1 1 Capture on rising or falling edge ...

  • Page 188

    ... ELSxB and ELSxA work. NOTE NOTE shows, the CHxMAX bit takes effect in the cycle after it is set OVERFLOW OVERFLOW PERIOD OUTPUT OUTPUT OUTPUT COMPARE COMPARE COMPARE Figure 16-13. CHxMAX Latency MC68HC908QB8 Data Sheet, Rev. 3 OVERFLOW OVERFLOW OUTPUT COMPARE Freescale Semiconductor ...

  • Page 189

    ... Bit 7 Read: Bit 15 Write: Reset: Figure 16-14. TIM Channel x Register High (TCHxH) Bit 7 Read: Bit 7 Write: Reset: Figure 16-15. TIM Channel x Register Low (TCHxL) Freescale Semiconductor Bit 14 Bit 13 Bit 12 Bit 11 Indeterminate after reset ...

  • Page 190

    ... Timer Interface Module (TIM) 190 MC68HC908QB8 Data Sheet, Rev. 3 Freescale Semiconductor ...

  • Page 191

    ... BRKA bit in the break status and control register, the CPU starts a break interrupt by: • Loading the instruction register with the SWI instruction • Loading the program counter with $FFFC and $FFFD ($FEFC and $FEFD in monitor mode) Freescale Semiconductor MC68HC908QB8 Data Sheet, Rev. 3 191 ...

  • Page 192

    ... MC68HC908QB8 Data Sheet, Rev. 3 CLOCK GENERATOR KEYBOARD INTERRUPT MODULE SINGLE INTERRUPT MODULE AUTO WAKEUP MODULE LOW-VOLTAGE INHIBIT 4-CHANNEL 16-BIT TIMER MODULE COP MODULE 10-CHANNEL 10-BIT ADC ENHANCED SERIAL COMMUNICATIONS INTERFACE MODULE SERIAL PERIPHERAL INTERFACE DEVELOPMENT SUPPORT MONITOR ROM BREAK MODULE Freescale Semiconductor ...

  • Page 193

    ... A break interrupt stops the timer counter. 17.2.1.3 COP During Break Interrupts The COP is disabled during a break interrupt in monitor mode when the BDCOP bit is set in the break auxiliary register (BRKAR). Freescale Semiconductor ADDRESS BUS[15:8] BREAK ADDRESS REGISTER HIGH 8-BIT COMPARATOR 8-BIT COMPARATOR ...

  • Page 194

    ... Figure 17-4. Break Address Register High (BRKH) Bit 7 Read: Bit 7 Write: Reset: 0 Figure 17-5. Break Address Register Low (BRKL) 194 Bit 14 Bit 13 Bit 12 Bit Bit 6 Bit 5 Bit 4 Bit MC68HC908QB8 Data Sheet, Rev Bit Bit 0 Bit 10 Bit 9 Bit Bit 0 Bit 2 Bit 1 Bit Freescale Semiconductor ...

  • Page 195

    ... Wait mode was not exited by break interrupt 17.2.2.5 Break Flag Control Register The break control register (BFCR) contains a bit that enables software to clear status bits while the MCU break state. Bit 7 Read: BCFE Write: Reset Reserved R Figure 17-8. Break Flag Control Register (BFCR) Freescale Semiconductor ...

  • Page 196

    ... No security feature is absolutely secure. However, Freescale’s strategy is to make reading or copying the FLASH difficult for unauthorized users. 196 ( reset vector is blank ($FFFE and $FFFF contain TST is applied to IRQ TST MC68HC908QB8 Data Sheet, Rev. 3 Figure 17-10, Figure 17-11, Freescale Semiconductor ...

  • Page 197

    ... FROM Table 17-1 RESET VECTOR BLANK? YES FORCED MONITOR MODE DEBUGGING AND FLASH PROGRAMMING (IF FLASH IS ENABLED) Figure 17-9. Simplified Monitor Mode Entry Flowchart Freescale Semiconductor POR RESET YES NO IRQ = V ? TST NO PTA1 = 1, AND NORMAL USER MODE MONITOR MODE HOST SENDS 8 SECURITY BYTES ...

  • Page 198

    ... MC68HC908QB8 Data Sheet, Rev RST (PTA3) OSC1 (PTA5) PTA1 IRQ (PTA2) PTA4 PTA0 Value not critical N.C. RST (PTA3 OSC1 (PTA5) * PTA1 IRQ (PTA2) PTA4 PTA0 Value not critical Freescale Semiconductor V DD 0.1 μ kΩ kΩ 0.1 μF N.C. N.C. ...

  • Page 199

    ... PTA1 and PTA4 pins can be changed. Once out of reset, the MCU waits for the host to send eight security bytes (see security bytes, the MCU sends a break signal (10 consecutive 0s) to the host, indicating that it is ready to receive a command. Freescale Semiconductor μF 1 μ ...

  • Page 200

    ... MHz MHz clock at OSC1. 9.8304 2.4576 Provide external 9600 MHz MHz clock at OSC1. 3.2 MHz Internal clock is X 9600 (Trimmed) active OSC1 — — [13] TST ) then the chip will still be operating in lowered, the BIH and TST is applied to TST Freescale Semiconductor is ...