MC908QB8CDWE Freescale Semiconductor, MC908QB8CDWE Datasheet - Page 127

• Manufacturer Part Number: MC908QB8CDWE
• Description: IC MCU 8BIT 8K FLASH 16-SOIC
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908QB8CDWE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 13
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 16-SOIC (0.300", 7.5mm Width)
• Processor Series: HC08QB
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 14
• Number Of Timers: 4
• Operating Supply Voltage: 3 V to 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, M68CBL05AE, DEMO908QB8, DEMO908QC16
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• For Use With: DEMO908QB8 - BOARD DEMO FOR MC68HC908QB8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

TC — Transmission Complete Bit
SCRF — ESCI Receiver Full Bit
IDLE — Receiver Idle Bit
OR — Receiver Overrun Bit
NF — Receiver Noise Flag Bit
Freescale Semiconductor
This read-only bit is set when the SCTE bit is set, and no data, preamble, or break character is being
transmitted. TC generates an ESCI transmitter interrupt request if the TCIE bit in SCC2 is also set. TC
is cleared automatically when data, preamble, or break is queued and ready to be sent. There may be
up to 1.5 transmitter clocks of latency between queueing data, preamble, and break and the
transmission actually starting.
This clearable, read-only bit is set when the data in the receive shift register transfers to the ESCI data
register. SCRF can generate an ESCI receiver interrupt request. When the SCRIE bit in SCC2 is set
the SCRF generates a interrupt request. In normal operation, clear the SCRF bit by reading SCS1 with
SCRF set and then reading the SCDR.
This clearable, read-only bit is set when 10 or 11 consecutive 1s appear on the receiver input. IDLE
generates an ESCI receiver interrupt request if the ILIE bit in SCC2 is also set. Clear the IDLE bit by
reading SCS1 with IDLE set and then reading the SCDR. After the receiver is enabled, it must receive
a valid character that sets the SCRF bit before an idle condition can set the IDLE bit. Also, after the
IDLE bit has been cleared, a valid character must again set the SCRF bit before an idle condition can
set the IDLE bit.
This clearable, read-only bit is set when software fails to read the SCDR before the receive shift
register receives the next character. The OR bit generates an ESCI error interrupt request if the ORIE
bit in SCC3 is also set. The data in the shift register is lost, but the data already in the SCDR is not
affected. Clear the OR bit by reading SCS1 with OR set and then reading the SCDR.
Software latency may allow an overrun to occur between reads of SCS1 and SCDR in the flag-clearing
sequence.
caused by a delayed flag-clearing sequence. The delayed read of SCDR does not clear the OR bit
because OR was not set when SCS1 was read. Byte 2 caused the overrun and is lost. The next
flag-clearing sequence reads byte 3 in the SCDR instead of byte 2.
In applications that are subject to software latency or in which it is important to know which byte is lost
due to an overrun, the flag-clearing routine can check the OR bit in a second read of SCS1 after
reading the data register.
This clearable, read-only bit is set when the ESCI detects noise on the RxD pin. NF generates an NF
interrupt request if the NEIE bit in SCC3 is also set. Clear the NF bit by reading SCS1 and then reading
the SCDR.
1 = No transmission in progress
0 = Transmission in progress
1 = Received data available in SCDR
0 = Data not available in SCDR
1 = Receiver input idle
0 = Receiver input active (or idle since the IDLE bit was cleared)
1 = Receive shift register full and SCRF = 1
0 = No receiver overrun
1 = Noise detected
0 = No noise detected
Figure 13-13
shows the normal flag-clearing sequence and an example of an overrun
MC68HC908QB8 Data Sheet, Rev. 3
Registers
127