MC908QB8CDWE Freescale Semiconductor, MC908QB8CDWE Datasheet - Page 163

IC MCU 8BIT 8K FLASH 16-SOIC

MC908QB8CDWE

Manufacturer Part Number
MC908QB8CDWE
Description
IC MCU 8BIT 8K FLASH 16-SOIC
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet

Specifications of MC908QB8CDWE

Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Connectivity
SCI, SPI
Peripherals
LVD, POR, PWM
Number Of I /o
13
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
16-SOIC (0.300", 7.5mm Width)
Processor Series
HC08QB
Core
HC08
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
SCI, SPI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
14
Number Of Timers
4
Operating Supply Voltage
3 V to 5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Development Tools By Supplier
FSICEBASE, M68CBL05AE, DEMO908QB8, DEMO908QC16
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit
For Use With
DEMO908QB8 - BOARD DEMO FOR MC68HC908QB8
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
 Details

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC908QB8CDWE
Manufacturer:
FREESCALE/PBF
Quantity:
162
Part Number:
MC908QB8CDWE
Manufacturer:
FREESCALE
Quantity:
20 000
Part Number:
MC908QB8CDWE
Manufacturer:
FREESCALE
Quantity:
18 302
Part Number:
MC908QB8CDWER
Manufacturer:
FREESCALE
Quantity:
20 000
15.3.4 Queuing Transmission Data
The double-buffered transmit data register allows a data byte to be queued and transmitted. For an SPI
configured as a master, a queued data byte is transmitted immediately after the previous transmission
has completed. The SPI transmitter empty flag (SPTE) indicates when the transmit data buffer is ready
to accept new data. Write to the transmit data register only when the SPTE bit is high.
shows the timing associated with doing back-to-back transmissions with the SPI (SPSCK has
CPHA: CPOL = 1:0).
The transmit data buffer allows back-to-back transmissions without the slave precisely timing its writes
between transmissions as in a system with a single data buffer. Also, if no new data is written to the data
buffer, the last value contained in the shift register is the next data word to be transmitted.
For an idle master or idle slave that has no data loaded into its transmit buffer, the SPTE is set again no
more than two bus cycles after the transmit buffer empties into the shift register. This allows the user to
queue up a 16-bit value to send. For an already active slave, the load of the shift register cannot occur
until the transmission is completed. This implies that a back-to-back write to the transmit data register is
not possible. SPTE indicates when the next write can occur.
Freescale Semiconductor
CPHA:CPOL = 1:0
WRITE TO SPDR
4 FIRST INCOMING BYTE TRANSFERS FROM SHIFT
5
1
2
3
6
READ SPSCR
WRITE BYTE 1 TO SPDR, CLEARING SPTE BIT.
BYTE 1 TRANSFERS FROM TRANSMIT DATA
REGISTER TO SHIFT REGISTER, SETTING SPTE BIT.
WRITE BYTE 2 TO SPDR, QUEUEING BYTE 2
AND CLEARING SPTE BIT.
REGISTER TO RECEIVE DATA REGISTER, SETTING
SPRF BIT.
BYTE 2 TRANSFERS FROM TRANSMIT DATA
REGISTER TO SHIFT REGISTER, SETTING SPTE BIT.
READ SPDR
READ SPSCR WITH SPRF BIT SET.
SPSCK
SPRF
SPTE
MOSI
1
Figure 15-8. SPRF/SPTE interrupt Timing
MSB BIT
BYTE 1
MC68HC908QB8 Data Sheet, Rev. 3
2
6
BIT
5
3
BIT
4
BIT
3
BIT
2
BIT
1
10
11 READ SPSCR WITH SPRF BIT SET.
12 READ SPDR, CLEARING SPRF BIT.
7 READ SPDR, CLEARING SPRF BIT.
8
9
LSB MSB BIT
5
4
WRITE BYTE 3 TO SPDR, QUEUEING BYTE
3 AND CLEARING SPTE BIT.
SECOND INCOMING BYTE TRANSFERS FROM SHIFT
REGISTER TO RECEIVE DATA REGISTER, SETTING
SPRF BIT.
BYTE 3 TRANSFERS FROM TRANSMIT DATA
REGISTER TO SHIFT REGISTER, SETTING SPTE BIT.
BYTE 2
6
6
7
BIT
5
8
BIT
4
BIT
3
BIT
2
BIT
1
LSB MSB BIT
10
9
BYTE 3
11
6
Functional Description
12
BIT
5
Figure 15-8
BIT
4
163

Related parts for MC908QB8CDWE