MC908QB8CDWE Freescale Semiconductor, MC908QB8CDWE Datasheet - Page 171

IC MCU 8BIT 8K FLASH 16-SOIC

MC908QB8CDWE

Manufacturer Part Number
MC908QB8CDWE
Description
IC MCU 8BIT 8K FLASH 16-SOIC
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet

Specifications of MC908QB8CDWE

Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Connectivity
SCI, SPI
Peripherals
LVD, POR, PWM
Number Of I /o
13
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
16-SOIC (0.300", 7.5mm Width)
Processor Series
HC08QB
Core
HC08
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
SCI, SPI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
14
Number Of Timers
4
Operating Supply Voltage
3 V to 5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Development Tools By Supplier
FSICEBASE, M68CBL05AE, DEMO908QB8, DEMO908QC16
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit
For Use With
DEMO908QB8 - BOARD DEMO FOR MC68HC908QB8
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
 Details

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15.8.1 SPI Control Register
The SPI control register:
SPRIE — SPI Receiver Interrupt Enable Bit
SPMSTR — SPI Master Bit
CPOL — Clock Polarity Bit
CPHA — Clock Phase Bit
SPWOM — SPI Wired-OR Mode Bit
SPE — SPI Enable
Freescale Semiconductor
This read/write bit enables interrupt requests generated by the SPRF bit. The SPRF bit is set when a
byte transfers from the shift register to the receive data register.
This read/write bit selects master mode operation or slave mode operation.
This read/write bit determines the logic state of the SPSCK pin between transmissions. (See
Figure 15-4
identical CPOL values.
This read/write bit controls the timing relationship between the serial clock and SPI data. (See
Figure 15-4
identical CPHA values. When CPHA = 0, the SS pin of the slave SPI module must be high between
bytes. (See
This read/write bit configures pins SPSCK, MOSI, and MISO so that these pins become open-drain
outputs.
This read/write bit enables the SPI module. Clearing SPE causes a partial reset of the SPI. (See
Resetting the
1 = SPRF interrupt requests enabled
0 = SPRF interrupt requests disabled
1 = Master mode
0 = Slave mode
1 = Wired-OR SPSCK, MOSI, and MISO pins
0 = Normal push-pull SPSCK, MOSI, and MISO pins
1 = SPI module enabled
0 = SPI module disabled
Enables SPI module interrupt requests
Configures the SPI module as master or slave
Selects serial clock polarity and phase
Configures the SPSCK, MOSI, and MISO pins as open-drain outputs
Enables the SPI module
Reset:
Read:
Write:
Figure
and
and
SPI.)
Figure
Figure
SPRIE
Bit 7
15-12.)
R
0
15-6.) To transmit data between SPI modules, the SPI modules must have
15-6.) To transmit data between SPI modules, the SPI modules must have
= Reserved
Figure 15-13. SPI Control Register (SPCR)
R
6
0
MC68HC908QB8 Data Sheet, Rev. 3
SPMSTR
5
1
CPOL
0
4
CPHA
3
1
SPWOM
2
0
SPE
1
0
SPTIE
Bit 0
0
Registers
15.3.5
171

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