MC908QB8CDWE Freescale Semiconductor, MC908QB8CDWE Datasheet - Page 186

IC MCU 8BIT 8K FLASH 16-SOIC

MC908QB8CDWE

Manufacturer Part Number
MC908QB8CDWE
Description
IC MCU 8BIT 8K FLASH 16-SOIC
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet

Specifications of MC908QB8CDWE

Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Connectivity
SCI, SPI
Peripherals
LVD, POR, PWM
Number Of I /o
13
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
16-SOIC (0.300", 7.5mm Width)
Processor Series
HC08QB
Core
HC08
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
SCI, SPI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
14
Number Of Timers
4
Operating Supply Voltage
3 V to 5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Development Tools By Supplier
FSICEBASE, M68CBL05AE, DEMO908QB8, DEMO908QC16
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit
For Use With
DEMO908QB8 - BOARD DEMO FOR MC68HC908QB8
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
 Details

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Timer Interface Module (TIM)
16.8.4 TIM Channel Status and Control Registers
Each of the TIM channel status and control registers does the following:
CHxF — Channel x Flag Bit
186
When channel x is an input capture channel, this read/write bit is set when an active edge occurs on
the channel x pin. When channel x is an output compare channel, CHxF is set when the value in the
counter registers matches the value in the TIM channel x registers.
Clear CHxF by reading the TSCx register with CHxF set and then writing a 0 to CHxF. If another
interrupt request occurs before the clearing sequence is complete, then writing 0 to CHxF has no
effect. Therefore, an interrupt request cannot be lost due to inadvertent clearing of CHxF.
Flags input captures and output compares
Enables input capture and output compare interrupts
Selects input capture, output compare, or PWM operation
Selects high, low, or toggling output on output compare
Selects rising edge, falling edge, or any edge as the active input capture trigger
Selects output toggling on TIM overflow
Selects 0% and 100% PWM duty cycle
Selects buffered or unbuffered output compare/PWM operation
Reset:
Reset:
Reset:
Reset:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Figure 16-10. TIM Channel 1 Status and Control Register (TSC1)
Figure 16-11. TIM Channel 2 Status and Control Register (TSC2)
Figure 16-12. TIM Channel 3 Status and Control Register (TSC3)
Figure 16-9. TIM Channel 0 Status and Control Register (TSC0)
CH0F
CH1F
CH2F
CH3F
Bit 7
Bit 7
Bit 7
Bit 7
0
0
0
0
0
0
0
0
= Unimplemented
CH0IE
CH1IE
CH2IE
CH3IE
6
0
6
0
6
0
6
0
MC68HC908QB8 Data Sheet, Rev. 3
MS0B
MS2B
5
0
5
0
0
5
0
5
0
0
MS0A
MS1A
MS2A
MS3A
0
0
0
0
4
4
4
4
ELS0B
ELS2B
ELS1B
ELS3B
3
0
3
0
3
0
3
0
ELS0A
ELS1A
ELS2A
ELS3A
2
0
2
0
2
0
2
0
TOV0
TOV1
TOV2
TOV3
1
0
1
0
1
0
1
0
CH0MAX
CH1MAX
CH2MAX
CH3MAX
Freescale Semiconductor
Bit 0
Bit 0
Bit 0
Bit 0
0
0
0
0

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