C8051F321-GM Silicon Laboratories Inc, C8051F321-GM Datasheet
C8051F321-GM
Specifications of C8051F321-GM
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C8051F321-GM Summary of contents
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... External oscillator: Crystal, RC Clock pin modes) Can switch between clock sources on-the-fly; - useful in power saving strategies RoHS Compliant Packages - 32-pin LQFP (C8051F320) - 28-pin QFN (C8051F321) Temperature Range: –40 to +85 °C ANALOG DIGITAL I/O PERIPHERALS UART SPI + A 10-bit SMBus ...
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C8051F320/1 2 Rev. 1.4 ...
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Table of Contents 1. System Overview.................................................................................................... 15 1.1. CIP-51™ Microcontroller Core.......................................................................... 18 1.1.1. Fully 8051 Compatible.............................................................................. 18 1.1.2. Improved Throughput ............................................................................... 18 1.1.3. Additional Features .................................................................................. 18 1.2. On-Chip Memory............................................................................................... 19 1.3. Universal Serial Bus Controller ......................................................................... 20 1.4. Voltage ...
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C8051F320/1 9.2.7. Register Descriptions ............................................................................... 83 9.3. Interrupt Handler ............................................................................................... 87 9.3.1. MCU Interrupt Sources and Vectors ........................................................ 87 9.3.2. External Interrupts .................................................................................... 88 9.3.3. Interrupt Priorities ..................................................................................... 88 9.3.4. Interrupt Latency ...................................................................................... 89 9.3.5. Interrupt Register Descriptions................................................................. 90 9.4. ...
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Clock Selection ......................................................................... 123 13.4.2.USB Clock Selection .............................................................................. 123 14. Port Input/Output ................................................................................................ 126 14.1.Priority Crossbar Decoder .............................................................................. 128 14.2.Port I/O Initialization ....................................................................................... 130 14.3.General Purpose Port I/O ............................................................................... 132 15. Universal Serial Bus Controller (USB)................................................................ 139 15.1.Endpoint Addressing ...
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C8051F320/1 16.5.3.Slave Receiver Mode ............................................................................. 182 16.5.4.Slave Transmitter Mode ......................................................................... 183 16.6.SMBus Status Decoding................................................................................. 184 17. UART0.................................................................................................................... 187 17.1.Enhanced Baud Rate Generation................................................................... 188 17.2.Operational Modes ......................................................................................... 188 17.2.1.8-Bit UART ............................................................................................. 189 17.2.2.9-Bit UART ............................................................................................. 190 17.3.Multiprocessor Communications .................................................................... 190 18. ...
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Timer Usage ......................................................................... 238 20.4.Register Descriptions for PCA........................................................................ 239 21. C2 Interface ........................................................................................................... 245 21.1.C2 Interface Registers.................................................................................... 245 21.2.C2 Pin Sharing ............................................................................................... 247 C8051F320/1 Rev. 1.4 7 ...
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... List of Figures and Tables 1. System Overview Table 1.1. Product Selection Guide ........................................................................ 16 Figure 1.1. C8051F320 Block Diagram .................................................................... 16 Figure 1.2. C8051F321 Block Diagram .................................................................... 17 Figure 1.3. On-Chip Clock and Reset ...................................................................... 19 Figure 1.4. On-Board Memory Map.......................................................................... 20 Figure 1.5. USB Controller Block Diagram............................................................... 21 Figure 1.6. Development/In-System Debug Diagram............................................... 22 Figure 1 ...
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Figure 8.1. External Capacitors for Voltage Regulator Input/Output ........................ 67 Table 8.1. Voltage Regulator Electrical Specifications ............................................ 68 Figure 8.2. REG0 Configuration: USB Bus-Powered ............................................... 68 Figure 8.3. REG0 Configuration: USB Self-Powered ............................................... 69 Figure 8.4. REG0 Configuration: USB Self-Powered, ...
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C8051F320/1 Figure 16.2. Typical SMBus Configuration ............................................................. 170 Figure 16.3. SMBus Transaction ............................................................................ 171 Table 16.1. SMBus Clock Source Selection........................................................... 173 Figure 16.4. Typical SMBus SCL Generation......................................................... 174 Table 16.2. Minimum SDA Setup and Hold Times ................................................. 174 Table 16.3. ...
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Figure 19.11. Timer 3 SOF Capture Mode (T3SPLIT = ‘1’).................................... 224 20. Programmable Counter Array (PCA0) Figure 20.1. PCA Block Diagram............................................................................ 227 Table 20.1. PCA Timebase Input Options .............................................................. 228 Figure 20.2. PCA Counter/Timer Block Diagram.................................................... 228 Table 20.2. PCA0CPM ...
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C8051F320/1 List of Registers SFR Definition 5.1. AMX0P: AMUX0 Positive Channel Select . . . . . . . . . . . . . . . . . . 46 SFR Definition 5.2. AMX0N: AMUX0 Negative Channel Select . ...
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SFR Definition 14.1. XBR0: Port I/O Crossbar Register 131 SFR Definition 14.2. XBR1: Port I/O Crossbar Register 1 ...
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C8051F320/1 SFR Definition 16.3. SMB0DAT: SMBus Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 SFR Definition ...
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System Overview C8051F320/1 devices are fully integrated mixed-signal System-on-a-Chip MCUs. Highlighted features are listed below. Refer to Table 1.1 for specific product feature selection. • High-speed pipelined 8051-compatible microcontroller core ( MIPS) • In-system, full-speed, non-intrusive debug ...
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... C8051F320/1 Table 1.1. Product Selection Guide C8051F320- 2304 C8051F321- 2304 5.0V Voltage Enable REGIN IN Regulator OUT Analog/Digital VDD Power GND C2D Debug HW /RST/C2CK Brown- POR Out XTAL1 XTAL2 External Oscillator Circuit 12MHz Internal x4 2 Oscillator 2 USB Clock Clock 1,2,3,4 ...
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... XTAL1 XTAL2 External Oscillator Circuit 12MHz Internal x4 2 Oscillator 2 USB Clock Clock 1,2,3,4 Recovery USB D+ Transceiver Controller D- VBUS 1K byte USB Figure 1.2. C8051F321 Block Diagram Port 0 Latch Port 1 Latch UART Timer 0,1,2,3 / RTC 8 16kbyte FLASH 0 PCA/ WDT 5 256 byte Reset SRAM SMBus 1 ...
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C8051F320/1 1.1. CIP-51™ Microcontroller Core 1.1.1. Fully 8051 Compatible The C8051F320/1 family utilizes Silicon Labs' proprietary CIP-51 microcontroller core. The CIP-51 is fully compatible with the MCS-51™ instruction set; standard 803x/805x assemblers and compilers can be used to develop software. ...
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Px.x Px.x Internal Oscillator Clock System Multiplier Clock External XTAL1 Oscillator Clock Select XTAL2 Drive Figure 1.3. On-Chip Clock and Reset 1.2. On-Chip Memory The CIP-51 has a standard 8051 program and data address configuration. It includes 256 bytes of ...
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C8051F320/1 PROGRAM/DATA MEMORY (Flash) RESERVED 0x3E00 0x3DFF 16 K Flash (In-System Programmable in 512 Byte Sectors) 0x0000 Figure 1.4. On-Board Memory Map 1.3. Universal Serial Bus Controller The Universal Serial Bus Controller (USB0 USB 2.0 compliant Full or ...
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The USB Transceiver is USB 2.0 compliant, and includes on-chip matching and pull-up resistors. The pull- up resistors can be enabled/disabled in software, and will appear on the D+ or D– pin according to the soft- ware-selected speed setting (Full ...
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... Programmable Digital I/O and Crossbar C8051F320 devices include 25 I/O pins (three byte-wide Ports and one 1-bit-wide Port); C8051F321 devices include 21 I/O pins (two byte-wide Ports, one 4-bit-wide Port, and one 1-bit-wide Port). The C8051F320/1 Ports behave like typical 8051 Ports with a few enhancements. Each Port pin may be config- ured as an analog input or a digital I/O pin. Pins selected as digital I/Os may additionally be configured for push-pull or open-drain output. The “ ...
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Highest UART Priority 4 SPI 2 SMBus 2 CP0 Outputs 2 CP1 Outputs SYSCLK 6 PCA 2 Lowest T0, T1 Priority 8 P0 (P0.0-P0. (P1.0-P1. (P2.0-P2. (P3.0) Figure 1.7. Digital Crossbar Diagram 1.7. ...
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C8051F320/1 SYSCLK/12 SYSCLK/4 Timer 0 Overflow ECI SYSCLK External Clock/8 Capture/Compare Capture/Compare Module 0 Figure 1.9. PCA Block Diagram 1.9. 10-Bit Analog to Digital Converter The C8051F320/1 devices include an on-chip 10-bit SAR ADC with a 17-channel differential input multi- ...
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Analog Multiplexer P1.0 P1.7 P2.0 19-to-1 P2.4-2.7 AMUX available on P2.7 C8051F320 P3.0 Temp Sensor VDD P1.0 P1.7 P2.0 19-to-1 AMUX P2.4-2.7 available on P2.7 C8051F320 P3.0 VREF GND Figure 1.10. 10-Bit ADC Block Diagram 1.10. Comparators C8051F320/1 devices include ...
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C8051F320/1 CP0EN CP0OUT CP0RIF CP0FIF CP0HYP1 CMX0N1 CP0HYP0 CMX0N0 CP0HYN1 CP0HYN0 CMX0P1 CMX0P0 P1.0 P1.4 P2.0 P2.4 P1.1 P1.5 P2.1 P2.5 Note: P2.4 and P2.5 available only on C8051F320 Figure 1.11. Comparator0 Block Diagram 26 VDD CP0 + + SET ...
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Absolute Maximum Ratings Table 2.1. Absolute Maximum Ratings Parameter Ambient temperature under bias Storage Temperature Voltage on any Port I/O Pin or /RST with respect to GND Voltage on VDD with respect to GND Maximum Total current through VDD ...
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C8051F320/1 3. Global Electrical Characteristics Table 3.1. Global Electrical Characteristics –40 to +85 °C, 25 MHz system clock unless otherwise noted. Parameter Digital Supply Voltage Digital Supply RAM Data Retention Voltage 3 SYSCLK (System Clock) T (SYSCLK High Time) SYSH ...
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Table 3.1. Global Electrical Characteristics (Continued) –40 to +85 °C, 25 MHz system clock unless otherwise noted. Parameter 4 Idle IDD Supply Sensitivity Idle IDD Frequency 4,6 Sensitivity Digital Supply Current ...
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C8051F320/1 4. Pinout and Package Definitions Table 4.1. Pin Definitions for the C8051F320/1 Pin Numbers Name ‘F320 ‘F321 Power In VDD 6 6 GND 3 3 /RST C2CK P3. C2D REGIN Power Regulator ...
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Table 4.1. Pin Definitions for the C8051F320/1 (Continued) Pin Numbers Name Type ‘F320 ‘F321 D I I I I/O ...
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C8051F320/1 P0 GND VDD 6 7 REGIN 8 VBUS Figure 4.1. LQFP-32 Pinout Diagram (Top View) 32 C8051F320 Top View Rev. 1.4 24 P1.2 23 P1.3 22 P1.4 21 P1.5 20 P1.6 ...
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Figure 4.2. LQFP-32 Package Drawing Table 4.2. LQFP-32 Package Dimensions Dimension Min A — A1 0.05 A2 1.35 b 0.30 c 0.09 D 9.00 BSC. D1 7.00 BSC. e 0.80 BSC. E 9.00 BSC. E1 7.00 BSC. L 0.45 Rev. ...
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C8051F320/1 Table 4.2. LQFP-32 Package Dimensions (Continued) Dimension aaa bbb ccc ddd Q Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1994. 3. This drawing conforms to JEDEC outline MS-026, ...
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Figure 4.3. LQFP-32 Recommended PCB Land Pattern Table 4.3. LQFP-32 PCB Land Pattern Dimensions Dimension Min Max C1 8.40 8.50 C2 8.40 8.50 E 0.80 Notes: General 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. This ...
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... C8051F320/1 P0.1 1 P0.0 2 GND VDD 6 REGIN 7 Figure 4.4. QFN-28 Pinout Diagram (Top View) 36 C8051F321 Top View GND Rev. 1.4 21 P1.1 20 P1.2 19 P1.3 18 P1.4 17 P1.5 16 P1.6 15 P1.7 ...
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Figure 4.5. QFN-28 Package Drawing Table 4.4. QFN-28 Package Dimensions Dimension Min Typ A 0.80 0.90 A1 0.00 0.02 A3 0.25 REF b 0.18 0.23 D 5.00 BSC. D2 2.90 3.15 e 0.50 BSC. E 5.00 BSC. E2 2.90 3.15 ...
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C8051F320/1 Figure 4.6. QFN-28 Recommended PCB Land Pattern Table 4.5. QFN-28 PCB Land Pattern Dimesions Dimension Min C1 4.80 C2 4.80 E 0.50 X1 0.20 Notes: General 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning ...
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ADC (ADC0) The ADC0 subsystem for the C8051F320/1 consists of two analog multiplexers (referred to collectively as AMUX0) with 17 total input selections, and a 200 ksps, 10-bit successive-approximation-register ADC with integrated track-and-hold and programmable window detector. The ...
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C8051F320/1 5.1. Analog Multiplexer AMUX0 selects the positive and negative inputs to the ADC. Any of the following may be selected as the positive input: P1.0-P3.0, the on-chip temperature sensor, or the positive power supply (V following may be selected ...
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Temperature Sensor The temperature sensor transfer function is shown in Figure 5.2. The output voltage (V ADC input when the temperature sensor is selected by bits AMX0P4-0 in register AMX0P. Values for the Offset and Slope parameters can be ...
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C8051F320/1 5.0 0 4.0 0 3.0 0 2.0 0 1.0 0 0.0 0 -40.00 -20.00 -1.00 -2.00 -3.00 -4.00 -5.00 Figure 5.3. Temperature Sensor Error with 1-Point Calibration (VREF = 2. 40.0 0.0 20 Temperature ...
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Modes of Operation ADC0 has a maximum conversion speed of 200 ksps. The ADC0 conversion clock is a divided version of the system clock, determined by the AD0SC bits in the ADC0CF register (system clock divided by (AD0SC + ...
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C8051F320/1 5.3.2. Tracking Modes The AD0TM bit in register ADC0CN controls the ADC0 track-and-hold mode. In its default state, the ADC0 input is continuously tracked, except when a conversion is in progress. When the AD0TM bit is logic 1, ADC0 ...
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Settling Time Requirements When the ADC0 input configuration is changed (i.e., a different AMUX0 selection is made), a minimum tracking time is required before an accurate conversion can be performed. This tracking time is determined by the AMUX0 resistance, ...
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... Only applies to C8051F320; selection RESERVED on C8051F321 devices. 46 AMX0P: AMUX0 Positive Channel Select R/W R/W R/W AMX0P4 AMX0P3 AMX0P2 AMX0P1 Bit4 Bit3 Bit2 ADC0 Positive Input P1.0 P1 ...
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... GND (ADC in Single-Ended Mode) *Note: Only applies to C8051F320; selection RESERVED on C8051F321 devices. AMX0N: AMUX0 Negative Channel Select R/W R/W R/W R/W Bit4 Bit3 Bit2 Bit1 ADC0 Negative Input P1.0 P1.1 P1 ...
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C8051F320/1 SFR Definition 5.3. R/W R/W R/W AD0SC4 AD0SC3 AD0SC2 Bit7 Bit6 Bit5 Bits7–3: AD0SC4–0: ADC0 SAR Conversion Clock Period Bits. SAR Conversion clock is derived from system clock by the following equation, where AD0SC refers to the 5-bit value ...
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SFR Definition 5.6. R/W R/W R/W AD0EN AD0TM AD0INT AD0BUSY AD0WINT AD0CM2 AD0CM1 AD0CM0 00000000 Bit7 Bit6 Bit5 Bit7: AD0EN: ADC0 Enable Bit. 0: ADC0 Disabled. ADC0 is in low-power shutdown. 1: ADC0 Enabled. ADC0 is active and ready for ...
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C8051F320/1 5.4. Programmable Window Detector The ADC Programmable Window Detector continuously compares the ADC0 conversion results to user- programmed limits, and notifies the system when a desired condition is detected. This is especially effec- tive in an interrupt-driven system, saving ...
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SFR Definition 5.9. ADC0LTH: ADC0 Less-Than Data High Byte R/W R/W R/W Bit7 Bit6 Bit5 Bits7–0: High byte of ADC0 Less-Than Data Word. SFR Definition 5.10. R/W R/W R/W Bit7 Bit6 Bit5 Bits7–0: Low byte of ADC0 Less-Than Data Word. ...
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C8051F320/1 5.4.1. Window Detector In Single-Ended Mode Figure 5.6 shows two example window comparisons for right-justified, single-ended data, with ADC0LTH:ADC0LTL = 0x0080 (128d) and ADC0GTH:ADC0GTL = 0x0040 (64d). In single-ended mode, the input voltage can range from ‘0’ to VREF ...
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Window Detector In Differential Mode Figure 5.8 shows two example window comparisons for right-justified, differential data, with ADC0LTH:ADC0LTL = 0x0040 (+64d) and ADC0GTH:ADC0GTH = 0xFFFF (-1d). In differential mode, the measurable voltage between the input pins is between -VREF ...
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C8051F320/1 Table 5.1. ADC0 Electrical Characteristics V = 3.0 V, VREF = 2.40 V, –40 to +85 °C unless otherwise specified. DD Parameter DC Accuracy Resolution Integral Nonlinearity Differential Nonlinearity Offset Error Full Scale Error Offset Temperature Coefficient Dynamic Performance ...
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Voltage Reference The Voltage reference MUX on C8051F320/1 devices is configurable to use an externally connected volt- age reference, the internal reference voltage generator, or the power supply voltage VDD (see Figure 6.1). The REFSL bit in the Reference ...
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C8051F320/1 SFR Definition 6.1. R/W R/W R Bit7 Bit6 Bit5 Bits7–3: UNUSED. Read = 00000b; Write = don’t care. Bit3: REFSL: Voltage Reference Select. This bit selects the source for the internal voltage reference. 0: VREF pin ...
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Comparators C8051F320/1 devices include two on-chip programmable voltage Comparators: Comparator0 is shown in Figure 7.1; Comparator1 is shown in Figure 7.2. The two Comparators operate identically with the follow- ing exceptions: (1) Their input selections differ as shown in ...
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C8051F320/1 Comparator outputs can be polled in software, used as an interrupt source, and/or routed to a Port pin. When routed to a Port pin, Comparator outputs are available asynchronous or synchronous to the system clock; the asynchronous output is ...
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CP0+ VIN+ + CP0 CP0- _ VIN- CIRCUIT CONFIGURATION Positive Hysteresis Voltage (Programmed with CP0HYP Bits) VIN- INPUTS VIN OUTPUT V OL Positive Hysteresis Disabled Figure 7.3. Comparator Hysteresis Plot Comparator hysteresis is programmed using Bits3–0 in the ...
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C8051F320/1 SFR Definition 7.1. CPT0CN: Comparator0 Control R/W R R/W CP0EN CP0OUT CP0RIF Bit7 Bit6 Bit5 Bit7: CP0EN: Comparator0 Enable Bit. 0: Comparator0 Disabled. 1: Comparator0 Enabled. Bit6: CP0OUT: Comparator0 Output State Flag. 0: Voltage on CP0+ < CP0–. 1: ...
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... Bits1–0: CMX0P1–CMX0P0: Comparator0 Positive Input MUX Select. These bits select which Port pin is used as the Comparator0 positive input. CMX0P1 CMX0P0 Positive Input *Note: P2.4 and P2.5 available only on C8051F320 devices; selection reserved on C8051F321 devices. R/W R/W R/W R CMX0P1 CMX0P0 00000000 Bit4 Bit3 Bit2 Bit1 P1.1 P1.5 P2 ...
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C8051F320/1 SFR Definition 7.3. CPT0MD: Comparator0 Mode Selection R/W R/W R CP0RIE Bit7 Bit6 Bit5 Bits7–6: UNUSED. Read = 00b. Write = don’t care. Bit5: CP0RIE: Comparator0 Rising-Edge Interrupt Enable. 0: Comparator0 rising-edge interrupt disabled. 1: Comparator0 rising-edge ...
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SFR Definition 7.4. CPT1CN: Comparator1 Control R/W R R/W CP1EN CP1OUT CP1RIF Bit7 Bit6 Bit5 Bit7: CP1EN: Comparator1 Enable Bit. 0: Comparator1 Disabled. 1: Comparator1 Enabled. Bit6: CP1OUT: Comparator1 Output State Flag. 0: Voltage on CP1+ < CP1–. 1: Voltage ...
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... Bits1–0: CMX1P1–CMX1P0: Comparator1 Positive Input MUX Select. These bits select which Port pin is used as the Comparator1 positive input. CMX1P1 CMX1P0 *Note: P2.6 and P2.7 available only on C8051F320 devices; selection reserved on C8051F321 devices. 64 R/W R/W R CMX1P1 CMX1P0 00000000 Bit4 Bit3 Bit2 P1.3 P1.7 P2 ...
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SFR Definition 7.6. CPT1MD: Comparator1 Mode Selection R/W R/W R CP1RIE CP1FIE Bit7 Bit6 Bit5 Bits7–6: UNUSED. Read = 00b, Write = don’t care. Bit5: CP1RIE: Comparator1 Rising-Edge Interrupt Enable. 0: Comparator1 rising-edge interrupt disabled. 1: Comparator1 rising-edge ...
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C8051F320/1 Table 7.1. Comparator Electrical Characteristics V = 3.0 V, –40 to +85 °C unless otherwise noted. All specifications apply to both Comparator0 and Comparator1 DD unless otherwise noted. Parameter Response Time: Mode 0, Vcm* = 1.5 V Response Time: ...
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Voltage Regulator (REG0) C8051F320/1 devices include a 5-to-3 V voltage regulator (REG0). When enabled, the REG0 output appears on the VDD pin and can be used to power external devices. REG0 can be enabled/disabled by software using bit REGEN ...
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C8051F320/1 Important Note: When USB is selected as a reset source, a system reset will be generated when the VBUS signal matches the polarity selected by the VBPOL bit. See Section “10. Reset Sources” on page 99 for details on ...
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VBUS From VBUS From 5V REGIN Power Net To 3V VDD Power Net Figure 8.3. REG0 Configuration: USB Self-Powered VBUS From VBUS REGIN From 3V VDD Power Net Figure 8.4. REG0 Configuration: USB Self-Powered, Regulator Disabled C8051F320/1 C8051F320/1 VBUS Sense ...
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C8051F320/1 VBUS From 5V REGIN Power Net To 3V Power Net Figure 8.5. REG0 Configuration: No USB Connection SFR Definition 8.1. REG0CN: Voltage Regulator Control R/W R R/W REGDIS VBSTAT VBPOL Bit7 Bit6 Bit5 Bit7: REGDIS: Voltage Regulator Disable. 0: ...
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CIP-51 Microcontroller The MCU system controller core is the CIP-51 microcontroller. The CIP-51 is fully compatible with the MCS-51™ instruction set; standard 803x/805x assemblers and compilers can be used to develop soft- ware. The MCU family has a superset ...
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C8051F320/1 Performance The CIP-51 employs a pipelined architecture that greatly increases its instruction throughput over the stan- dard 8051 architecture standard 8051, all instructions except for MUL and DIV take system clock cycles to execute, ...
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MOVX Instruction and Program Memory The MOVX instruction is typically used to access external data memory (Note: the C8051F320/1 does not support off-chip data or program memory). In the CIP-51, the MOVX write instruction is used to accesses external ...
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C8051F320/1 Table 9.1. CIP-51 Instruction Set Summary (Continued) Mnemonic Description ORL direct direct byte ORL direct, #data OR immediate to direct byte XRL A, Rn Exclusive-OR Register to A XRL A, direct Exclusive-OR direct byte to ...
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Table 9.1. CIP-51 Instruction Set Summary (Continued) Mnemonic Description CLR C Clear Carry CLR bit Clear direct bit SETB C Set Carry SETB bit Set direct bit CPL C Complement Carry CPL bit Complement direct bit ANL C, bit AND ...
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C8051F320/1 Notes on Registers, Operands and Addressing Modes Register R0-R7 of the currently selected register bank. @Ri - Data RAM location addressed indirectly through R0 or R1. rel - 8-bit, signed (two’s complement) offset relative to the first ...
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Memory Organization The memory organization of the CIP-51 System Controller is similar to that of a standard 8051. There are two separate memory spaces: program memory and data memory. Program and data memory share the same address space but ...
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C8051F320/1 9.2.2. Data Memory The CIP-51 includes 256 of internal RAM mapped into the data memory space from 0x00 through 0xFF. The lower 128 bytes of data memory are used for general purpose registers and scratch pad memory. Either direct ...
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Special Function Registers The direct-access data memory locations from 0x80 to 0xFF constitute the special function registers (SFRs). The SFRs provide control and data exchange with the CIP-51's resources and peripherals. The CIP-51 duplicates the SFRs found in a ...
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C8051F320/1 Table 9.3. Special Function Registers SFRs are listed in alphabetical order. All undefined SFR locations are reserved. Register Address ACC 0xE0 Accumulator ADC0CF 0xBC ADC0 Configuration ADC0CN 0xE8 ADC0 Control ADC0GTH 0xC4 ADC0 Greater-Than Compare High ADC0GTL 0xC3 ADC0 ...
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Table 9.3. Special Function Registers (Continued) SFRs are listed in alphabetical order. All undefined SFR locations are reserved. Register Address IT01CF 0xE4 INT0/INT1 Configuration OSCICL 0xB3 Internal Oscillator Calibration OSCICN 0xB2 Internal Oscillator Control OSCXCN 0xB1 External Oscillator Control P0 ...
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C8051F320/1 Table 9.3. Special Function Registers (Continued) SFRs are listed in alphabetical order. All undefined SFR locations are reserved. Register Address PCA0CPM2 0xDC PCA Module 2 Mode Register PCA0CPM3 0xDD PCA Module 3 Mode Register PCA0CPM4 0xDE PCA Module 4 ...
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Table 9.3. Special Function Registers (Continued) SFRs are listed in alphabetical order. All undefined SFR locations are reserved. Register Address TMR2RLL 0xCA Timer/Counter 2 Reload Low TMR3CN 0x91 Timer/Counter 3Control TMR3H 0x95 Timer/Counter 3 High TMR3L 0x94 Timer/Counter 3Low TMR3RLH ...
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C8051F320/1 SFR Definition 9.2. R/W R/W R/W Bit7 Bit6 Bit5 Bits7–0: DPH: Data Pointer High. The DPH register is the high byte of the 16-bit DPTR. DPTR is used to access indirectly addressed memory. SFR Definition 9.3. R/W R/W R/W ...
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SFR Definition 9.4. R/W R/W R Bit7 Bit6 Bit5 Bit7: CY: Carry Flag. This bit is set when the last arithmetic operation resulted in a carry (addition borrow (subtraction cleared to logic 0 ...
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C8051F320/1 SFR Definition 9.5. R/W R/W R/W ACC.7 ACC.6 ACC.5 Bit7 Bit6 Bit5 Bits7–0: ACC: Accumulator. This register is the accumulator for arithmetic operations. SFR Definition 9.6. R/W R/W R/W B.7 B.6 B.5 Bit7 Bit6 Bit5 Bits7– Register. ...
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Interrupt Handler The CIP-51 includes an extended interrupt system supporting a total of 16 interrupt sources with two prior- ity levels. The allocation of interrupt sources between on-chip peripherals and external inputs pins varies according to the specific version ...
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C8051F320/1 9.3.2. External Interrupts The /INT0 and /INT1 external interrupt sources are configurable as active high or low, edge or level sensi- tive. The IN0PL (/INT0 Polarity) and IN1PL (/INT1 Polarity) bits in the IT01CF register select active high or ...
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Interrupt Latency Interrupt response time depends on the state of the CPU when the interrupt occurs. Pending interrupts are sampled and priority decoded each system clock cycle. Therefore, the fastest possible response time is 5 system clock cycles: 1 ...
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C8051F320/1 Table 9.4. Interrupt Summary (Continued) Interrupt Interrupt Source Vector ADC0 Conversion 0x0053 Complete Programmable 0x005B Counter Array Comparator0 0x0063 Comparator1 0x006B Timer 3 Overflow 0x0073 VBUS Level 0x007B 9.3.5. Interrupt Register Descriptions The SFRs used to enable the interrupt ...
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SFR Definition 9.7. R/W R/W R/W EA ESPI0 ET2 Bit7 Bit6 Bit5 Bit7: EA: Enable All Interrupts. This bit globally enables/disables all interrupts. It overrides the individual interrupt mask set- tings. 0: Disable all interrupt sources. 1: Enable each interrupt ...
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C8051F320/1 SFR Definition 9.8. R/W R/W R/W - PSPI0 PT2 Bit7 Bit6 Bit5 Bit7: UNUSED. Read = 1b, Write = don't care. Bit6: PSPI0: Serial Peripheral Interface (SPI0) Interrupt Priority Control. This bit sets the priority of the SPI0 interrupt. ...
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SFR Definition 9.9. R/W R/W R/W ET3 ECP1 ECP0 Bit7 Bit6 Bit5 Bit7: ET3: Enable Timer 3 Interrupt. This bit sets the masking of the Timer 3 interrupt. 0: Disable Timer 3 interrupts. 1: Enable interrupt requests generated by the ...
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C8051F320/1 SFR Definition 9.10. R/W R/W R/W PT3 PCP1 PCP0 Bit7 Bit6 Bit5 Bit7: PT3: Timer 3 Interrupt Priority Control. This bit sets the priority of the Timer 3 interrupt. 0: Timer 3 interrupts set to low priority level. 1: ...
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SFR Definition 9.11. R/W R/W R Bit7 Bit6 Bit5 Bits7–1: UNUSED. Read = 0000000b. Write = don’t care. Bit0: EVBUS: Enable VBUS Level Interrupt. This bit sets the masking of the VBUS interrupt. 0: Disable all VBUS ...
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C8051F320/1 SFR Definition 9.13. R/W R/W R/W IN1PL IN1SL2 IN1SL1 Bit7 Bit6 Bit5 Note: Refer to Figure 19.1 for INT0/1 edge- or level-sensitive interrupt selection. Bit7: IN1PL: /INT1 Polarity 0: /INT1 input is active low. 1: /INT1 input is active ...
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Power Management Modes The CIP-51 core has two software programmable power management modes: Idle and Stop. Idle mode halts the CPU while leaving the peripherals and clocks active. In Stop mode, the CPU is halted, all inter- rupts, are ...
Page 98
C8051F320/1 SFR Definition 9.14. R/W R/W R/W GF5 GF4 GF3 Bit7 Bit6 Bit5 Bits7–2: GF5–GF0: General Purpose Flags 5–0. These are general purpose flags for use under software control. Bit1: STOP: Stop Mode Select. Setting this bit will place the ...
Page 99
Reset Sources Reset circuitry allows the controller to be easily placed in a predefined default condition. On entry to this reset state, the following occur: • CIP-51 halts program execution • Special Function Registers (SFRs) are initialized to their ...
Page 100
C8051F320/1 10.1. Power-On Reset During power-up, the device is held in a reset state and the /RST pin is driven low until VDD settles above Power-On Reset delay (T RST PORDelay typically less than 0.3 ms. Figure ...
Page 101
Power-Fail Reset / VDD Monitor When a power-down transition or power irregularity causes VDD to drop below V monitor will drive the /RST pin low and hold the CIP- reset state (see Figure 10.2). When VDD returns ...
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C8051F320/1 10.3. External Reset The external /RST pin provides a means for external circuitry to force the device into a reset state. Assert- ing an active-low signal on the /RST pin generates a reset; an external pull-up and/or decoupling of ...
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Software Reset Software may force a reset by writing a ‘1’ to the SWRSF bit (RSTSRC.4). The SWRSF bit will read ‘1’ fol- lowing a software forced reset. The state of the /RST pin is unaffected by this reset. ...
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C8051F320/1 SFR Definition 10.2. R/W R R/W USBRSF FERROR C0RSEF Bit7 Bit6 Bit5 Bit7: USBRSF: USB Reset Flag 0: Read: Last reset was not a USB reset; Write: USB resets disabled. 1: Read: Last reset was a USB reset; Write: ...
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Table 10.1. Reset Electrical Characteristics -40°C to +85°C unless otherwise specified. Parameter I /RST Output Low Voltage OL /RST Input High Voltage /RST Input Low Voltage /RST Input Pull-Up Current /RST = 0.0 V VDD POR Threshold (V ) RST ...
Page 106
C8051F320/1 11. Flash Memory On-chip, re-programmable Flash memory is included for program code and non-volatile data storage. The Flash memory can be programmed in-system, a single byte at a time, through the C2 interface or by soft- ware using the ...
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Flash Write Procedure Flash bytes are programmed by software with the following sequence: Step 1. Disable interrupts (recommended). Step 2. Erase the 512-byte Flash page containing the target location, as described in Section 11.1.2. Step 3. Write the first ...
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C8051F320/1 11.3. Security Options The CIP-51 provides security options to protect the Flash memory from inadvertent modification by soft- ware as well as to prevent the viewing of proprietary program code and constants. The Program Store Write Enable (bit PSWE ...
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The level of Flash security depends on the Flash access method. The three Flash access methods that can be restricted are reads, writes, and erases from the C2 debug interface, user firmware executing on unlocked pages, and user firmware executing ...
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C8051F320/1 11.4. Flash Write and Erase Guidelines Any system which contains routines which write or erase Flash memory from software involves some risk that the write or erase routines will execute unintentionally if the CPU is operating outside its specified ...
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PSWE Maintenance 7. Reduce the number of places in code where the PSWE bit (b0 in PSCTL) is set to a '1'. There should be exactly one routine in code that sets PSWE to a '1' to write ...
Page 112
C8051F320/1 SFR Definition 11.1. R/W R/W R Bit7 Bit6 Bit5 Bits7–3: Unused: Read = 00000b. Write = don’t care. Bit2: Reserved. Read = 0b. Must Write = 0b. Bit1: PSEE: Program Store Erase Enable Setting this bit ...
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SFR Definition 11.3. R/W R/W R/W FOSE Reserved Reserved Reserved Reserved Reserved Reserved Reserved 10000000 Bit7 Bit6 Bit5 Bits7: FOSE: Flash One-shot Enable This bit enables the Flash read one-shot. When the Flash one-shot disabled, the Flash sense amps are ...
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C8051F320/1 12. External RAM The C8051F320/1 devices include 2048 bytes of on-chip XRAM. This XRAM space is split into user RAM (addresses 0x0000 - 0x03FF) and USB0 FIFO space (addresses 0x0400 - 0x07FF). 0xFFFF Same 2048 bytes as from 0x0000 ...
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User XRAM Space User XRAM (1024 bytes) (System Clock Domain) 0x0000 Figure 12.2. XRAM Memory Map Expanded View SFR Definition 12.1. R/W R/W R Bit7 Bit6 Bit5 Bits7–3: Unused: Read = 00000b. Write = don’t care. ...
Page 116
C8051F320/1 13. Oscillators C8051F320/1 devices include a programmable internal oscillator, an external oscillator drive circuit, and a 4x Clock Multiplier. The internal oscillator can be enabled/disabled and calibrated using the OSCICN and OSCICL registers, as shown in Figure 13.1. The ...
Page 117
Equation 13.1. Typical Change in Internal Oscillator Period with OSCICL T 0.0025 On C8051F320/1 devices, OSCICL is factory calibrated to obtain a 12 MHz base frequency (f tion 13.1.1 details oscillator programming for C8051F320/1 devices. Electrical specifications for the preci- ...
Page 118
C8051F320/1 Important Note: If the sum of the reset value of OSCICL and OSCICL is greater than 31 or less than 0, then the device will not be capable of producing the desired frequency. 13.1.2. Internal Oscillator Suspend Mode The ...
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External Oscillator Drive Circuit The external oscillator circuit may drive an external crystal, ceramic resonator, capacitor network. A CMOS clock may also provide a clock input. For a crystal or ceramic resonator configuration, the crys- tal/resonator must ...
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C8051F320/1 13.2.3. External RC Example network is used as an external oscillator source for the MCU, the circuit should be configured as shown in Figure 13.1, Option 2. The capacitor should be no greater than 100 pF; ...
Page 121
SFR Definition 13.3. OSCXCN: External Oscillator Control R R/W R/W XTLVLD XOSCMD2 XOSCMD1 XOSCMD0 Bit7 Bit6 Bit5 Bit7: XTLVLD: Crystal Oscillator Valid Flag. (Read only when XOSCMD = 11x.) 0: Crystal Oscillator is unused or not yet stable. 1: Crystal ...
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C8051F320/1 13.3. 4x Clock Multiplier The 4x Clock Multiplier allows a 12 MHz oscillator to generate the 48 MHz clock required for Full Speed USB communication (see Section “15.4. USB Clock Configuration” on page 146). A divided version of the ...
Page 123
System and USB Clock Selection The internal oscillator requires little start-up time and may be selected as the system or USB clock immedi- ately following the OSCICN write that enables the internal oscillator. External crystals and ceramic resona- tors ...
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C8051F320/1 Table 13.2. Typical USB Low Speed Clock Settings Clock Signal USB Clock Internal Oscillator Clock Signal USB Clock External Oscillator SFR Definition 13.5. CLKSEL: Clock Select R/W R/W R/W - USBCLK Bit7 Bit6 Bit5 Bit 7: Unused. Read = ...
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Table 13.3. Internal Oscillator Electrical Characteristics –40 to +85 °C unless otherwise specified. Parameter Internal Oscillator Frequency Internal Oscillator Supply Current (from VDD) USB Clock Frequency* *Note: Applies only to external oscillator sources. Conditions Min Reset Frequency 11.82 OSCICN.7 = ...
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... C8051F320/1 14. Port Input/Output Digital and analog resources are available through 25 I/O pins (C8051F320 I/O pins (C8051F321). Port pins are organized as shown in Figure 14.1. Each of the Port pins can be defined as general-purpose I/O (GPIO) or analog input; Port pins P0.0-P2.3 can be assigned to one of the internal digital resources as shown in Figure 14 ...
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PUSH-PULL /PORT-OUTENABLE PORT-OUTPUT Analog Select ANALOG INPUT PORT-INPUT Figure 14.2. Port I/O Cell Block Diagram Rev. 1.4 C8051F320/1 VDD VDD (WEAK) PORT PAD GND 127 ...
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C8051F320/1 14.1. Priority Crossbar Decoder The Priority Crossbar Decoder (Figure 14.3) assigns a priority to each I/O function, starting at the top with UART0. When a digital resource is selected, the least-significant unassigned Port pin is assigned to that resource ...
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P0 SF Signals PIN I TX0 RX0 SCK MISO MOSI NSS* SDA SCL CP0 CP0A CP1 CP1A SYSCLK CEX0 CEX1 CEX2 CEX3 CEX4 ECI P0SKIP[0:7] Port ...
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C8051F320/1 14.2. Port I/O Initialization Port I/O initialization consists of the following steps: Step 1. Select the input mode (analog or digital) for all Port pins, using the Port Input Mode register (PnMDIN). Step 2. Select the output mode (open-drain ...
Page 131
SFR Definition 14.1. XBR0: Port I/O Crossbar Register 0 R/W R/W R/W CP1AE CP1E CP0AE Bit7 Bit6 Bit5 Bit7: CP1AE: Comparator1 Asynchronous Output Enable 0: Asynchronous CP1 unavailable at Port pin. 1: Asynchronous CP1 routed to Port pin. Bit6: CP1E: ...
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C8051F320/1 SFR Definition 14.2. XBR1: Port I/O Crossbar Register 1 R/W R/W R/W WEAKPUD XBARE T1E Bit7 Bit6 Bit5 Bit7: WEAKPUD: Port I/O Weak Pull-up Disable. 0: Weak Pull-ups enabled (except for Ports whose I/O are configured as analog input ...
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SFR Definition 14.3. P0: Port0 Register R/W R/W R/W P0.7 P0.6 P0.5 Bit7 Bit6 Bit5 Bits7–0: P0.[7:0] Write - Output appears on I/O pins per Crossbar Registers (when XBARE = ‘1’). 0: Logic Low Output. 1: Logic High Output (high ...
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C8051F320/1 SFR Definition 14.6. P0SKIP: Port0 Skip Register R/W R/W R/W Bit7 Bit6 Bit5 Bits7–0: P0SKIP[7:0]: Port0 Crossbar Skip Enable Bits. These bits select Port pins to be skipped by the Crossbar Decoder. Port pins used as ana- log inputs ...
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SFR Definition 14.9. P1MDOUT: Port1 Output Mode Register R/W R/W R/W Bit7 Bit6 Bit5 Bits7–0: Output Configuration Bits for P1.7-P1.0 (respectively): ignored if corresponding bit in regis- ter P1MDIN is logic 0. 0: Corresponding P1.n Output is open-drain. 1: Corresponding ...
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C8051F320/1 SFR Definition 14.12. P2MDIN: Port2 Input Mode Register R/W R/W R/W Bit7 Bit6 Bit5 Bits7–0: Analog Input Configuration Bits for P2.7–P2.0 (respectively). Port pins configured as analog inputs have their weak pull-up, digital driver, and digital receiver disabled. 0: ...
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SFR Definition 14.15. P3: Port3 Register R/W R/W R/W P3.7 P3.6 P3.5 Bit7 Bit6 Bit5 Bits7–0: P3.[7:0] Write - Output appears on I/O pins. 0: Logic Low Output. 1: Logic High Output (high impedance if corresponding P3MDOUT.n bit = 0). ...
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C8051F320/1 Table 14.1. Port I/O DC Electrical Characteristics V = 2.7 to 3.6V, –40 to +85 °C unless otherwise specified. DD Parameters I = –3 mA, Port I/O push-pull Output High Voltage –10 µA, Port I/O push-pull ...
Page 139
Universal Serial Bus Controller (USB) C8051F320/1 devices include a complete Full/Low Speed USB function for USB peripheral implementa- tions*. The USB Function Controller (USB0) consists of a Serial Interface Engine (SIE), USB Transceiver (including matching resistors and configurable pull-up ...
Page 140
C8051F320/1 15.1. Endpoint Addressing A total of eight endpoint pipes are available. The control endpoint (Endpoint0) always functions as a bi-directional IN/OUT endpoint. The other endpoints are implemented as three pairs of IN/OUT endpoint pipes: Table 15.1. Endpoint Addressing Scheme ...
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SFR Definition 15.1. USB0XCN: USB0 Transceiver Control R/W R/W R/W PREN PHYEN SPEED PHYTST1 PHYTST0 DFREC Bit7 Bit6 Bit5 Bit7: PREN: Internal Pull-up Resistor Enable The location of the pull-up resistor (D+ or D–) is determined by the SPEED bit. ...
Page 142
C8051F320/1 15.3. USB Register Access The USB0 controller registers listed in Table 15.2 are accessed through two SFRs: USB0 Address (USB0ADR) and USB0 Data (USB0DAT). The USB0ADR register selects which USB register is targeted by reads/writes of the USB0DAT register. ...
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SFR Definition 15.2. USB0ADR: USB0 Indirect Address R/W R/W R/W BUSY AUTORD Bit7 Bit6 Bit5 Bits7: BUSY: USB0 Register Read Busy Flag This bit is used during indirect USB0 register accesses. Software should write ‘1’ to this bit to initiate ...
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C8051F320/1 SFR Definition 15.3. USB0DAT: USB0 Data R/W R/W R/W Bit7 Bit6 Bit5 This SFR is used to indirectly read and write USB0 registers. Write Procedure: 1. Poll for BUSY (USB0ADR.7) => ‘0’. 2. Load the target USB0 register address ...
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Table 15.2. USB0 Controller Registers (Continued) USB Register USB Register Name Address E0CSR 0x11 EINCSRL EINCSRH 0x12 EOUTCSRL 0x14 EOUTCSRH 0x15 E0CNT 0x16 EOUTCNTL EOUTCNTH 0x17 USB Register Definition 15.4. INDEX: USB0 Endpoint Index ...
Page 146
C8051F320/1 15.4. USB Clock Configuration USB0 is capable of communication as a Full or Low Speed USB function. Communication speed is selected via the SPEED bit in SFR USB0XCN. When operating as a Low Speed function, the USB0 clock must ...
Page 147
FIFO Management 1024 bytes of on-chip XRAM are used as FIFO space for USB0. This FIFO space is split between Endpoints0-3 as shown in Figure 15.3. FIFO space allocated for Endpoints1-3 is configurable as IN, OUT, or both (Split ...
Page 148
C8051F320/1 15.5.2. FIFO Double Buffering FIFO slots for Endpoints1-3 can be configured for double-buffered mode. In this mode, the maximum packet size is halved and the FIFO may contain two packets at a time. This mode is available for Endpoints1-3. ...
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Function Addressing The FADDR register holds the current USB0 function address. Software should write the host-assigned 7-bit function address to the FADDR register when received as part of a SET_ADDRESS command. A new address written to FADDR will not ...
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C8051F320/1 disabling appropriate peripherals and/or configuring clock sources for low power modes. See Section “13. Oscillators” on page 116 for more details on internal oscillator configuration, including the Suspend mode feature of the internal oscillator. USB0 exits Suspend mode when ...
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USB Register Definition 15.8. POWER: USB0 Power R/W R/W R/W ISOUD - - USBINH Bit7 Bit6 Bit5 Bit7: ISOUD: ISO Update This bit affects all IN Isochronous endpoints. 0: When software writes INPRDY = ‘1’, USB0 will send the packet ...
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C8051F320/1 USB Register Definition 15.9. FRAMEL: USB0 Frame Number Low Bit7 Bit6 Bit5 Bits7-0: Frame Number Low This register contains bits7-0 of the last received frame number. USB Register Definition 15.10. FRAMEH: USB0 Frame Number High R ...
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USB Register Definition 15.11. IN1INT: USB0 IN Endpoint Interrupt Bit7 Bit6 Bit5 Bits7–4: Unused. Read = 0000b. Write = don’t care. Bit3: IN3: IN Endpoint 3 Interrupt-pending Flag This bit is cleared when software ...
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C8051F320/1 USB Register Definition 15.12. OUT1INT: USB0 Out Endpoint Interrupt Bit7 Bit6 Bit5 Bits7–4: Unused. Read = 0000b. Write = don’t care. Bit3: OUT3: OUT Endpoint 3 Interrupt-pending Flag This bit is cleared when ...
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USB Register Definition 15.13. CMINT: USB0 Common Interrupt Bit7 Bit6 Bit5 Bits7–4: Unused. Read = 0000b; Write = don’t care. Bit3: SOF: Start of Frame Interrupt Set by hardware when a SOF token is ...
Page 156
C8051F320/1 USB Register Definition 15.14. IN1IE: USB0 IN Endpoint Interrupt Enable R/W R/W R Bit7 Bit6 Bit5 Bits7–4: Unused. Read = 0000b. Write = don’t care. Bit3: IN3E: IN Endpoint 3 Interrupt Enable 0: IN Endpoint 3 ...
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USB Register Definition 15.16. CMIE: USB0 Common Interrupt Enable R/W R/W R Bit7 Bit6 Bit5 Bits7–4: Unused. Read = 0000b; Write = don’t care. Bit3: SOFE: Start of Frame Interrupt Enable 0: SOF interrupt disabled. 1: SOF ...
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C8051F320/1 The E0CNT register (Figure 15.18) holds the number of received data bytes in the Endpoint0 FIFO. Hardware will automatically detect protocol errors and send a STALL condition in response. Firmware may force a STALL condition to abort the current ...
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OUT Transactions When a SETUP request is received that requires the host to transmit data to USB0, one or more OUT requests will be sent by the host. When an OUT packet is successfully received by USB0, hardware will ...
Page 160
C8051F320/1 USB Register Definition 15.17. E0CSR: USB0 Endpoint0 Control R/W R/W R/W SSUEND SOPRDY SDSTL Bit7 Bit6 Bit5 Bit7: SSUEND: Serviced Setup End Write: Software should set this bit to ‘1’ after servicing a Setup End (bit SUEND) event. Hardware ...
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USB Register Definition 15.18. E0CNT: USB0 Endpoint 0 Data Count Bit7 Bit6 Bit5 Bit7: Unused. Read = 0b; Write = don’t care. Bits6–0: E0CNT: Endpoint 0 Data Count This 7-bit number indicates the number of received ...
Page 162
C8051F320/1 A Bulk or Interrupt pipe can be shut down (or Halted) by writing ‘1’ to the SDSTL bit (EINCSRL.4). While SDSTL = ‘1’, hardware will respond to all IN requests with a STALL condition. Each time hardware gener- ates ...
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USB Register Definition 15.19. EINCSRL: USB0 IN Endpoint Control Low Byte R W R/W - CLRDT STSTL Bit7 Bit6 Bit5 Bit7: Unused. Read = 0b; Write = don’t care. Bit6: CLRDT: Clear Data Toggle. Write: Software should write ‘1’ to ...
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C8051F320/1 USB Register Definition 15.20. EINCSRH: USB0 IN Endpoint Control High Byte R/W R/W R/W DBIEN ISO DIRSEL Bit7 Bit6 Bit5 Bit7: DBIEN: IN Endpoint Double-buffer Enable. 0: Double-buffering disabled for the selected IN endpoint. 1: Double-buffering enabled for the ...
Page 165
A Bulk or Interrupt pipe can be shut down (or Halted) by writing ‘1’ to the SDSTL bit (EOUTCSRL.5). While SDSTL = ‘1’, hardware will respond to all OUT requests with a STALL condition. Each time hardware gen- erates a ...
Page 166
C8051F320/1 USB Register Definition 15.21. EOUTCSRL: USB0 OUT Endpoint Control High Byte W R/W R/W CLRDT STSTL SDSTL Bit7 Bit6 Bit5 Bit7: CLRDT: Clear Data Toggle Write: Software should write ‘1’ to this bit to reset the OUT endpoint data ...
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USB Register Definition 15.22. EOUTCSRH: USB0 OUT Endpoint Control Low Byte R/W R/W R/W DBOEN ISO - Bit7 Bit6 Bit5 Bit7: DBOEN: Double-buffer Enable 0: Double-buffering disabled for the selected OUT endpoint. 1: Double-buffering enabled for the selected OUT endpoint. ...
Page 168
C8051F320/1 Table 15.4. USB Transceiver Electrical Characteristics V = 3.0 to 3.6V, –40 to +85 °C unless otherwise specified. DD Parameters Symbol Transmitter V Output High Voltage OH V Output Low Voltage OL V Output Crossover Point CRS Z Output ...
Page 169
SMBus The SMBus I/O interface is a two-wire, bi-directional serial bus. The SMBus is compliant with the System Management Bus Specification, version 1.1, and compatible with the I the interface by the system controller are byte oriented with the ...
Page 170
C8051F320/1 16.1. Supporting Documents It is assumed the reader is familiar with or has access to the following supporting documents The I C-Bus and How to Use It (including specifications), Philips Semiconductor The I C-Bus Specification ...
Page 171
All transactions are initiated by a master, with one or more addressed slave devices as the target. The master generates the START condition and then transmits the slave address and direction bit. If the trans- action is a WRITE operation ...
Page 172
C8051F320/1 16.3.4. SCL High (SMBus Free) Timeout The SMBus specification stipulates that if the SCL and SDA lines remain high for more that 50 µs, the bus is designated as free. When the SMBFTE bit in SMB0CF is set, the ...
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SMBus Configuration Register The SMBus Configuration register (SMB0CF) is used to enable the SMBus Master and/or Slave modes, select the SMBus clock source, and select the SMBus timing and timeout options. When the ENSMB bit is set, the SMBus ...
Page 174
C8051F320/1 Figure 16.4 shows the typical SCL generation described by Equation 16.2. Notice that T twice as large The actual SCL output may vary due to other devices on the bus (SCL may be LOW extended low ...
Page 175
SFR Definition 16.1. R/W R/W R ENSMB INH BUSY EXTHOLD SMBTOE SMBFTE SMBCS1 SMBCS0 00000000 Bit7 Bit6 Bit5 Bit7: ENSMB: SMBus Enable. This bit enables/disables the SMBus interface. When enabled, the interface constantly mon- itors the SDA and SCL pins. ...
Page 176
C8051F320/1 16.4.2. SMB0CN Control Register SMB0CN is used to control the interface and to provide status information (see Figure 16.2). The higher four bits of SMB0CN (MASTER, TXMODE, STA, and STO) form a status vector that can be used to ...
Page 177
SFR Definition 16. R/W MASTER TXMODE STA Bit7 Bit6 Bit5 Bit7: MASTER: SMBus Master/Slave Indicator. This read-only bit indicates when the SMBus is operating as a master. 0: SMBus operating in Slave Mode. 1: SMBus operating in Master ...
Page 178
C8051F320/1 Table 16.3. Sources for Hardware Changes to SMB0CN Bit Set by Hardware When: • A START is generated. MASTER • START is generated. • SMB0DAT is written before the start of an TXMODE SMBus frame. • A START followed ...
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Data Register The SMBus Data register SMB0DAT holds a byte of serial data to be transmitted or one that has just been received. Software may safely read or write to the data register when the SI flag is set. ...
Page 180
C8051F320/1 16.5. SMBus Transfer Modes The SMBus interface may be configured to operate as master and/or slave. At any particular time, it will be operating in one of the following four modes: Master Transmitter, Master Receiver, Slave Transmitter, or Slave ...
Page 181
Master Receiver Mode Serial data is received on SDA while the serial clock is output on SCL. The SMBus interface generates the START condition and transmits the first byte containing the address of the target slave and the data ...
Page 182
C8051F320/1 16.5.3. Slave Receiver Mode Serial data is received on SDA and the clock is received on SCL. When slave events are enabled (INH = 0), the interface enters Slave Receiver Mode when a START followed by a slave address ...
Page 183
Slave Transmitter Mode Serial data is transmitted on SDA and the clock is received on SCL. When slave events are enabled (INH = 0), the interface enters Slave Receiver Mode (to receive the slave address) when a START followed ...
Page 184
C8051F320/1 16.6. SMBus Status Decoding The current SMBus status can be easily decoded using the SMB0CN register. In the table below, STATUS VECTOR refers to the four upper bits of SMB0CN: MASTER, TXMODE, STA, and STO. Note that the shown ...
Page 185
Table 16.4. SMBus Status Decoding (Continued) Values Read Current SMbus State A master data byte was received; 1000 ACK requested. A slave byte was transmitted NACK received. A slave byte was transmitted; 0100 0 ...
Page 186
C8051F320/1 Table 16.4. SMBus Status Decoding (Continued) Values Read Current SMbus State A slave address was received ACK requested. 0010 Lost arbitration as master; slave address received; ACK requested. Lost arbitration while attempting a ...
Page 187
UART0 UART0 is an asynchronous, full duplex serial port offering modes 1 and 3 of the standard 8051 UART. Enhanced baud rate support allows a wide range of clock sources to generate standard baud rates (details in Section “17.1. ...
Page 188
C8051F320/1 17.1. Enhanced Baud Rate Generation The UART0 baud rate is generated by Timer 1 in 8-bit auto-reload mode. The TX clock is generated by TL1; the RX clock is generated by a copy of TL1 (shown as RX Timer ...
Page 189
Figure 17.3. UART Interconnect Diagram 17.2.1. 8-Bit UART 8-Bit UART mode uses a total of 10 bits per data byte: one start bit, eight data bits (LSB first), and one stop bit. Data are transmitted LSB first from the TX0 ...
Page 190
C8051F320/1 17.2.2. 9-Bit UART 9-bit UART mode uses a total of eleven bits per data byte: a start bit, 8 data bits (LSB first), a programma- ble ninth data bit, and a stop bit. The state of the ninth transmit ...
Page 191
Master Slave Device Device Figure 17.6. UART Multi-Processor Mode Interconnect Diagram C8051F320/1 Slave Slave Device Device Rev. 1.4 V+ 191 ...
Page 192
C8051F320/1 SFR Definition 17.1. SCON0: Serial Port 0 Control R/W R R/W S0MODE - MCE0 Bit7 Bit6 Bit5 Bit7: S0MODE: Serial Port 0 Operation Mode. This bit selects the UART0 Operation Mode. 0: 8-bit UART with Variable Baud Rate. 1: ...
Page 193
SFR Definition 17.2. SBUF0: Serial (UART0) Port Data Buffer R/W R/W R/W Bit7 Bit6 Bit5 Bits7–0: SBUF0[7:0]: Serial Data Buffer Bits 7–0 (MSB-LSB) This SFR accesses two registers; a transmit shift register and a receive latch register. When data is ...
Page 194
C8051F320/1 Table 17.1. Timer Settings for Standard Baud Rates Using The Internal Oscillator Target Actual Baud Rate Baud Rate Baud Rate Error (bps) (bps) 230400 230769 0.16% 115200 115385 0.16% 57600 57692 0.16% 28800 28846 0.16% 14400 14423 0.16% 9600 ...
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Enhanced Serial Peripheral Interface (SPI0) The Enhanced Serial Peripheral Interface (SPI0) provides access to a flexible, full-duplex synchronous serial bus. SPI0 can operate as a master or slave device in both 3-wire or 4-wire modes, and supports mul- tiple ...
Page 196
C8051F320/1 18.1. Signal Descriptions The four signals used by SPI0 (MOSI, MISO, SCK, NSS) are described below. 18.1.1. Master Out, Slave In (MOSI) The master-out, slave-in (MOSI) signal is an output from a master device and an input to slave ...
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SPI0 Master Mode Operation A SPI master device initiates all data transfers on a SPI bus. SPI0 is placed in master mode by setting the Master Enable flag (MSTEN, SPI0CN.6). Writing a byte of data to the SPI0 data ...
Page 198
C8051F320/1 Master Device 1 Figure 18.2. Multiple-Master Mode Connection Diagram Master Device Figure 18.3. 3-Wire Single Master and Slave Mode Connection Diagram Master Device GPIO Figure 18.4. 4-Wire Single Master Mode and 4-Wire Slave Mode Connection 18.3. SPI0 Slave Mode ...
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When configured as a slave, SPI0 can be configured for 4-wire or 3-wire operation. The default, 4-wire slave mode, is active when NSSMD1 (SPI0CN. and NSSMD0 (SPI0CN. 4-wire mode, the NSS signal is routed to ...
Page 200
C8051F320/1 slower. When the SPI is configured as a slave, the maximum data transfer rate (bits/sec) for full-duplex operation is 1/10 the system clock frequency, provided that the master issues SCK, NSS (in 4-wire slave mode), and the serial input ...