R5F21244SNFP#U0 Renesas Electronics America, R5F21244SNFP#U0 Datasheet - Page 119

• Manufacturer Part Number: R5F21244SNFP#U0
• Description: IC R8C MCU FLASH 16K 52LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/R8C/Tiny/24r

Specifications of R5F21244SNFP#U0

• Core Processor: R8C
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, Voltage Detect, WDT
• Number Of I /o: 41
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 52-LQFP
• For Use With: R0K521256S000BE - KIT EVAL STARTER FOR R8C/25
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Rev.2.00 Oct 17, 2005
REJ09B0001-0200
OR
[ Syntax ]
[ Operation ]
[ Function ]
[ Selectable src/dest ]
[ Flag Change ]
[ Description Example ]
[ Related Instructions ]
Chapter 3 Functions
*1 If (.B) is selected as the size specifier (.size), A0 or A1 cannot be chosen for
Change
Conditions
R0L/R0
A0/A0
dsp:8[A0]
dsp:16[A0] dsp:16[A1]
dsp:20[A0] dsp:20[A1]
R2R0
OR.size (:format) src,dest
dest
Flag
• This instruction logically ORs
• If
S :
Z :
OR.B
OR.B:G
OR.B:G
OR.B:S
neously.
operation in 16 bits. If
*1
dest
U
The flag is set when the operation results in MSB = 1; otherwise cleared.
The flag is set when the operation results in 0; otherwise cleared.
src
is A0 or A1 and the selected size specifier (.size) is (.B),
R0H/R1
A1/A1
dsp:8[A1]
R3R1
I
Ram:8[SB],R0L
A0,R0L
R0L,A0
#3,R0L
O
*1
page 99 of 263
dest
B
src
R1L/R2
[A0]
dsp:8[SB]
dsp:16[SB]
abs20
A1A0
S
src
AND, XOR, TST
Z
is A0 or A1, operation is performed using the 8 low-order bits of A0 or A1.
dest
D
R1H/R3
[A1]
dsp:8[FB] dsp:8[A0]
abs16
#IMM
C
and
G , S (Can be specified)
B , W
(See next page for
src
Logically OR
and stores the result in
OR
R0L/R0
A0/A0
dsp:16[A0] dsp:16[A1] dsp:16[SB] abs16
dsp:20[A0] dsp:20[A1] abs20
R2R0
; 8 low-order bits of A0 and R0L are ORed.
; R0L is zero-expanded and ORed with A0.
*1
R0H/R1
A1/A1
dsp:8[A1]
R3R1
[ Instruction Code/Number of Cycles ]
src / dest
*1
src
dest
dest
is zero-expanded to perform
.
R1L/R2
[A0]
dsp:8[SB]
A1A0
classified by format.)
src
and
3.2
R1H/R3
[A1]
dsp:8[FB]
SP/SP
dest
Page: 209
Functions
simulta-
OR