R5F21244SNFP#U0 Renesas Electronics America, R5F21244SNFP#U0 Datasheet - Page 44

IC R8C MCU FLASH 16K 52LQFP

R5F21244SNFP#U0

Manufacturer Part Number
R5F21244SNFP#U0
Description
IC R8C MCU FLASH 16K 52LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M16C/R8C/Tiny/24r
Datasheets

Specifications of R5F21244SNFP#U0

Core Processor
R8C
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, LIN, SIO, SSU, UART/USART
Peripherals
POR, Voltage Detect, WDT
Number Of I /o
41
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.2 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
52-LQFP
For Use With
R0K521256S000BE - KIT EVAL STARTER FOR R8C/25
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R5F21244SNFP#U0
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Company:
Part Number:
R5F21244SNFP#U0R5F21244SNFP#V2
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Company:
Part Number:
R5F21244SNFP#U0R5F21244SNFP#X6
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Rev.2.00 Oct 17, 2005
REJ09B0001-0200
2.3 General Instruction Addressing
Chapter 2 Addressing Modes
Immediate
Register direct
Absolute
abs16
#IMM
#IMM8
#IMM16
#IMM20
R0L
R0H
R1L
R1H
R0
R1
R2
R3
A0
A1
Address register indirect
[A0]
[A1]
The value indicated by the content of
the address register (A0/A1) is the
effective address for the operation.
The effective address range is 00000
to 0FFFF
The immediate data indicated by #IMM
is the object of the operation.
The specified register is the object of
the operation.
The value indicated by abs16 is the
effective address for the operation.
The effective address range is 00000
0FFFF
16
page 24 of 263
.
16
.
16
to
16
A0 / A1
#IMM8
#IMM16
#IMM20
R0L / R1L
R0H / R1H
R0 / R1 / R2 /
R3 / A0 / A1
abs16
Register
address
b19
2.3 General Instruction Addressing
b15
b15
b15
b15
Memory
Register
b8 b7
b8
b8
b8
b7
b7
b7
Memory
b0
b0
b0
b0
b0

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