IC R8C MCU FLASH 32K 52LQFP

R5F21256SNFP#U0

Manufacturer Part NumberR5F21256SNFP#U0
DescriptionIC R8C MCU FLASH 32K 52LQFP
ManufacturerRenesas Electronics America
SeriesR8C/2x/25
R5F21256SNFP#U0 datasheets
 

Specifications of R5F21256SNFP#U0

Core ProcessorR8CCore Size16/32-Bit
Speed20MHzConnectivityI²C, LIN, SIO, SSU, UART/USART
PeripheralsPOR, Voltage Detect, WDTNumber Of I /o41
Program Memory Size32KB (32K x 8)Program Memory TypeFLASH
Ram Size2K x 8Voltage - Supply (vcc/vdd)2.2 V ~ 5.5 V
Data ConvertersA/D 12x10bOscillator TypeInternal
Operating Temperature-20°C ~ 85°CPackage / Case52-LQFP
For Use WithR0K521256S000BE - KIT EVAL STARTER FOR R8C/25Lead Free Status / RoHS StatusLead free / RoHS Compliant
Eeprom Size-  
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On April 1
, 2010, NEC Electronics Corporation merged with Renesas Technology
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R5F21256SNFP#U0 Summary of contents

  • Page 1

    To our customers, Old Company Name in Catalogs and Other Documents st On April 1 , 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the ...

  • Page 2

    All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm ...

  • Page 3

    R8C/Tiny Series 16 Software Manual RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER Rev.2.00 2005.10 ...

  • Page 4

    Keep safety first in your circuit designs! Renesas Technology Corp. puts the maximum effort into making semiconductor products 1. better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead ...

  • Page 5

    This software manual is written for the R8C/Tiny Series. It applies to all microcomputers integrating the R8C/Tiny Series CPU core. The reader of this manual is assumed to have a basic knowledge of electrical circuits, logic circuits, and microcomputers. This ...

  • Page 6

    M16C Family Documents The following documents were prepared for the M16C family. Document Short Sheet Data Sheet Hardware Manual Software Manual Application Note RENESAS TECHNICAL UPDATE NOTES: 1. Before using this material, please visit the our website to verify that ...

  • Page 7

    Chapter 1 Overview ___________________________________________________ 1.1 Features of R8C/Tiny Series ...................................................................................................... 2 1.1.1 Features of R8C/Tiny Series .............................................................................................. 2 1.1.2 Speed Performance ............................................................................................................ 2 1.2 Address Space ........................................................................................................................... 3 1.3 Register Configuration ................................................................................................................ 4 1.3.1 Data registers (R0, R0H, R0L, R1, ...

  • Page 8

    Data Arrangement .................................................................................................................... 16 1.8.1 Data Arrangement in Register .......................................................................................... 16 1.8.2 Data Arrangement in Memory ........................................................................................... 17 1.9 Instruction Formats ................................................................................................................... 18 1.9.1 Generic Format (:G) .......................................................................................................... 18 1.9.2 Quick Format (:Q) ............................................................................................................. 18 1.9.3 Short Format (:S) ...

  • Page 9

    Interrupt Control ...................................................................................................................... 249 5.2.1 I Flag ...............................................................................................................................249 5.2.2 IR Bit ...............................................................................................................................249 5.2.3 ILVL2 to ILVL0 bis, IPL ................................................................................................... 250 5.2.4 Changing Interrupt Control Register ............................................................................... 251 5.3 Interrupt Sequence .................................................................................................................252 5.3.1 Interrupt Response Time ................................................................................................ 253 5.3.2 Changes ...

  • Page 10

    Quick Reference in Alphabetic Order Page No. for Mnemonic Function ABS 39 ADC 40 ADCF 41 ADD 42 ADJNZ 44 AND 45 BAND 47 BCLR 48 BMCnd 49 BMEQ/Z 49 BMGE 49 BMGEU/C 49 BMGT 49 BMGTU 49 BMLE 49 ...

  • Page 11

    Quick Reference in Alphabetic Order Page No. for Mnemonic Function Dir MOV 93 MOVHH 93 MOVHL 93 MOVLH 93 MOVLL 93 MUL 94 MULU 95 NEG 96 NOP 97 NOT POP 101 POPC 102 POPM 103 PUSH ...

  • Page 12

    Quick Reference by Function Function Mnemonic Transfer MOV MOVA MOVDir POP POPM PUSH PUSHA PUSHM LDE STE STNZ STZ STZX XCHG Bit BAND manipulation BCLR Cnd BM BNAND BNOR BNOT BNTST BNXOR BOR BSET BTST BTSTC BTSTS BXOR Shift ROLC ...

  • Page 13

    Quick Reference by Function Function Mnemonic Arithmetic DADD DEC DIV DIVU DIVX DSBB DSUB EXTS INC MUL MULU NEG RMPA SBB SUB Logical AND NOT OR TST XOR Jump ADJNZ SBJNZ JCnd JMP JMPI JSR JSRI RTS String SMOVB SMOVF ...

  • Page 14

    Quick Reference by Function Function Mnemonic Other LDIPL NOP POPC PUSHC REIT STC STCTX UND WAIT Description Set interrupt enable level No operation Restore control register Save control register Return from interrupt Transfer from control register Save context Interrupt for ...

  • Page 15

    Quick Reference by Addressing Mode (General Instruction Addressing) Mnemonic ABS ADC ADCF *1 ADD *1 ADJNZ AND CMP DADC DADD DEC DIV DIVU DIVX DSBB DSUB ENTER *2 EXTS *3 *4 INC INT *1 JMPI *1 JSRI *1 LDC *1 ...

  • Page 16

    Quick Reference by Addressing Mode (General Instruction Addressing) Mnemonic *1 MOV MOVA Dir MOV MUL MULU NEG NOT OR POP *1 POPM PUSH PUSHA *1 PUSHM ROLC RORC ROT SBB *1 SBJNZ *1 SHA *1 SHL *1 STC *1 STCTX ...

  • Page 17

    Quick Reference by Addressing Mode (General Instruction Addressing) Mnemonic STZX SUB TST XCHG XOR Addressing Mode Quick Reference-8 Page No. for Page No. for Function Instruction Code /No. of Cycles 126 236 127 236 129 239 132 242 133 243 ...

  • Page 18

    Quick Reference by Addressing Mode (Special Instruction Addressing) Mnemonic *1 ADD *1 ADJNZ JCnd JMP *1 JMPI JSR *1 JSRI *1 LDC LDCTX *1 LDE LDINTB *1 MOV POPC *1 POPM PUSHC *1 PUSHM *1 SBJNZ *1 SHA *1 SHL ...

  • Page 19

    Quick Reference by Addressing Mode (Bit Instruction Addressing) Addressing Mode Mnemonic BAND BCLR Cnd BM BNAND BNOR BNOT BNTST BNXOR BOR BSET BTST BTSTC BTSTS BXOR FCLR FSET Page No. for Function ...

  • Page 20

    This page intentionally left blank. Quick Reference-11 ...

  • Page 21

    Features of R8C/Tiny Series 1.2 Address Space 1.3 Register Configuration 1.4 Flag Register (FLG) 1.5 Register Banks 1.6 Internal State after Reset is Cleared 1.7 Data Types 1.8 Data Arrangement 1.9 Instruction Formats 1.10 Vector Tables Chapter 1 Overview ...

  • Page 22

    Chapter 1 Overview 1.1 Features of R8C/Tiny Series The R8C/Tiny Series of single-chip microcomputers was developed for embedded applications. The R8C/Tiny Series supports instructions tailored for the C language, with frequently used instructions implemented in one-byte op-code. It thus allows ...

  • Page 23

    Chapter 1 Overview 1.2 Address Space Figure 1.2.1 shows the address space. Addresses 00000 through 002FF 16 the R8C/Tiny Series, the SFR area extends from 002FF Addresses from 00400 and below make up the memory area. In some models in ...

  • Page 24

    Chapter 1 Overview 1.3 Register Configuration The central processing unit (CPU) contains the 13 registers shown in figure 1.3.1. Of these registers, R0, R1, R2, R3, A0, A1, and FB each consist of two sets of registers configured as two ...

  • Page 25

    Chapter 1 Overview 1.3.2 Address Registers (A0 and A1) The address registers (A0 and A1) are 16-bit registers with functions similar to those of the data regis- ters. These registers are used for address register-based indirect addressing and address register- ...

  • Page 26

    Chapter 1 Overview 1.4 Flag Register (FLG) Figure 1.4.1 shows the configuration of the flag register (FLG). The function of each flag is described below. 1.4.1 Bit 0: Carry Flag (C Flag) This flag holds bits carried, borrowed, or shifted-out ...

  • Page 27

    Chapter 1 Overview 1.4.10 Bits 12 to 14: Processor Interrupt Priority Level (IPL) The processor interrupt priority level (IPL) consists of three bits, enabling specification of eight proces- sor interrupt priority levels from level 0 to level ...

  • Page 28

    Chapter 1 Overview 1.5 Register Banks The R8C/Tiny has two register banks, each comprising data registers (R0, R1, R2, and R3), address regis- ters (A0 and A1), and a frame base register (FB). These two register banks are switched by ...

  • Page 29

    Chapter 1 Overview 1.6 Internal State after Reset is Cleared The contents of each register after a reset is cleared are as follows. • Data registers (R0, R1, R2, and R3): 0000 • Address registers (A0 and A1): 0000 • ...

  • Page 30

    Chapter 1 Overview 1.7 Data Types There are four data types: integer, decimal, bit, and string. 1.7.1 Integer An integer can be signed or unsigned. A negative value of a signed integer is represented by two’s complement. Signed byte (8 ...

  • Page 31

    Chapter 1 Overview 1.7.2 Decimal The decimal data type is used by the DADC, DADD, DSBB, and DSUB instructions. Pack format (2 digits) Pack format (4 digits) Figure 1.7.2 Decimal Data Rev.2.00 Oct 17, 2005 page 11 of 263 REJ09B0001-0200 ...

  • Page 32

    Chapter 1 Overview 1.7.3 Bits Register bits Figure 1.7.3 shows register bit specification. Register bits can be specified by register directly (bit bit, An). Use bit specify a bit in a data register (Rn); use bit, ...

  • Page 33

    Chapter 1 Overview (1) Bit Specification by Bit, Base Figure 1.7.5 shows the relationship between the memory map and the bit map. Memory bits can be handled as an array of consecutive bits. Bits can be specified by a combination ...

  • Page 34

    Chapter 1 Overview (2) SB/FB Relative Bit Specification For SB/FB-based relative addressing, use bit 0 of the address that is the sum of the address set in static base register (SB) or frame base register (FB) plus the address set ...

  • Page 35

    Chapter 1 Overview 1.7.4 String String data consists of a given length of consecutive byte (8-bit) or word (16-bit) data. This data type can be used in three string instructions: character string backward transfer (SMOVB instruction), character string forward transfer ...

  • Page 36

    Chapter 1 Overview 1.8 Data Arrangement 1.8.1 Data Arrangement in Register Figure 1.8.1 shows the relationship between a register’s data size and bit numbers. Nibble (4-bit) data Byte (8-bit) data Word (16-bit) data Long word (32-bit) data Figure 1.8.1 Data ...

  • Page 37

    Chapter 1 Overview 1.8.2 Data Arrangement in Memory Figure 1.8.2 shows the data arrangement in memory. Figure 1.8.3 shows some operation examples. N N+1 N+2 N+3 Byte (8-bit) data N N+1 N+2 N+3 20-bit (Address) data Figure 1.8.2 Data Arrangement ...

  • Page 38

    Chapter 1 Overview 1.9 Instruction Formats The instruction formats can be classified into four types: generic, quick, short, and zero. The number of instruction bytes that can be chosen by a given format is least for the zero format, and ...

  • Page 39

    Chapter 1 Overview 1.10 Vector Tables Interrupt vector tables are the only vector tables. There are two types of interrupt vector tables: fixed and variable. 1.10.1 Fixed Vector Tables A fixed vector table is an address-fixed vector table. Part of ...

  • Page 40

    Chapter 1 Overview 1.10.2 Variable Vector Tables A variable vector table is an address-variable vector table. Specifically, this type of vector table is a 256- byte interrupt vector table that uses the value indicated by the interrupt table register (INTB) ...

  • Page 41

    Addressing Modes 2.1 Addressing Modes 2.2 Guide to This Chapter 2.3 General Instruction Addressing 2.4 Special Instruction Addressing 2.5 Bit Instruction Addressing Chapter 2 ...

  • Page 42

    Chapter 2 Addressing Modes 2.1 Addressing Modes This section describes the symbols used to represent addressing modes and operations of each address- ing mode. The R8C/Tiny Series has three types of addressing modes as outlined below. 2.1.1 General Instruction Addressing ...

  • Page 43

    Chapter 2 Addressing Modes 2.2 Guide to This Chapter An example illustrating how to read this chapter is shown below. (1) Address register relative The value indicated by the displace- dsp:8[A0] ment (dsp) plus the content of the (2) dsp:8[A1] ...

  • Page 44

    Chapter 2 Addressing Modes 2.3 General Instruction Addressing Immediate The immediate data indicated by #IMM #IMM is the object of the operation. #IMM8 #IMM16 #IMM20 Register direct The specified register is the object of R0L the operation. R0H R1L R1H ...

  • Page 45

    Chapter 2 Addressing Modes Address register relative The value indicated by the displace- dsp:8[A0] ment (dsp) plus the content of the dsp:8[A1] address register (A0/A1)—added dsp:16[A0] without the sign bits—is the effective address for the operation. dsp:16[A1] However, if the ...

  • Page 46

    Chapter 2 Addressing Modes Stack pointer relative dsp:8[SP] The address indicated by the content of the stack pointer (SP) plus the value indicated by the displacement (dsp)—added including the sign bits—is the effective address for the operation. The stack pointer ...

  • Page 47

    Chapter 2 Addressing Modes 2.4 Special Instruction Addressing 20-bit absolute The value indicated by abs20 is the abs20 effective address for the operation. The effective address range is 00000 FFFFF . 16 This addressing mode can be used with the ...

  • Page 48

    Chapter 2 Addressing Modes 32-bit register direct The 32-bit concatenated register content of two R2R0 specified registers is the object of the operation. R3R1 A1A0 This addressing mode can be used with the SHL, SHA, JMPI, and JSRI instructions. Valid ...

  • Page 49

    Chapter 2 Addressing Modes Program counter relative • If the jump length specifier (.length) label is (.S), the base address plus the value indicated by the displacement (dsp)—added without the sign bits—is the effective address. This addressing mode can be ...

  • Page 50

    Chapter 2 Addressing Modes 2.5. Bit Instruction Addressing This addressing mode type can be used with the following instructions: BCLR, BSET, BNOT, BTST, BNTST, BAND, BNAND, BOR, BNOR, BXOR, BNXOR, BM Register direct The specified register bit is the object ...

  • Page 51

    Chapter 2 Addressing Modes Address register relative base:8[A0] The bit that is the number of bits base:8[A1] indicated by the address register base:16[A0] (A0/A1) away from bit 0 at the address indicated by base is the base:16[A1] object of the ...

  • Page 52

    Chapter 2 Addressing Modes FB relative The bit that is the number of bits bit,base:8[FB] indicated by bit away from bit 0 at the address indicated by the frame base register (FB) plus the value indicated by base (added including ...

  • Page 53

    Guide to This Chapter 3.2 Functions Chapter 3 Functions ...

  • Page 54

    Chapter 3 Functions 3.1 Guide to This Chapter In this chapter each instruction’s syntax, operation, function, selectable src/dest, and flag changes are listed, and description examples and related instructions are shown. An example illustrating how to read this chapter is ...

  • Page 55

    Chapter 3 Functions (1) Mnemonic The mnemonic explained in the page. (2) Instruction Code/Number of Cycles The page on which the instruction code and number of cycles is listed. Refer to this page for information on the instruction code and ...

  • Page 56

    Chapter 3 Functions Chapter 3 Functions MOV (1) (2) [ Syntax ] (3) MOV.size (:format) src,dest (4) [ Operation ] dest src [ Function ] (5) • This instruction transfers dest • and the selected ...

  • Page 57

    Chapter 3 Functions (4) Operation Explains the operation of the instruction using symbols. (5) Function Explains the function of the instruction and precautions to be taken when using the instruction. (6) Selectable src / dest (label) If the instruction has ...

  • Page 58

    Chapter 3 Functions The syntax of the jump instructions JMP, JPMI, JSR, and JSRI are illustrated below by example . Chapter 3 Functions JMP (1) (2) [ Syntax ] (3) JMP (.length) label (3) Syntax Indicates the instruction syntax using ...

  • Page 59

    Chapter 3 Functions ABS [ Syntax ] ABS.size dest [ Operation ] dest dest [ Function ] • This instruction takes the absolute value of [ Selectable dest ] [ Flag Change ] Flag Change ...

  • Page 60

    Chapter 3 Functions ADC [ Syntax ] ADC.size src,dest [ Operation ] dest src + dest + [ Function ] dest • This instruction adds dest • and the selected size specifier (.size) is (.B), ...

  • Page 61

    Chapter 3 Functions ADCF [ Syntax ] ADCF.size dest [ Operation ] dest dest + C [ Function ] dest This instruction adds [ Selectable dest ] [ Flag Change ] Flag Change Conditions O ...

  • Page 62

    Chapter 3 Functions ADD [ Syntax ] ADD.size (:format) src,dest [ Operation ] dest dest + src [ Function ] dest • This instruction adds dest • and the selected size specifier (.size) is (.B), ...

  • Page 63

    Chapter 3 Functions [src/dest Classified by Format] G format src R0L/R0 R0H/R1 R1L/R2 A0/A0 *1 A1/A1 *1 [A0] dsp:8[A0] dsp:8[A1] dsp:8[SB] dsp:16[A0] dsp:16[A1] dsp:16[SB] dsp:20[A0] dsp:20[A1] abs20 R2R0 R3R1 A1A0 *1 If (.B) is selected as the size specifier (.size), ...

  • Page 64

    Chapter 3 Functions ADJNZ [ Syntax ] ADJNZ.size src,dest,label [ Operation ] dest dest + src if dest 0 then jump label [ Function ] dest • This instruction adds • If the addition results in any value other than ...

  • Page 65

    Chapter 3 Functions AND [ Syntax ] AND.size (:format) src,dest [ Operation ] dest src dest [ Function ] • This instruction logically ANDs dest • and the selected size specifier (.size) is (.B), src ...

  • Page 66

    Chapter 3 Functions [src/dest Classified by Format] G format src R0L/R0 R0H/R1 R1L/R2 A0/A0 *1 A1/A1 *1 [A0] dsp:8[A0] dsp:8[A1] dsp:8[SB] dsp:16[A0] dsp:16[A1] dsp:16[SB] dsp:20[A0] dsp:20[A1] abs20 R2R0 R3R1 A1A0 *1 If (.B) is selected as the size specifier (.size), ...

  • Page 67

    Chapter 3 Functions BAND [ Syntax ] BAND src [ Operation ] C src C [ Function ] • This instruction logically ANDs the C flag and [ Selectable src ] src bit,R0 bit,R1 bit,R2 bit,A0 bit,A1 [A0] base:8[A0] base:8[A1] ...

  • Page 68

    Chapter 3 Functions BCLR [ Syntax ] BCLR (:format) dest [ Operation ] dest 0 [ Function ] • This instruction stores Selectable dest ] [ Flag Change ] Flag Change [ ...

  • Page 69

    Chapter 3 Functions BM Cnd [ Syntax ] BM Cnd dest [ Operation ] if true then dest 1 else dest 0 [ Function ] • This instruction transfers the true or false value of the condition indicated by condition ...

  • Page 70

    Chapter 3 Functions BNAND [ Syntax ] BNAND src [ Operation ] ______ C src C [ Function ] • This instruction logically ANDs the C flag and the inverted value of flag. [ Selectable src ] src bit,R0 bit,R1 ...

  • Page 71

    Chapter 3 Functions BNOR [ Syntax ] BNOR src [ Operation ] ______ C src C [ Function ] • This instruction logically ORs the C flag and the inverted value of flag. [ Selectable src ] src bit,R0 bit,R1 ...

  • Page 72

    Chapter 3 Functions BNOT [ Syntax ] BNOT(:format) dest [ Operation ] ________ dest dest [ Function ] dest • This instruction inverts [ Selectable dest ] [ Flag Change ] Flag Change [ Description ...

  • Page 73

    Chapter 3 Functions BNTST [ Syntax ] BNTST src [ Operation ] Z src ______ C src [ Function ] • This instruction transfers the inverted value of flag. [ Selectable src ] src bit,R0 bit,R1 bit,R2 bit,A0 bit,A1 [A0] ...

  • Page 74

    Chapter 3 Functions BNXOR [ Syntax ] BNXOR src [ Operation ] ______ A C src C [ Function ] • This instruction exclusive ORs the C flag and the inverted value of flag. [ Selectable src ] src bit,R0 ...

  • Page 75

    Chapter 3 Functions BOR [ Syntax ] BOR src [ Operation ] C src C [ Function ] • This instruction logically ORs the C flag and [ Selectable src ] src bit,R0 bit,R1 bit,R2 bit,A0 bit,A1 [A0] base:8[A0] base:8[A1] ...

  • Page 76

    Chapter 3 Functions BRK [ Syntax ] BRK [ Operation ] SP SP – 2 M(SP) ( – 2 M(SP) ( M(FFFE4 ) 16 [ Function ] • This instruction generates ...

  • Page 77

    Chapter 3 Functions BSET [ Syntax ] BSET (:format) dest [ Operation ] dest 1 [ Function ] • This instruction stores Selectable dest ] [ Flag Change ] Flag Change [ ...

  • Page 78

    Chapter 3 Functions BTST [ Syntax ] BTST (:format) src [ Operation ] ______ Z src C src [ Function ] • This instruction transfers the inverted value of the C flag. [ Selectable src ] src bit,R0 bit,R1 bit,R2 ...

  • Page 79

    Chapter 3 Functions BTSTC [ Syntax ] BTSTC dest [ Operation ] ________ Z dest C dest dest 0 [ Function ] • This instruction transfers the inverted value of dest to the C flag. Then it stores 0 in ...

  • Page 80

    Chapter 3 Functions BTSTS [ Syntax ] BTSTS dest [ Operation ] ________ Z dest C dest dest 1 [ Function ] • This instruction transfers the inverted value of the C flag. Then it stores Selectable ...

  • Page 81

    Chapter 3 Functions BXOR [ Syntax ] BXOR src [ Operation ] A C src C [ Function ] • This instruction exclusive ORs the C flag and [ Selectable src ] src bit,R0 bit,R1 bit,R2 bit,A0 bit,A1 [A0] base:8[A0] ...

  • Page 82

    Chapter 3 Functions CMP [ Syntax ] CMP.size (:format) src,dest [ Operation ] dest – src [ Function ] • Flag bits in the flag register change depending on the result of subtraction of dest • ...

  • Page 83

    Chapter 3 Functions [src/dest Classified by Format] G format src R0L/R0 R0H/R1 R1L/R2 A0/A0 *1 A1/A1 *1 [A0] dsp:8[A0] dsp:8[A1] dsp:8[SB] dsp:16[A0] dsp:16[A1] dsp:16[SB] dsp:20[A0] dsp:20[A1] abs20 R2R0 R3R1 A1A0 *1 If (.B) is selected as the size specifier (.size), ...

  • Page 84

    Chapter 3 Functions DADC [ Syntax ] DADC.size src,dest [ Operation ] dest src + dest + [ Function ] dest • This instruction adds [ Selectable src/dest ] src R0L/R0 R0H/R1 R1L/R2 A0/A0 A1/A1 [A0] dsp:8[A0] dsp:8[A1] dsp:8[SB] dsp:16[A0] ...

  • Page 85

    Chapter 3 Functions DADD [ Syntax ] DADD.size src,dest [ Operation ] dest src + dest [ Function ] dest • This instruction adds [ Selectable src/dest ] src R0L/R0 R0H/R1 R1L/R2 A0/A0 A1/A1 [A0] dsp:8[A0] dsp:8[A1] dsp:8[SB] dsp:16[A0] dsp:16[A1] ...

  • Page 86

    Chapter 3 Functions DEC [ Syntax ] DEC.size dest [ Operation ] dest dest – Function ] • This instruction decrements [ Selectable dest ] [ Flag Change ] Flag Change Conditions S ...

  • Page 87

    Chapter 3 Functions DIV [ Syntax ] DIV.size src [ Operation ] If the size specifier (.size) is (.B) R0L (quotient), R0H (remainder) If the size specifier (.size) is (.W) R0 (quotient), R2 (remainder) [ Function ] • This instruction ...

  • Page 88

    Chapter 3 Functions DIVU [ Syntax ] DIVU.size src [ Operation ] If the size specifier (.size) is (.B) R0L (quotient), R0H (remainder) If the size specifier (.size) is (.W) R0 (quotient), R2 (remainder) [ Function ] • This instruction ...

  • Page 89

    Chapter 3 Functions DIVX [ Syntax ] DIVX.size src [ Operation ] If the size specifier (.size) is (.B) R0L (quotient), R0H (remainder) If the size specifier (.size) is (.W) R0 (quotient), R2 (remainder) [ Function ] • This instruction ...

  • Page 90

    Chapter 3 Functions DSBB [ Syntax ] DSBB.size src,dest [ Operation ] dest dest – src – [ Function ] • This instruction subtracts dest stores the result Selectable src/dest ] src R0L/R0 R0H/R1 R1L/R2 A0/A0 A1/A1 ...

  • Page 91

    Chapter 3 Functions DSUB [ Syntax ] DSUB.size src,dest [ Operation ] dest dest – src [ Function ] • This instruction subtracts [ Selectable src/dest ] src R0L/R0 R0H/R1 R1L/R2 A0/A0 A1/A1 [A0] dsp:8[A0] dsp:8[A1] dsp:8[SB] dsp:16[A0] dsp:16[A1] dsp:16[SB] ...

  • Page 92

    Chapter 3 Functions ENTER [ Syntax ] ENTER src [ Operation ] SP SP – M(SP – [ Function ] • This instruction generates a stack frame. • The diagrams below show the stack area ...

  • Page 93

    Chapter 3 Functions EXITD [ Syntax ] EXITD [ Operation ] M(SP M(SP M(SP Function ] • This instruction deallocates a stack frame ...

  • Page 94

    Chapter 3 Functions EXTS [ Syntax ] EXTS.size dest [ Operation ] dest EXT(dest) [ Function ] • This instruction sign extends • If (.B) is selected as the size specifier (.size), • If (.W) is selected as the size ...

  • Page 95

    Chapter 3 Functions FCLR [ Syntax ] FCLR dest [ Operation ] dest 0 [ Function ] • This instruction stores Selectable dest ] [ Flag Change ] Flag Change *1 *1 ...

  • Page 96

    Chapter 3 Functions FSET [ Syntax ] FSET dest [ Operation ] dest 1 [ Function ] • This instruction stores Selectable dest ] [ Flag Change ] Flag Change *1 *1 ...

  • Page 97

    Chapter 3 Functions INC [ Syntax ] INC.size dest [ Operation ] dest dest + 1 [ Function ] • This instruction adds Selectable dest ] [ Flag Change ] Flag Change ...

  • Page 98

    Chapter 3 Functions INT [ Syntax ] INT src [ Operation ] SP SP – 2 M(SP) ( – 2 M(SP) ( M(IntBase + [ Function ] • This instruction generates ...

  • Page 99

    Chapter 3 Functions INTO [ Syntax ] INTO [ Operation ] SP SP – 2 M(SP) ( – 2 M(SP) ( M(FFFE0 ) 16 [ Function ] • If the O ...

  • Page 100

    Chapter 3 Functions J Cnd [ Syntax ] J Cnd label [ Operation ] if true then jump label [ Function ] • This instruction causes program flow to branch after checking the execution result of the preceding instruction against ...

  • Page 101

    Chapter 3 Functions JMP [ Syntax ] JMP(.length) label [ Operation ] PC label [ Function ] • This instruction causes control to jump to label. [ Selectable label ] .length label * label ...

  • Page 102

    Chapter 3 Functions JMPI [ Syntax ] JMPI.length src [ Operation ] When jump distance specifier (.length src [ Function ] • This instruction causes control to jump to the address indicated by memory, specify the ...

  • Page 103

    Chapter 3 Functions JSR [ Syntax ] JSR(.length) label [ Operation ] SP SP – M(SP) ( – M(SP) ( label *1 n denotes the number of instruction bytes. [ Function ] • This instruction ...

  • Page 104

    Chapter 3 Functions JSRI [ Syntax ] JSRI.length src [ Operation ] When jump distance specifier (.length – 1 M(SP) ( – 2 M(SP) ( src *1 n ...

  • Page 105

    Chapter 3 Functions LDC [ Syntax ] LDC src,dest [ Operation ] dest src [ Function ] • This instruction transfers memory, the required memory capacity is 2 bytes. • If the destination is INTBL or INTBH, make sure that ...

  • Page 106

    Chapter 3 Functions LDCTX [ Syntax ] LDCTX abs16,abs20 [ Function ] • This instruction restores task context from the stack area. • Set the RAM address that contains the task number in abs16 and the start address of table ...

  • Page 107

    Chapter 3 Functions LDE [ Syntax ] LDE.size src,dest [ Operation ] dest src [ Function ] • This instruction transfers dest • and the selected size specifier (.size) is (.B bits. [ ...

  • Page 108

    Chapter 3 Functions LDINTB [ Syntax ] LDINTB src [ Operation ] INTBHL src [ Function ] • This instruction transfers • The LDINTB instruction is a macro-instruction consisting of the following: LDC LDC [ Selectable src ] src #IMM20 ...

  • Page 109

    Chapter 3 Functions LDIPL [ Syntax ] LDIPL src [ Operation ] IPL src [ Function ] • This instruction transfers [ Selectable src ] src #IMM *1 *1 The acceptable range of values is 0 < #IMM < 7 ...

  • Page 110

    Chapter 3 Functions MOV [ Syntax ] MOV.size (:format) src,dest [ Operation ] dest src [ Function ] • This instruction transfers dest • and the selected size specifier (.size) is (.B), src in 16 ...

  • Page 111

    Chapter 3 Functions [src/dest Classified by Format] G format src R0L/R0 R0H/R1 R1L/R2 A0/A0 *1 A1/A1 *1 [A0] dsp:8[A0] dsp:8[A1] dsp:8[SB] dsp:16[A0] dsp:16[A1] dsp:16[SB] dsp:20[A0] dsp:20[A1] abs20 R2R0 R3R1 A1A0 *1 If (.B) is selected as the size specifier (.size), ...

  • Page 112

    Chapter 3 Functions MOVA [ Syntax ] MOVA src,dest [ Operation ] dest EVA(src) [ Function ] • This instruction transfers the affective address of [ Selectable src/dest ] src R0L/R0 R0H/R1 R1L/R2 A0/A0 A1/A1 [A0] dsp:8[A0] dsp:8[A1] dsp:8[SB] dsp:16[A0] ...

  • Page 113

    Chapter 3 Functions MOV Dir [ Syntax ] MOV Dir src,dest [ Operation ] Dir Operation HH H4:dest H4:src HL L4:dest H4:src LH H4:dest L4:src LL L4:dest L4:src [ Function ] • Be sure to choose R0L for either Dir ...

  • Page 114

    Chapter 3 Functions MUL [ Syntax ] MUL.size src,dest [ Operation ] dest dest src [ Function ] • This instruction multiplies • If (.B) is selected as the size specifier (.size), and the result is stored in 16 bits. ...

  • Page 115

    Chapter 3 Functions MULU [ Syntax ] MULU.size src,dest [ Operation ] dest dest src [ Function ] • This instruction multiplies • If (.B) is selected as the size specifier (.size), and the result is stored in 16 bits. ...

  • Page 116

    Chapter 3 Functions NEG [ Syntax ] NEG.size dest [ Operation ] dest 0 – dest [ Function ] • This instruction takes the complement of two of [ Selectable dest ] [ Flag Change ] Flag ...

  • Page 117

    Chapter 3 Functions NOP [ Syntax ] NOP [ Operation ] Function ] • This instruction adds 1 to PC. [ Flag Change ] Flag Change [ Description Example ] ...

  • Page 118

    Chapter 3 Functions NOT [ Syntax ] NOT.size (:format) dest [ Operation ] ________ dest dest [ Function ] dest • This instruction inverts [ Selectable dest ] [ Flag Change ] Flag Change Conditions ...

  • Page 119

    Chapter 3 Functions OR [ Syntax ] OR.size (:format) src,dest [ Operation ] dest src dest [ Function ] • This instruction logically ORs dest • and the selected size specifier (.size) is (.B), src ...

  • Page 120

    Chapter 3 Functions [src/dest Classified by Format] G format src R0L/R0 R0H/R1 R1L/R2 A0/A0 *1 A1/A1 *1 [A0] dsp:8[A0] dsp:8[A1] dsp:8[SB] dsp:16[A0] dsp:16[A1] dsp:16[SB] dsp:20[A0] dsp:20[A1] abs20 R2R0 R3R1 A1A0 *1 If (.B) is selected as the size specifier (.size), ...

  • Page 121

    Chapter 3 Functions POP [ Syntax ] POP.size (:format) dest [ Operation ] If the size specifier (.size) is (.B) dest M(SP Function ] • This instruction restores [ Selectable dest ] [ Flag Change ...

  • Page 122

    Chapter 3 Functions POPC [ Syntax ] POPC dest [ Operation ] dest M(SP dest *1 When when the U flag = 0 and [ Function ] • This instruction restores data ...

  • Page 123

    Chapter 3 Functions POPM [ Syntax ] POPM dest [ Operation ] dest M(SP Number of registers to be restored [ Function ] • This instruction restores the registers selected by • Registers are ...

  • Page 124

    Chapter 3 Functions PUSH [ Syntax ] PUSH.size (:format) src [ Operation ] If the size specifier (.size – 1 M(SP) src [ Function ] src • This instruction saves [ Selectable src ] src *1 ...

  • Page 125

    Chapter 3 Functions PUSHA [ Syntax ] PUSHA src [ Operation ] SP SP – 2 M(SP) EVA(src) [ Function ] • This instruction saves the effective address of [ Selectable src ] src R0L/R0 R0H/R1 R1L/R2 A0/A0 A1/A1 [A0] ...

  • Page 126

    Chapter 3 Functions PUSHC [ Syntax ] PUSHC src [ Operation ] SP SP – 2 M(SP) src *1 src *1 When when the U flag = 0 and [ Function ] • This instruction saves the ...

  • Page 127

    Chapter 3 Functions PUSHM [ Syntax ] PUSHM src [ Operation ] SP SP – M(SP) src *1 Number of registers saved. [ Function ] • This instruction saves the registers selected by • The registers are saved ...

  • Page 128

    Chapter 3 Functions REIT [ Syntax ] REIT [ Operation ] PC M(SP FLG M(SP Function ] • This instruction restores the PC and FLG values that were saved ...

  • Page 129

    Chapter 3 Functions RMPA [ Syntax ] RMPA.size [ Operation ] *1 Repeat R2R0(R0 Until set to 0, this instruction is ignored. *2 Items in parentheses and followed by ...

  • Page 130

    Chapter 3 Functions ROLC [ Syntax ] ROLC.size dest [ Operation ] [ Function ] dest • This instruction rotates [ Selectable dest ] [ Flag Change ] Flag Change Conditions S : The flag ...

  • Page 131

    Chapter 3 Functions RORC [ Syntax ] RORC.size dest [ Operation ] [ Function ] dest • This instruction rotates [ Selectable dest ] [ Flag Change ] Flag Change Conditions S : The flag ...

  • Page 132

    Chapter 3 Functions ROT [ Syntax ] ROT.size src,dest [ Operation ] C [ Function ] dest • This instruction rotates (MSB) are transferred to MSB (LSB) and the C flag. • The direction of rotation is determined by the ...

  • Page 133

    Chapter 3 Functions RTS [ Syntax ] RTS [ Operation ] PC M(SP M(SP Function ] • This instruction causes control to return from a subroutine. [ Flag ...

  • Page 134

    Chapter 3 Functions SBB [ Syntax ] SBB.size src,dest [ Operation ] dest dest – src – [ Function ] • This instruction subtracts dest • and the selected size specifier (.size) is (.B), src ...

  • Page 135

    Chapter 3 Functions SBJNZ [ Syntax ] SBJNZ.size src,dest,label [ Operation ] dest dest – src if dest 0 then jump label [ Function ] • This instruction subtracts • If the operation results in any value other than 0, ...

  • Page 136

    Chapter 3 Functions SHA [ Syntax ] SHA.size src,dest [ Operation ] src When < 0 src When > Function ] • This instruction arithmetically shifts ing from LSB (MSB) are transferred to the C flag. src • ...

  • Page 137

    Chapter 3 Functions SHL [ Syntax ] SHL.size src,dest [ Operation ] src When < 0 src When > Function ] • This instruction logically shifts from LSB (MSB) are transferred to the C flag. • The direction ...

  • Page 138

    Chapter 3 Functions SMOVB [ Syntax ] SMOVB.size [ Operation ] *1 When size specifier (.size) is (.B) Repeat M(A1) M Until set to 0, this ...

  • Page 139

    Chapter 3 Functions SMOVF [ Syntax ] SMOVF.size [ Operation ] *1 When size specifier (.size) is (.B) Repeat M(A1) M Until set to 0, this ...

  • Page 140

    Chapter 3 Functions SSTR [ Syntax ] SSTR.size [ Operation ] *1 When size specifier (.size) is (.B) Repeat M(A1) R0L Until set to 0, this instruction is ignored. [ Function ...

  • Page 141

    Chapter 3 Functions STC [ Syntax ] STC src,dest [ Operation ] dest src [ Function ] • This instruction transfers the content of the control register indicated by location in the memory, specify the address in which to store ...

  • Page 142

    Chapter 3 Functions STCTX [ Syntax ] STCTX abs16,abs20 [ Operation ] [ Function ] • This instruction saves task context to the stack area. • Set the RAM address that contains the task number in abs16 and the start ...

  • Page 143

    Chapter 3 Functions STE [ Syntax ] STE.size src,dest [ Operation ] dest src [ Function ] • This instruction transfers src • and the selected size specifier (.size) is (.B), the operation is performed ...

  • Page 144

    Chapter 3 Functions STNZ [ Syntax ] STNZ src,dest [ Operation ] then dest src [ Function ] • This instruction transfers [ Selectable src/dest ] src #IMM8 [ Flag Change ] ...

  • Page 145

    Chapter 3 Functions STZ [ Syntax ] STZ src,dest [ Operation ] then dest src [ Function ] • This instruction transfers [ Selectable src/dest ] src #IMM8 [ Flag Change ] ...

  • Page 146

    Chapter 3 Functions STZX [ Syntax ] STZX src1,src2,dest [ Operation ] then dest src1 else dest src2 [ Function ] • This instruction transfers dest . [ Selectable src/dest ] src #IMM8 [ Flag Change ...

  • Page 147

    Chapter 3 Functions SUB [ Syntax ] SUB.size (:format) src,dest [ Operation ] dest dest – src [ Function ] • This instruction subtracts dest • and the selected size specifier (.size) is (.B), src ...

  • Page 148

    Chapter 3 Functions [src/dest Classified by Format] G format src R0L/R0 R0H/R1 R1L/R2 A0/A0 *1 A1/A1 *1 [A0] dsp:8[A0] dsp:8[A1] dsp:8[SB] dsp:16[A0] dsp:16[A1] dsp:16[SB] dsp:20[A0] dsp:20[A1] abs20 R2R0 R3R1 A1A0 *1 If (.B) is selected as for the size specifier ...

  • Page 149

    Chapter 3 Functions TST [ Syntax ] TST.size src,dest [ Operation ] dest src [ Function ] • Each flag in the flag register changes state depending on the result of a logical AND of dest • ...

  • Page 150

    Chapter 3 Functions UND [ Syntax ] UND [ Operation ] SP SP – M(SP) ( – M(SP) ( M(FFFDC [ Function ] • This instruction generates an undefined instruction interrupt. • The undefined instruction ...

  • Page 151

    Chapter 3 Functions WAIT [ Syntax ] WAIT [ Operation ] [ Function ] • This instruction halts program execution. Program execution is restarted when an interrupt of a higher priority level than IPL is acknowledged or a reset is ...

  • Page 152

    Chapter 3 Functions XCHG [ Syntax ] XCHG.size src,dest [ Operation ] dest src [ Function ] • This instruction exchanges the contents of dest • and the selected size specifier (.size) is (.B), the ...

  • Page 153

    Chapter 3 Functions XOR [ Syntax ] XOR.size src,dest [ Operation ] dest dest src [ Function ] • This instruction exclusive ORs dest • and the selected size specifier (.size) is (.B), src operation ...

  • Page 154

    Chapter 3 Functions Rev.2.00 Oct 17, 2005 page 134 of 263 REJ09B0001-0200 This page intentionally left blank. 3.2 Functions ...

  • Page 155

    Instruction Codes/Number of Cycles 4.1 Guide to This Chapter 4.2 Instruction Codes/Number of Cycles Chapter 4 ...

  • Page 156

    Chapter 4 Instruction Codes 4.1 Guide to This Chapter This chapter lists the instruction code and number of cycles for each op-code. An example illustrating how to read this chapter is shown below. Chapter 4 Instruction Code (1) (1) LDIPL ...

  • Page 157

    Chapter 4 Instruction Codes (1) Mnemonic Shows the mnemonic explained in the page. (2) Syntax Shows an instruction syntax using symbols. (3) Instruction code Shows instruction code. Portions in parentheses ( ) may be omitted depending on the selected src/dest. ...

  • Page 158

    Chapter 4 Instruction Codes/Number of Cycles ABS (1) ABS.size dest SIZE 1 .size SIZE . [An] [ Number of Bytes/Number of Cycles ] dest Rn ...

  • Page 159

    Chapter 4 Instruction Codes/Number of Cycles (2) ADC.size src, dest SIZE .size SIZE . [An] [ Number of Bytes/Number of Cycles ] dest Rn An ...

  • Page 160

    Chapter 4 Instruction Codes/Number of Cycles ADCF (1) ADCF.size dest SIZE .size SIZE . [An] [ Number of Bytes/Number of Cycles ...

  • Page 161

    Chapter 4 Instruction Codes/Number of Cycles (2) ADD.size:Q #IMM, dest SIZE .size SIZE #IMM . [An] [ ...

  • Page 162

    Chapter 4 Instruction Codes/Number of Cycles ADD (3) ADD.B:S #IMM8, dest DEST dest R0H Rn R0L dsp:8[SB] dsp:8[SB/FB] dsp:8[FB] abs16 abs16 [ Number of Bytes/Number of Cycles ] dest Rn Bytes/Cycles 2/1 Rev.2.00 ...

  • Page 163

    Chapter 4 Instruction Codes/Number of Cycles (4) ADD.size:G src, dest SIZE .size SIZE . [An] [ Number of Bytes/Number of Cycles ] dest Rn An ...

  • Page 164

    Chapter 4 Instruction Codes/Number of Cycles ADD (5) ADD.B:S src, R0L/R0H DEST SRC src R0L/R0H Rn dsp:8[SB] dsp:8[SB/FB] dsp:8[FB] abs16 abs16 [ Number of Bytes/Number of Cycles ] src Rn Bytes/Cycles 1/2 ADD ...

  • Page 165

    Chapter 4 Instruction Codes/Number of Cycles (7) ADD.size:Q #IMM • The instruction code is the same regardless of whether (.B) or (.W) is selected as the size ...

  • Page 166

    Chapter 4 Instruction Codes/Number of Cycles ADJNZ (1) ADJNZ.size #IMM, dest, label SIZE dsp8 (label code) = address indicated by label – (start address of instruction + 2) .size SIZE ...

  • Page 167

    Chapter 4 Instruction Codes/Number of Cycles (1) AND.size:G #IMM, dest SIZE .size SIZE . [An] [ Number of Bytes/Number of Cycles ...

  • Page 168

    Chapter 4 Instruction Codes/Number of Cycles AND (3) AND.size:G src, dest SIZE .size SIZE . [An] [ Number of Bytes/Number of Cycles ] dest Rn ...

  • Page 169

    Chapter 4 Instruction Codes/Number of Cycles (4) AND.B:S src, R0L/R0H DEST SRC src Rn R0L/R0H dsp:8[SB] dsp:8[SB/FB] dsp:8[FB] abs16 abs16 [ Number of Bytes/Number of Cycles ] src Rn Bytes/Cycles 1/2 Rev.2.00 Oct ...

  • Page 170

    Chapter 4 Instruction Codes/Number of Cycles BAND (1) BAND src src bit,R0 bit,R1 bit,Rn bit,R2 bit,R3 bit,A0 bit,An bit,A1 [A0] [An] [A1] [ Number of ...

  • Page 171

    Chapter 4 Instruction Codes/Number of Cycles (2) BCLR:S bit, base:11[SB BIT [ Number of Bytes/Number of Cycles ] Bytes/Cycles 2/3 Rev.2.00 Oct 17, 2005 page 151 of 263 REJ09B0001-0200 4.2 dest code dsp8 ...

  • Page 172

    Chapter 4 Instruction Codes/Number of Cycles BM Cnd (1) BM Cnd dest dest bit,R0 bit,R1 bit,Rn bit,R2 bit,R3 bit,A0 bit,An bit,A1 [A0] [An] [A1] Cnd ...

  • Page 173

    Chapter 4 Instruction Codes/Number of Cycles (2) BM Cnd Cnd CND Cnd GEU GTU ...

  • Page 174

    Chapter 4 Instruction Codes/Number of Cycles BNOR (1) BNOR src src bit,R0 bit,R1 bit,Rn bit,R2 bit,R3 bit,A0 bit,An bit,A1 [A0] [An] [A1] [ Number of ...

  • Page 175

    Chapter 4 Instruction Codes/Number of Cycles (2) BNOT:S bit, base:11[SB BIT [ Number of Bytes/Number of Cycles ] Bytes/Cycles 2/3 (1) BNTST src ...

  • Page 176

    Chapter 4 Instruction Codes/Number of Cycles BNXOR (1) BNXOR src src bit,R0 bit,R1 bit,Rn bit,R2 bit,R3 bit,A0 bit,An bit,A1 [A0] [An] [A1] [ Number of Bytes/Number of Cycles ...

  • Page 177

    Chapter 4 Instruction Codes/Number of Cycles (1) BRK Number of Bytes/Number of Cycles ] Bytes/Cycles 1/27 • If the target address of the BRK interrupt is specified using the ...

  • Page 178

    Chapter 4 Instruction Codes/Number of Cycles BSET (2) BSET:S bit, base:11[SB BIT [ Number of Bytes/Number of Cycles ] Bytes/Cycles 2/3 BTST (1) BTST:G src ...

  • Page 179

    Chapter 4 Instruction Codes/Number of Cycles (2) BTST:S bit, base:11[SB BIT [ Number of Bytes/Number of Cycles ] Bytes/Cycles 2/3 (1) BTSTC dest ...

  • Page 180

    Chapter 4 Instruction Codes/Number of Cycles BTSTS (1) BTSTS dest dest bit,R0 bit,R1 bit,Rn bit,R2 bit,R3 bit,A0 bit,An bit,A1 [A0] [An] [A1] [ Number of ...

  • Page 181

    Chapter 4 Instruction Codes/Number of Cycles (1) CMP.size:G #IMM, dest SIZE .size SIZE . [An] [ Number of Bytes/Number of Cycles ...

  • Page 182

    Chapter 4 Instruction Codes/Number of Cycles CMP (2) CMP.size:Q #IMM, dest SIZE .size SIZE #IMM . [An] ...

  • Page 183

    Chapter 4 Instruction Codes/Number of Cycles (3) CMP.B:S #IMM8, dest DEST dest R0H Rn R0L dsp:8[SB] dsp:8[SB/FB] dsp:8[FB] abs16 abs16 [ Number of Bytes/Number of Cycles ] dest Rn Bytes/Cycles 2/1 Rev.2.00 Oct ...

  • Page 184

    Chapter 4 Instruction Codes/Number of Cycles CMP (4) CMP.size:G src, dest SIZE .size SIZE . [An] [ Number of Bytes/Number of Cycles ] dest Rn ...

  • Page 185

    Chapter 4 Instruction Codes/Number of Cycles (5) CMP.B:S src, R0L/R0H DEST SRC src Rn R0L/R0H dsp:8[SB] dsp:8[SB/FB] dsp:8[FB] abs16 abs16 [ Number of Bytes/Number of Cycles ] src Rn Bytes/Cycles 1/2 (1) DADC.B ...

  • Page 186

    Chapter 4 Instruction Codes/Number of Cycles DADC (2) DADC.W #IMM16 Number of Bytes/Number of Cycles ] Bytes/Cycles 4/5 DADC ...

  • Page 187

    Chapter 4 Instruction Codes/Number of Cycles (4) DADC.W R1 Number of Bytes/Number of Cycles ] Bytes/Cycles 2/5 (1) DADD.B ...

  • Page 188

    Chapter 4 Instruction Codes/Number of Cycles DADD (2) DADD.W #IMM16 Number of Bytes/Number of Cycles ] Bytes/Cycles 4/5 DADD ...

  • Page 189

    Chapter 4 Instruction Codes/Number of Cycles (4) DADD.W R1 Number of Bytes/Number of Cycles ] Bytes/Cycles 2/5 (1) DEC.B ...

  • Page 190

    Chapter 4 Instruction Codes/Number of Cycles DEC (2) DEC.W dest DEST dest DEST Number of Bytes/Number of Cycles ] Bytes/Cycles 1/1 DIV (1) DIV.size #IMM b7 ...

  • Page 191

    Chapter 4 Instruction Codes/Number of Cycles (2) DIV.size src SIZE .size SIZE . [An] [ Number of Bytes/Number of Cycles ] ...

  • Page 192

    Chapter 4 Instruction Codes/Number of Cycles DIVU (2) DIVU.size src SIZE 1 1 .size SIZE . [An] [ Number of Bytes/Number of Cycles ] src ...

  • Page 193

    Chapter 4 Instruction Codes/Number of Cycles (2) DIVX.size src SIZE .size SIZE . [An] [ Number of Bytes/Number of Cycles ] ...

  • Page 194

    Chapter 4 Instruction Codes/Number of Cycles DSBB (2) DSBB.W #IMM16 Number of Bytes/Number of Cycles ] Bytes/Cycles 4/4 DSBB (3) DSBB.B R0H, R0L ...

  • Page 195

    Chapter 4 Instruction Codes/Number of Cycles (4) DSBB.W R1 Number of Bytes/Number of Cycles ] Bytes/Cycles 2/4 (1) DSUB.B ...

  • Page 196

    Chapter 4 Instruction Codes/Number of Cycles DSUB (2) DSUB.W #IMM16 Number of Bytes/Number of Cycles ] Bytes/Cycles 4/4 DSUB (3) DSUB.B R0H, R0L ...

  • Page 197

    Chapter 4 Instruction Codes/Number of Cycles (4) DSUB.W R1 Number of Bytes/Number of Cycles ] Bytes/Cycles 2/4 (1) ENTER ...

  • Page 198

    Chapter 4 Instruction Codes/Number of Cycles EXITD (1) EXITD Number of Bytes/Number of Cycles ] Bytes/Cycles 2/9 EXTS (1) EXTS.B dest ...

  • Page 199

    Chapter 4 Instruction Codes/Number of Cycles (2) EXTS Number of Bytes/Number of Cycles ] Bytes/Cycles 2/3 (1) FCLR dest ...

  • Page 200

    Chapter 4 Instruction Codes/Number of Cycles FSET (1) FSET dest dest DEST ...