R5F21256SNFP#U0 Renesas Electronics America, R5F21256SNFP#U0 Datasheet - Page 106

• Manufacturer Part Number: R5F21256SNFP#U0
• Description: IC R8C MCU FLASH 32K 52LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/2x/25r

Specifications of R5F21256SNFP#U0

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, Voltage Detect, WDT
• Number Of I /o: 41
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 52-LQFP
• For Use With: R0K521256S000BE - KIT EVAL STARTER FOR R8C/25
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Rev.2.00 Oct 17, 2005
REJ09B0001-0200
LDCTX
[ Syntax ]
[ Function ]
[ Flag Change ]
[ Description Example ]
[ Related Instructions ]
Change
Chapter 3
LDCTX
Flag
• The table data is configured as shown below. The address indicated by abs20 is the base address of
• This instruction restores task context from the stack area.
• Set the RAM address that contains the task number in abs16 and the start address of table data in abs20.
• The required register information is specified from table data by the task number and the data in the
• Information on transferred registers is configured as shown below. Logical 1 indicates a register to be
LDCTX
abs20
the table. The data stored at an address twice the content of abs16 away from the base address
indicates register information, and the next address contains the stack pointer correction value.
stack area is transferred to each register according to the specified register information. Then the SP
correction value is added to the stack pointer (SP). For this SP correction value, set the number of
bytes to be transferred.
transferred and logical 0 indicates a register that is not transferred.
U
I
Direction in
which address
increases
Base address
of table
abs16,abs20
Ram,Rom_TBL
Functions
O
page 86 of 263
B
S
STCTX
*1
Z
Register information for task with task number n
SP correction value for task with task number n
Register information for task with task number 0. (See above diagram.)
Register information for task with task number 1. (See above diagram.)
SP correction value for task with task number 0. (See above diagram.)
SP correction value for task with task number 1. (See above diagram.)
MSB
D
n=0 to 255
FB SB A1 A0 R3 R2 R1 R0
C
Transferred sequentially
beginning with R0
LoaD ConTeXt
Restore context
[ Instruction Code/Number of Cycles ]
LSB
*1
*1
. (See above diagram.)
. (See above diagram.)
LDCTX
3.2 Functions
Page: 189
abs16 2