R5F21256SNFP#U0 Renesas Electronics America, R5F21256SNFP#U0 Datasheet - Page 111

• Manufacturer Part Number: R5F21256SNFP#U0
• Description: IC R8C MCU FLASH 32K 52LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/2x/25r

Specifications of R5F21256SNFP#U0

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, Voltage Detect, WDT
• Number Of I /o: 41
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 52-LQFP
• For Use With: R0K521256S000BE - KIT EVAL STARTER FOR R8C/25
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Rev.2.00 Oct 17, 2005
REJ09B0001-0200
[src/dest Classified by Format]
Chapter 3 Functions
*1 If (.B) is selected as the size specifier (.size), A0 or A1 cannot be chosen for
*2 If
*3 The operation is performed on the stack pointer indicated by the U flag. dsp:8 [SP] cannot be chosen
*4 The acceptable range of values is –8 < #IMM < +7.
*5 Only (.B) can be selected as the size specifier (.size).
*6 The same register cannot be chosen for
*7 If
*8 If
*9 (.B) or (.W) can be selected as the size specifier (.size).
R0L/R0
A0/A0
dsp:8[A0]
dsp:16[A0] dsp:16[A1]
dsp:20[A0] dsp:20[A1]
R2R0
R0L/R0
A0/A0
dsp:8[A0]
dsp:16[A0] dsp:16[A1]
dsp:20[A0] dsp:20[A1]
R2R0
R0L
abs16
R0L
abs16
R0L
abs16
R0L
abs16
G format
Q format
S format
Z format
neously.
for
*5*6*7
*5*6
src
src
src
*1
*5
src
is #IMM, dsp:8 [SP] cannot be chosen for
is R0L, only A1 can be selected for
is R0H, only A0 can be selected for
and
R0H/R1
A1/A1
dsp:8[A1]
R3R1
R0H/R1
A1/A1
dsp:8[A1]
R3R1
R0H
#IMM
R0H
#IMM
R0H
#IMM
R0H
#0
dest
*5*6*8
*5*6
*9
*1
page 91 of 263
simultaneously.
src
src
src
src
R1L/R2
[A0]
dsp:8[SB]
dsp:16[SB]
abs20
A1A0
R1L/R2
[A0]
dsp:8[SB]
dsp:16[SB]
abs20
A1A0
dsp:8[SB]
dsp:8[SB]
dsp:8[SB]
dsp:8[SB]
*5
dsp:8[FB]
R1H/R3
[A1]
dsp:8[FB] dsp:8[A0]
abs16
#IMM
dsp:8[SP]
R1H/R3
[A1]
dsp:8[FB]
abs16
#IMM
dsp:8[FB]
dsp:8[FB]
dsp:8[FB]
src
*2
*4
dest
dest
*3
and
*5
R0L/R0
A0/A0
dsp:16[A0] dsp:16[A1] dsp:16[SB] abs16
dsp:20[A0] dsp:20[A1] abs20
R2R0
as the address register.
R0L/R0
A0/A0
dsp:8[A0]
dsp:16[A0] dsp:16[A1] dsp:16[SB] abs16
dsp:20[A0] dsp:20[A1] abs20
R2R0
R0L
abs16
R0L
abs16
R0L
abs16
R0L
abs16
as the address register.
dest
dest
*5*6
*5*6
*5
.
*1
*5
*5
.
R0H/R1
A1/A1
dsp:8[A1]
R3R1
R0H/R1
A1/A1
dsp:8[A1]
R3R1
R0H
A0
R0H
A0
R0H
A0
R0H
A0
*5*8
*9
*5*6
*5*6
*5
*1
dest
dest
dest
dest
R1L/R2
[A0]
dsp:8[SB]
A1A0
R1L/R2
[A0]
dsp:8[SB]
A1A0
dsp:8[SB]
A1
dsp:8[SB]
A1
dsp:8[SB]
A1
dsp:8[SB]
A1
*5*7
*9
src
*5
*5
and
R1H/R3
[A1]
dsp:8[FB]
SP/SP
dsp:8[SP]
R1H/R3
SP/SP
dsp:8[FB]
dsp:8[FB]
dsp:8[FB]
dsp:8[FB]
[A1]
dsp:8[FB]
3.2 Functions
dest
simulta-
*2*3
*5
*5