R5F21256SNFP#U0 Renesas Electronics America, R5F21256SNFP#U0 Datasheet - Page 268

• Manufacturer Part Number: R5F21256SNFP#U0
• Description: IC R8C MCU FLASH 32K 52LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/2x/25r

Specifications of R5F21256SNFP#U0

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, Voltage Detect, WDT
• Number Of I /o: 41
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 52-LQFP
• For Use With: R0K521256S000BE - KIT EVAL STARTER FOR R8C/25
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Rev.2.00 Oct 17, 2005
REJ09B0001-0200
Chapter 5
5.1.3 Hardware Interrupts
There are two types in hardware interrupts: special interrupts and peripheral function interrupts.
Special interrupts are nonmaskable.
(1) Watchdog timer interrupt
(2) Oscillation stop detection interrupt
(3) Single-step interrupt
(4) Address-match interrupt
These interrupts are generated by the peripheral functions built into the microcomputer. Peripheral func-
tion interrupts are maskable.
The types of built-in peripheral functions vary with each R8C model, as do the interrupt sources. For
details about peripheral function interrupts, refer to the R8C’s hardware manual.
Special interrupts
Peripheral function interrupts
This interrupt is caused by the watchdog timer. Initialize the watchdog timer after the watchdog timer
interrupt is generated. For details about the watchdog timer, refer to the R8C’s hardware manual.
This interrupt is caused by the oscillation stop detection function. For details about the oscillation stop
detection function, refer to the R8C’s hardware manual.
This interrupt is used exclusively by development support tools. Do not use this interrupt.
When the AIER0 or AIER1 bit in the AIER register is set to 1 (address-match interrupt enabled), the
address-match interrupt is generated just before executing the instruction of the address indicated by
the corresponding RMAD0 to RMAD1 register.
Interrupts
page 248 of 263
5.1 Outline of Interrupt