R5F21256SNFP#U0 Renesas Electronics America, R5F21256SNFP#U0 Datasheet - Page 271

• Manufacturer Part Number: R5F21256SNFP#U0
• Description: IC R8C MCU FLASH 32K 52LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/2x/25r

Specifications of R5F21256SNFP#U0

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, Voltage Detect, WDT
• Number Of I /o: 41
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 52-LQFP
• For Use With: R0K521256S000BE - KIT EVAL STARTER FOR R8C/25
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Rev.2.00 Oct 17, 2005
REJ09B0001-0200
Chapter 5
5.2.4 Changing Interrupt Control Registers
(1) Individual interrupt control registers can only be modified while no interrupt requests corresponding
(2) When modifying an interrupt control register after disabling interrupts, care must be taken when
Changing Bits Other Than IR Bit
If an interrupt request corresponding to the register is generated while executing the instruction, the IR
bit may not be set to 1 (interrupt requested), with the result that the interrupt request is ignored. To get
around this problem, use the following instructions to modify the register: AND, OR, BCLR, BSET.
Changing IR Bit
Even when the IR bit is cleared to 0 (interrupt not requested), it may not actually be cleared to 0 depend-
ing on the instruction used. Therefore, use the MOV instruction to set the IR bit to 0.
(3) When disabling interrupts using the I flag, refer to the following sample programs. (Refer to (2) above
Sample programs 1 to 3 are to prevent the I flag from being set to 1 (interrupt enabled) before writing to
the interrupt control registers depending on the state of the internal bus or the instruction queue buffer.
to that register are generated. If interrupt requests managed by the interrupt control register are
likely to occur, disable interrupts before changing the contents of the interrupt control register.
selecting the instructions to be used.
regarding changing interrupt control registers in the sample programs.)
Example 1: Use NOP instruction to prevent I flag being set to 1
Example 2: Use dummy read to delay FSET instruction
Example 3: Use POPC instruction to change I flag
INT_SWITCH1:
INT_SWITCH2:
INT_SWITCH3:
Interrupts
FCLR
AND.B
NOP
NOP
FSET
FCLR
AND.B
MOV.W MEM, R0
FSET
PUSHC FLG
FCLR
AND.B
POPC
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before interrupt control register is changed
I
#00H, 0056H ; Set TXIC register to 00
I
I
#00H, 0056H ; Set TXIC register to 00
I
I
#00H, 0056H ; Set TXIC register to 00
FLG
; Disable interrupts
; Enable interrupts
; Disable interrupts
; Dummy read
; Enable interrupts
; Disable interrupts
; Enable interrupts
16
16
16
5.2 Interrupt Control