R5F21256SNFP#U0 Renesas Electronics America, R5F21256SNFP#U0 Datasheet - Page 282

• Manufacturer Part Number: R5F21256SNFP#U0
• Description: IC R8C MCU FLASH 32K 52LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/2x/25r

Specifications of R5F21256SNFP#U0

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, Voltage Detect, WDT
• Number Of I /o: 41
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 52-LQFP
• For Use With: R0K521256S000BE - KIT EVAL STARTER FOR R8C/25
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Rev.2.00 Oct 17, 2005
REJ09B0001-0200
6.1 Instruction Queue Buffer
Chapter 6
R8C/Tiny Series microcomputers have 4-stage (4-byte) instruction queue buffers. If the instruction queue
buffer has free space when the CPU can use the bus, instruction codes are taken into the instruction queue
buffer. This is referred to as “prefetching”. The CPU reads (fetches) the instruction codes from the instruc-
tion queue buffer as it executes a program.
The explanation of the number of cycles in chapter 4 assumes that all the necessary instruction codes are
placed in the instruction queue buffer, and that 8-bit data is read or written to the memory without software
wait states. In the following cases, more cycles may be needed than the number of cycles indicated in this
manual:
Note that if prefetch and data access occur at the same time, data access has priority. Also, if more than
three bytes of instruction codes exist in the instruction queue buffer, the CPU assumes there is no free
space and, therefore, does not prefetch instruction code.
Figure 6.1.1 shows an example of starting a read instruction (without software wait).
• If not all of the instruction codes needed by the CPU have been placed in the instruction queue buffer.
• When reading or writing data to an area in which software wait cycles exist.
• When reading or writing 16-bit data from/to the SFR or the internal memory.
Instruction codes are read in until all of the instruction codes required for program execution are avail-
able. Furthermore, the number of read cycles increases in the following case:
The number of read or write cycles increases to match the number of wait cycles incurred.
The memory is accessed twice to read or write one 16-bit data item. Therefore, the number of read or
write cycles increases by one for each 16-bit data item read or written.
(1) The number of read cycles increases to match the number of wait cycles incurred when reading
instruction codes from an area in which software wait cycles exist.
Calculating the Number of Cycles
page 262 of 263
6.1 Instruction Queue Buffer