R5F21256SNFP#U0 Renesas Electronics America, R5F21256SNFP#U0 Datasheet - Page 88

• Manufacturer Part Number: R5F21256SNFP#U0
• Description: IC R8C MCU FLASH 32K 52LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/2x/25r

Specifications of R5F21256SNFP#U0

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, Voltage Detect, WDT
• Number Of I /o: 41
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 52-LQFP
• For Use With: R0K521256S000BE - KIT EVAL STARTER FOR R8C/25
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Rev.2.00 Oct 17, 2005
REJ09B0001-0200
DIVU
[ Syntax ]
[ Operation ]
[ Function ]
[ Selectable src ]
[ Flag Change ]
[ Description Example ]
[ Related Instructions ]
Chapter 3
Change
Conditions
R0L/R0
A0/A0
dsp:8[A0]
dsp:16[A0] dsp:16[A1]
dsp:20[A0] dsp:20[A1]
R2R0
DIVU.size
If the size specifier (.size) is (.B)
If the size specifier (.size) is (.W)
Flag
O :
DIVU.B
DIVU.B
DIVU.W
• This instruction divides R2R0 (R0)
• If
• If (.B) is selected as the size specifier (.size), the O flag is set when the operation results in a quotient
• If (.W) is selected as the size specifier (.size), the O flag is set when the operation results in a quotient
(R0L)
registers that are the object of the operation when (.B) is selected as the size specifier (.size).
order bits of A0 or A1.
exceeding 8 bits or the divisor is 0. In this case, R0L and R0H are undefined.
exceeding 16 bits or the divisor is 0. In this case, R0 and R2 are undefined.
src
U
R0L (quotient), R0H (remainder)
R0 (quotient), R2 (remainder)
The flag is set when the operation results in a quotient exceeding 16 bits (.W) or 8 bits (.B) or the
divisor is 0; otherwise cleared.
*1
is A0 or A1 and the selected size specifier (.size) is (.B), the operation is performed on the 8 low-
R0H/R1
A1/A1
dsp:8[A1]
R3R1
and the remainder in R2 (R0H)
I
Functions
src
A0
#4
R0
O
page 68 of 263
B
src
R1L/R2
[A0]
dsp:8[SB]
dsp:16[SB]
abs20
A1A0
S
DIV, DIVX, MUL, MULU
Z
D
R1H/R3
[A1]
dsp:8[FB]
abs16
#IMM
C
*1
R2R0
DIVide Unsigned
B , W
Unsigned divide
by the unsigned value of
R0
*1
. Items in parentheses and followed by
src
src
;Value of 8 low-order bits of A0 is the divisor.
[ Instruction Code/Number of Cycles ]
src
and stores the quotient in R0
“*1”
3.2 Functions
( )
DIVU
Page: 171
*1
indicate