R5F21272SDFP#U0 Renesas Electronics America, R5F21272SDFP#U0 Datasheet - Page 272

• Manufacturer Part Number: R5F21272SDFP#U0
• Description: IC R8C/27 MCU FLASH 32LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/2x/27r

Specifications of R5F21272SDFP#U0

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: LED, POR, Voltage Detect, WDT
• Number Of I /o: 25
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-LQFP
• For Use With: R0K521276S000BE - KIT DEV RSK-R8C/26-29R0E521000EPB00 - PROBE EMULATOR FOR PC7501
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/26 Group, R8C/27 Group
Rev.2.10
REJ09B0278-0210
15.2
Table 15.4
i = 0 or 1
NOTE:
Transfer data formats
Transfer clocks
Transmit start conditions
Receive start conditions
Interrupt request
generation timing
Error detection
The UART mode allows data transmission and reception after setting the desired bit rate and transfer data format.
Table 15.4 lists the Specifications of UART Mode. Table 15.5 lists the Registers Used and Settings for UART
Mode.
1. If an overrun error occurs, the receive data (b0 to b8) of the UiRB register will be undefined. The IR
bit in the SiRIC register remains unchanged.
Clock Asynchronous Serial I/O (UART) Mode
Sep 26, 2008
Item
Specifications of UART Mode
Page 253 of 453
• Character bit (transfer data): Selectable among 7, 8 or 9 bits
• Start bit: 1 bit
• Parity bit: Selectable among odd, even, or none
• Stop bit: Selectable among 1 or 2 bits
• CKDIR bit in UiMR register is set to 0 (internal clock): fj/(16(n+1))
• CKDIR bit is set to 1 (external clock): fEXT/(16(n+1))
• Before transmission starts, the following are required
• Before reception starts, the following are required
• When transmitting, one of the following conditions can be selected
• When receiving
• Overrun error
• Framing error
• Parity error
• Error sum flag
fj = f1, f8, f32 n = value set in UiBRG register: 00h to FFh
fEXT: Input from CLKi pin, n = value set in UiBRG register: 00h to FFh
- TE bit in UiC1 register is set to 1 (transmission enabled)
- TI bit in UiC1 register is set to 0 (data in UiTB register)
- RE bit in UiC1 register is set to 1 (reception enabled)
- Start bit detected
- UiIRS bit is set to 0 (transmit buffer empty):
- UiIRS bit is set to 1 (transfer ends):
When transferring data from the UARTi receive register to UiRB register
(when receive ends).
This error occurs if the serial interface starts receiving the next data item
before reading the UiRB register and receive the bit preceding the final
stop bit of the next data item.
This error occurs when the set number of stop bits is not detected.
This error occurs when parity is enabled, and the number of 1’s in parity
and character bits do not match the number of 1’s set.
This flag is set is set to 1 when an overrun, framing, or parity error is
generated.
When transferring data from the UiTB register to UARTi transmit register
(when transmit starts).
When serial interfac.e completes transmitting data from the UARTi
transmit register
(1)
Specification
15. Serial Interface