R5F21272SDFP#U0 Renesas Electronics America, R5F21272SDFP#U0 Datasheet - Page 299

IC R8C/27 MCU FLASH 32LQFP

R5F21272SDFP#U0

Manufacturer Part Number
R5F21272SDFP#U0
Description
IC R8C/27 MCU FLASH 32LQFP
Manufacturer
Renesas Electronics America
Series
R8C/2x/27r
Datasheet

Specifications of R5F21272SDFP#U0

Core Processor
R8C
Core Size
16/32-Bit
Speed
20MHz
Connectivity
I²C, LIN, SIO, SSU, UART/USART
Peripherals
LED, POR, Voltage Detect, WDT
Number Of I /o
25
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2.2 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
32-LQFP
For Use With
R0K521276S000BE - KIT DEV RSK-R8C/26-29R0E521000EPB00 - PROBE EMULATOR FOR PC7501
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

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Manufacturer:
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Manufacturer:
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R8C/26 Group, R8C/27 Group
Rev.2.10
REJ09B0278-0210
16.2.5.4
Data transmission/reception is an operation combining data transmission and reception which were described
earlier. Transmission/reception is started by writing data to the SSTDR register.
When the 8th clock rises or the ORER bit is set to 1 (overrun error) while the TDRE bit is set to 1 (data is
transferred from registers SSTDR to SSTRSR), the transmit/receive operation is stopped.
When switching from transmit mode (TE = 1) or receive mode (RE = 1) to transmit/receive mode (Te = RE =
1), set the TE bit to 0 and RE bit to 0 before switching. After confirming that the TEND bit is set to 0 (the
TDRE bit is set to 0 when the last bit of the transmit data is transmitted), the RDRF bit is set to 0 (no data in the
SSRDR register), and the ORER bit is set to 0 (no overrun error), set bits TE and RE to 1.
Figure 16.17 shows a Sample Flowchart for Data Transmission/Reception (Clock Synchronous Communication
Mode).
When exiting transmit/receive mode after this mode is used (TE = RE = 1), a clock may be output if
transmit/receive mode is exited after reading the SSRDR register. To avoid any clock outputs, perform either of
the following:
- First set the RE bit to 0, and then set the TE bit to 0.
- Set bits TE and RE at the same time.
When subsequently switching to receive mode (TE = 0 and RE = 1), first set the SRES bit to 1, and set this bit
to 0 to reset the clock synchronous serial interface control unit and the SSTRSR register. Then, set the RE bit to
1.
Sep 26, 2008
Data Transmission/Reception
Page 280 of 453
16. Clock Synchronous Serial Interface

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