R5F21272SDFP#U0 Renesas Electronics America, R5F21272SDFP#U0 Datasheet - Page 68

IC R8C/27 MCU FLASH 32LQFP

R5F21272SDFP#U0

Manufacturer Part Number
R5F21272SDFP#U0
Description
IC R8C/27 MCU FLASH 32LQFP
Manufacturer
Renesas Electronics America
Series
R8C/2x/27r
Datasheet

Specifications of R5F21272SDFP#U0

Core Processor
R8C
Core Size
16/32-Bit
Speed
20MHz
Connectivity
I²C, LIN, SIO, SSU, UART/USART
Peripherals
LED, POR, Voltage Detect, WDT
Number Of I /o
25
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2.2 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
32-LQFP
For Use With
R0K521276S000BE - KIT DEV RSK-R8C/26-29R0E521000EPB00 - PROBE EMULATOR FOR PC7501
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

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R8C/26 Group, R8C/27 Group
Rev.2.10
REJ09B0278-0210
6.4
Figure 6.15
Table 6.5
NOTE:
Table 6.5 lists the Procedure for Setting Bits Associated with Voltage Monitor 1 Reset. Figure 6.15 shows an
Example of Voltage Monitor 1 Reset Operation (J, K Version). To use the voltage monitor 1 reset to exit stop mode,
set the VW1C1 bit in the VW1C register to 1 (digital filter disabled).
1. When the VW1C0 bit is set to 0, steps 3, 4, and 5 can be executed simultaneously (with 1
When the VW1C1 bit is set
to 0 (digital filter enabled)
When the VW1C1 bit is set
to 1 (digital filter disabled)
and the VW1C7 bit is set
to 1
Step
4
5
1
2
3
6
7
8
9
(1)
(1)
instruction).
Voltage Monitor 1 Reset (J, K Version)
VW1C1 and VW1C7: Bits in VW1C register
Sep 26, 2008
Procedure for Setting Bits Associated with Voltage Monitor 1 Reset
Set the VCA26 bit in the VCA2 register to 1 (voltage detection 1 circuit enabled)
Wait for td(E-A)
Select the sampling clock of the digital filter
by the VW1F0 to VW1F1 bits in the VW1C
register
Set the VW1C1 bit in the VW1C register to 0
(digital filter enabled)
Set the VW1C6 bit in the VW1C register to 1 (voltage monitor 1 reset mode)
Set the VW1C2 bit in the VW1C register to 0
Set the CM14 bit in the CM1 register to 0
(low-speed on-chip oscillator on)
Wait for 4 cycles of the sampling clock of the
digital filter
Set the VW1C0 bit in the VW1C register to 1 (voltage monitor 1 reset enabled)
Example of Voltage Monitor 1 Reset Operation (J, K Version)
Internal reset signal
Internal reset signal
The above applies under the following conditions.
• VCA26 bit in VCA2 register = 1 (voltage detection 1 circuit enabled)
• VW1C0 bit in VW1C register = 1 (voltage monitor 1 reset enabled)
• VW1C6 bit in VW1C register = 1 (voltage monitor 1 reset mode)
When the internal reset signal is held “L”, the pins, CPU and SFR are reset.
The internal reset signal level changes from “L” to “H”, and a program is executed beginning with the address indicated by
the reset vector.
Refer to 4. Special Function Registers (SFRs) for the SFR status after reset.
Page 49 of 453
When Using Digital Filter
Vdet1
VCC
Sampling clock of
digital filter × 4 cycles
Set the VW1C7 bit in the VW1C register to 1
Set the VW1C1 bit in the VW1C register to 1
(digital filter disabled)
− (No wait time required)
When Not Using Digital Filter
6. Voltage Detection Circuit
fOCO-S
fOCO-S
1
1
× 32
× 32

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