C8051F361-GQ Silicon Laboratories Inc, C8051F361-GQ Datasheet

IC 8051 MCU 32K FLASH 32LQFP

C8051F361-GQ

Manufacturer Part Number
C8051F361-GQ
Description
IC 8051 MCU 32K FLASH 32LQFP
Manufacturer
Silicon Laboratories Inc
Series
C8051F36xr
Datasheets

Specifications of C8051F361-GQ

Program Memory Type
FLASH
Program Memory Size
32KB (32K x 8)
Package / Case
32-LQFP
Core Processor
8051
Core Size
8-Bit
Speed
100MHz
Connectivity
SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
POR, PWM, Temp Sensor, WDT
Number Of I /o
29
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 21x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
C8051F3x
Core
8051
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
I2C/SMBus/SPI/UART
Maximum Clock Frequency
100 MHz
Number Of Programmable I/os
29
Number Of Timers
4
Operating Supply Voltage
3 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
KSK-SL-TOOLSTICK, PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F360DK
Minimum Operating Temperature
- 40 C
On-chip Adc
21-ch x 10-bit
On-chip Dac
1-ch x 10-bit
Package
32LQFP
Device Core
8051
Family Name
C8051F36x
Maximum Speed
100 MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
770-1006 - ISP 4PORT FOR SILABS C8051F MCU336-1410 - KIT DEV FOR C8051F360 FAMILY
Eeprom Size
-
Lead Free Status / Rohs Status
 Details
Other names
336-1408

Available stocks

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Price
Part Number:
C8051F361-GQ
Manufacturer:
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Quantity:
295
Part Number:
C8051F361-GQ
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
Part Number:
C8051F361-GQR
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Quantity:
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Part Number:
C8051F361-GQR
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
Part Number:
C8051F361-GQR
Manufacturer:
SILICON
Quantity:
7 942
Rev. 1.0 7/07
Analog Peripherals
-
-
-
-
On-Chip Debug
-
-
-
-
Supply Voltage
-
-
High Speed 8051 µC Core
-
-
-
-
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
10-Bit ADC (‘F360/1/2/6/7/8/9 only)
10-Bit Current Output DAC
(‘F360/1/2/6/7/8/9 only)
Two Comparators
Brown-out detector and POR Circuitry
On-chip debug circuitry facilitates full speed, non-
intrusive in-system debug (no emulator required)
Provides breakpoints, single stepping,
inspect/modify memory and registers
Superior performance to emulation systems using
ICE-chips, target pods, and sockets
Low cost, complete development kit
Range: 2.7–3.6 V (50 MIPS) 3.0–3.6 V (100 MIPS)
Power saving suspend and shutdown modes
Pipelined instruction architecture; executes 70% of
instructions in 1 or 2 system clocks
100 MIPS or 50 MIPS throughput with on-chip PLL
Expanded interrupt handler
2-cycle 16 x 16 MAC engine
Up to 200 ksps
Up to 21 external single-ended or differential inputs
VREF from internal VREF, external pin or V
Internal or external start of conversion source
Built-in temperature sensor
Programmable hysteresis and response time
Configurable as interrupt or reset source
Low current (0.4 µA)
‘F360/1/2/6/7/8/9 only
M
A
U
X
INTERRUPTS
WDT
FLEXIBLE
COMPARATORS
PERIPHERALS
200 ksps
VOLTAGE
ANALOG
Copyright © 2007 by Silicon Laboratories
HIGH-SPEED CONTROLLER CORE
10-bit
16 x 16
ADC
MAC
CIRCUITRY
+
-
Current
DD
DEBUG
SENSOR
10-bit
TEMP
DAC
+
-
(100 or 50 MIPS)
C8051F360/1/2/3/4/5/6/7/8/9
8051 CPU
Internal Oscillator/
Memory
-
-
Digital Peripherals
-
-
-
-
-
-
Clock Sources
-
-
-
-
Packages
-
-
-
Temperature Range: –40 to +85 °C
Timer 0
Timer 1
Timer 2
Timer 3
48-pin only
SMBus
UART
PCA
LFO/PLL
SPI
1280 bytes internal data RAM (256 + 1024)
32 kB (‘F360/1/2/3/4/5/6/7) or 16 kB (‘F368/9) Flash;
In-system programmable in 1024-byte Sectors—
1024 bytes are reserved in the 32 kB devices
up to 39 Port I/O; All 5 V tolerant with high sink cur-
rent
Hardware enhanced UART, SMBus™, and
enhanced SPI™ serial ports
Four general purpose 16-bit counter/timers
16-Bit programmable counter array (PCA) with six
capture/compare modules
Real time clock mode using PCA or timer and exter-
nal clock source
External Memory Interface (EMIF)
Two internal oscillators:
Flexible PLL technology
External oscillator: Crystal, RC, C, or clock
(1 or 2 pin modes)
Can switch between clock sources on-the-fly; useful
in power saving modes
48-pin TQFP (C8051F360/3)
32-pin LQFP (C8051F361/4/6/8)
28-pin QFN (C8051F362/5/7/9)
DIGITAL I/O
Mixed Signal ISP Flash MCU Family
24.5 MHz with ±2% accuracy supports crystal-less
UART operation
80/40/20/10 kHz low frequency, low power
1024 B
SRAM
ISP FLASH
32/16 kB
Port 0
Port 1
Port 2
Port 3
Port 3
Port 4
POR
C8051F36x

Related parts for C8051F361-GQ

C8051F361-GQ Summary of contents

Page 1

... Flexible PLL technology - External oscillator: Crystal, RC clock ( pin modes) - Can switch between clock sources on-the-fly; useful in power saving modes Packages - 48-pin TQFP (C8051F360/3) - 32-pin LQFP (C8051F361/4/6/8) - 28-pin QFN (C8051F362/5/7/9) Temperature Range: –40 to +85 °C ANALOG DIGITAL I/O PERIPHERALS UART + SMBus + VOLTAGE ...

Page 2

C8051F360/1/2/3/4/5/6/7/8/9 2 Rev. 1.0 ...

Page 3

Table of Contents 1. System Overview.................................................................................................... 18 1.1. CIP-51™ Microcontroller Core.......................................................................... 22 1.1.1. Fully 8051 Compatible.............................................................................. 22 1.1.2. Improved Throughput ............................................................................... 22 1.1.3. Additional Features .................................................................................. 23 1.2. On-Chip Memory............................................................................................... 24 1.3. On-Chip Debug Circuitry................................................................................... 24 1.4. Programmable Digital I/O ...

Page 4

C8051F360/1/2/3/4/5/6/7/8/9 9.4.3. General Purpose Registers ...................................................................... 87 9.4.4. Bit Addressable Locations........................................................................ 87 9.4.5. Stack ....................................................................................................... 87 9.4.6. Special Function Registers....................................................................... 88 9.4.7. Register Descriptions ............................................................................. 102 9.5. Power Management Modes ............................................................................ 104 9.5.1. Idle Mode................................................................................................ 105 9.5.2. Stop Mode .............................................................................................. ...

Page 5

PSWE Maintenance .................................................................... 141 13.3.3.System Clock ......................................................................................... 141 13.4.Flash Read Timing ......................................................................................... 143 14. Branch Target Cache ........................................................................................... 145 14.1.Cache and Prefetch Operation ....................................................................... 145 14.2.Cache and Prefetch Optimization................................................................... 146 15. External Data Memory Interface and On-Chip XRAM........................................ 153 ...

Page 6

C8051F360/1/2/3/4/5/6/7/8/9 18.3.SMBus Operation ........................................................................................... 203 18.3.1.Arbitration............................................................................................... 204 18.3.2.Clock Low Extension.............................................................................. 204 18.3.3.SCL Low Timeout................................................................................... 204 18.3.4.SCL High (SMBus Free) Timeout .......................................................... 205 18.4.Using the SMBus............................................................................................ 205 18.4.1.SMBus Configuration Register............................................................... 206 18.4.2.SMB0CN Control Register ..................................................................... 209 18.4.3.Data Register ......................................................................................... 212 18.5.SMBus ...

Page 7

Programmable Counter Array ............................................................................. 264 22.1.PCA Counter/Timer ........................................................................................ 265 22.2.Capture/Compare Modules ............................................................................ 266 22.2.1.Edge-triggered Capture Mode................................................................ 267 22.2.2.Software Timer (Compare) Mode........................................................... 268 22.2.3.High Speed Output Mode....................................................................... 269 22.2.4.Frequency Output Mode ........................................................................ 270 22.2.5.8-Bit Pulse Width Modulator Mode......................................................... 271 22.2.6.16-Bit ...

Page 8

... C8051F360/1/2/3/4/5/6/7/8/9 List of Figures 1. System Overview Figure 1.1. C8051F360/3 Block Diagram ................................................................. 20 Figure 1.2. C8051F361/4/6/8 Block Diagram ........................................................... 21 Figure 1.3. C8051F362/5/7/9 Block Diagram ........................................................... 21 Figure 1.4. Comparison of Peak MCU Execution Speeds ....................................... 22 Figure 1.5. On-Chip Clock and Reset ......................................................................23 Figure 1.6. On-Board Memory Map ......................................................................... 24 Figure 1.7. Development/In-System Debug Diagram .............................................. 25 Figure 1 ...

Page 9

Figure 8.2. Comparator1 Functional Block Diagram ............................................... 71 Figure 8.3. Comparator Hysteresis Plot .................................................................. 72 9. CIP-51 Microcontroller Figure 9.1. CIP-51 Block Diagram .......................................................................... 81 Figure 9.2. Memory Map ......................................................................................... 86 Figure 9.3. SFR Page Stack .................................................................................... 89 Figure 9.4. ...

Page 10

C8051F360/1/2/3/4/5/6/7/8/9 18. SMBus Figure 18.1. SMBus Block Diagram ...................................................................... 202 Figure 18.2. Typical SMBus Configuration ............................................................ 203 Figure 18.3. SMBus Transaction ........................................................................... 204 Figure 18.4. Typical SMBus SCL Generation ........................................................ 207 Figure 18.5. Typical Master Transmitter Sequence ............................................... 213 Figure ...

Page 11

Figure 22.7. PCA Frequency Output Mode ........................................................... 270 Figure 22.8. PCA 8-Bit PWM Mode Diagram ........................................................ 271 Figure 22.9. PCA 16-Bit PWM Mode ..................................................................... 272 Figure 22.10. PCA Module 5 with Watchdog Timer Enabled ................................ 273 23. Revision Specific Behavior ...

Page 12

C8051F360/1/2/3/4/5/6/7/8/9 List of Tables 1. System Overview Table 1.1. Product Selection Guide ......................................................................... 19 2. Absolute Maximum Ratings Table 2.1. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . ...

Page 13

Port Input/Output Table 17.1. Port I/O DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 201 18. SMBus Table 18.1. SMBus ...

Page 14

C8051F360/1/2/3/4/5/6/7/8/9 List of Registers SFR Definition 5.1. AMX0P: AMUX0 Positive Channel Select . . . . . . . . . . . . . . . . . . . 54 SFR Definition 5.2. AMX0N: AMUX0 Negative Channel Select ...

Page 15

SFR Definition 11.6. MAC0BL: MAC0 B Low Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 SFR Definition 11.7. MAC0ACC3: ...

Page 16

C8051F360/1/2/3/4/5/6/7/8/9 SFR Definition 17.16. P2MDIN: Port2 Input Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 SFR Definition 17.17. P2MDOUT: ...

Page 17

C2 Register Definition 24.2. DEVICEID: C2 Device 284 C2 Register Definition 24.3. REVID: C2 Revision ...

Page 18

C8051F360/1/2/3/4/5/6/7/8/9 1. System Overview C8051F36x devices are fully integrated mixed-signal System-on-a-Chip MCUs. Highlighted features are listed below. Refer to Table 1.1 for specific product feature selection. • High-speed pipelined 8051-compatible microcontroller core (up to 100 MIPS) • In-system, full-speed, non-intrusive ...

Page 19

... Table 1.1. Product Selection Guide C8051F360-GQ 100 32 1024 100 32 1024 1 C8051F361-GQ 100 32 1024 2 C8051F362-GM C8051F363-GQ 100 32 1024 100 32 1024 1 C8051F364-GQ 2 100 32 1024 C8051F365- 1024 C8051F366- 1024 C8051F367- 1024 C8051F368- 1024 C8051F369-GM Notes: 1. Pin compatible with the C8051F310-GQ. 2. Pin compatible with the C8051F311-GM. ...

Page 20

C8051F360/1/2/3/4/5/6/7/8/9 C2D Debug / Programming Hardware C2CK/RST Reset CIP-51 8051 Controller Core Power-On Reset 32/16 kB ISP FLASH Supply Program Memory Monitor VDD 256 Byte RAM Power Net 1 kB XRAM GND 2-cycle Multiply and Accumulate System ...

Page 21

... Multiply and Accumulate System Clock Setup XTAL1 External XTAL2 Oscillator Clock Multiplier Internal Oscillator Low Frequency Oscillator Figure 1.2. C8051F361/4/6/8 Block Diagram C2D Debug / Programming Hardware C2CK/RST Reset CIP-51 8051 Controller Core Power-On Reset 32/16 kB ISP FLASH Supply Program Memory ...

Page 22

C8051F360/1/2/3/4/5/6/7/8/9 1.1. CIP-51™ Microcontroller Core 1.1.1. Fully 8051 Compatible The C8051F36x family utilizes Silicon Labs' proprietary CIP-51 microcontroller core. The CIP-51 is fully compatible with the MCS-51™ instruction set; standard 803x/805x assemblers and compilers can be used to develop software. ...

Page 23

Additional Features The C8051F36x SoC family includes several key enhancements to the CIP-51 core and peripherals to improve performance and ease of use in end applications. The extended interrupt handler provides 16 interrupt sources into the CIP-51 (as opposed ...

Page 24

C8051F360/1/2/3/4/5/6/7/8/9 1.2. On-Chip Memory The CIP-51 has a standard 8051 program and data address configuration. It includes 256 bytes of data RAM, with the upper 128 bytes dual-mapped. Indirect addressing accesses the upper 128 bytes of general purpose RAM, and ...

Page 25

All the digital and analog peripherals are functional and work correctly while debugging. All the peripherals (except for the ADC and SMBus) are stalled when the MCU is halted, during single stepping breakpoint in ...

Page 26

C8051F360/1/2/3/4/5/6/7/8/9 The Digital Crossbar allows mapping of internal digital system resources to Port I/O pins. (See Figure 1.8.) On-chip counter/timers, serial buses, HW interrupts, comparator output, and other digital signals in the controller can be configured to appear on the ...

Page 27

PCA is clocked by an external source while the internal oscillator drives the system clock. Each capture/compare module can be configured to operate in one of six modes: Edge-Triggered Capture, Software Timer, High Speed Output, ...

Page 28

... Note: The first Port I/O pins shown in Figure 1.12 and Figure 1.13 are for the 48-pin (C8051F360/3) devices. The second set of Port I/O pins are for the 32-pin and 28-pin (C8051F361/2/4/5/6/7/8/9) devices. Please refer to the CPTnMX registers (SFR Definition 8.2 and SFR Definition 8.5) for more information. ...

Page 29

CP0EN CP0OUT CP0RIF CMX0N3 CP0FIF CMX0N2 CP0HYP1 CMX0N1 CP0HYP0 CMX0N0 CP0HYN1 CP0HYN0 CMX0P1 CMX0P0 P1.4 / P1.0 P2.3 / P1.4 P3.1 / P2.0 P3.5 / P2.4 P1.5 / P1.1 P2.4 / P1.5 P3.2 / P2.1 P3.6 / P2.5 Figure 1.12. ...

Page 30

C8051F360/1/2/3/4/5/6/7/8/9 CP1EN CP1OUT CP1RIF CP1FIF CP1HYP1 CMX1N1 CP1HYP0 CMX1N0 CP1HYN1 CP1HYN0 CMX1P1 CMX1P0 P2.0 / P1.2 P2.5 / P1.6 P3.3 / P2.2 P3.7 / P2.6 P2.1 / P1.3 P2.6 / P1.7 P3.4 / P2.3 P4.0 / P2.7 Figure 1.13. Comparator1 ...

Page 31

IDA0EN IDA0CM2 IDA0CM1 IDA0CM0 IDA0OMD1 IDA0OMD0 8 2 Figure 1.14. IDA0 Functional Block Diagram C8051F360/1/2/3/4/5/6/7/8/9 10 IDA0 Rev. 1.0 IDA0 31 ...

Page 32

C8051F360/1/2/3/4/5/6/7/8/9 2. Absolute Maximum Ratings Table 2.1. Absolute Maximum Ratings Parameter Ambient temperature under bias Storage Temperature Voltage on any Port I/O Pin or RST with respect to GND Voltage on V with respect to GND DD Maximum Total current ...

Page 33

Global Electrical Characteristics Table 3.1. Global Electrical Characteristics –40 to +85 °C, 25 MHz system clock unless otherwise specified. Parameter Digital Supply Voltage SYSCLK = MHz SYSCLK > 50 MHz Digital Supply RAM Data Retention Voltage ...

Page 34

C8051F360/1/2/3/4/5/6/7/8/9 Table 3.1. Global Electrical Characteristics (Continued) –40 to +85 °C, 25 MHz system clock unless otherwise specified. Parameter Digital Supply Current—CPU Inactive (Idle Mode, not fetching instructions from Flash 3 100 MHz I ...

Page 35

Table 3.2. Index to Electrical Characteristics Tables Peripheral Electrical Characteristics ADC0 Electrical Characteristics IDAC Electrical Characteristics Voltage Reference Electrical Characteristics Comparator Electrical Characteristics Reset Electrical Characteristics Flash Electrical Characteristics Internal High Frequency Oscillator Electrical Characteristics Internal Low Frequency Oscillator Electrical ...

Page 36

C8051F360/1/2/3/4/5/6/7/8/9 4. Pinout and Package Definitions Table 4.1. Pin Definitions for the C8051F36x Pin Pin Pin Name ‘F360/3 ‘F361/4/6/8 ‘F362/5/7/9 (48-pin) (32-pin) (28-pin) V 19, 31 GND 18, 30 AGND 6 — AV+ 7 — ...

Page 37

Table 4.1. Pin Definitions for the C8051F36x (Continued) Pin Pin Pin Name ‘F360/3 ‘F361/4/6/8 ‘F362/5/7/9 (48-pin) (32-pin) (28-pin P1.5 38 ...

Page 38

C8051F360/1/2/3/4/5/6/7/8/9 Table 4.1. Pin Definitions for the C8051F36x (Continued) Pin Pin Pin Name ‘F360/3 ‘F361/4/6/8 ‘F362/5/7/9 (48-pin) (32-pin) (28-pin P3.5 20 — P3.6 17 — P3.7 16 — ...

Page 39

P0.4 1 P0.3 2 P0.2 3 P0.1 4 P0.0 5 AGND 6 AV+ 7 /RST/C2CK 8 P4.6/C2D 9 P4.5 10 P4.4 11 P4.3 12 Figure 4.1. TQFP-48 Pinout Diagram (Top View) C8051F360/1/2/3/4/5/6/7/8/9 C8051F360/3 Rev. 1.0 P1.7 36 P2.0 35 P2.1 ...

Page 40

C8051F360/1/2/3/4/5/6/7/8/9 Figure 4.2. TQFP-48 Package Diagram Table 4.2. TQFP-48 Package Dimensions Dimension Min Nom A — — A1 0.05 — A2 0.95 1.00 b 0.17 0.22 c 0.09 — D 9.00 BSC. D1 7.00 BSC. e 0.50 BSC. Notes: 1. ...

Page 41

... P0 P0.0 GND 3 VDD 4 C8051F361/4/6/8 5 /RST/C2CK 6 P3.0/C2D 7 P3.1 8 P3.2 Figure 4.3. LQFP-32 Pinout Diagram (Top View) C8051F360/1/2/3/4/5/6/7/8/9 Rev. 1.0 24 P1.2 23 P1.3 22 P1.4 21 P1.5 20 P1.6 19 P1.7 18 P2.0 17 P2.1 41 ...

Page 42

C8051F360/1/2/3/4/5/6/7/8/9 Figure 4.4. LQFP-32 Package Diagram Table 4.3. LQFP-32 Package Dimensions Dimension Min Nom A — — A1 0.05 — A2 1.35 1.40 b 0.30 0.37 c 0.09 — D 9.00 BSC. D1 7.00 BSC. e 0.80 BSC. Notes: 1. ...

Page 43

P0.1 1 P0.0 2 GND 3 C8051F362/5/7/9 VDD 4 /RST/C2CK 5 6 P3.0/C2D P2.7 7 Figure 4.5. QFN-28 Pinout Diagram (Top View) C8051F360/1/2/3/4/5/6/7/8/9 GND Rev. 1.0 21 P1.1 20 P1.2 19 P1.3 18 P1.4 17 P1.5 16 P1.6 15 P1.7 ...

Page 44

C8051F360/1/2/3/4/5/6/7/8/9 Figure 4.6. QFN-28 Package Drawing Table 4.4. QFN-28 Package Dimensions Dimension Min Nom A 0.80 0.90 A1 0.03 0.07 A3 0.25 REF b 0.18 0.25 D 5.00 BSC. D2 2.90 3.15 e 0.50 BSC. E 5.00 BSC. Notes: 1. ...

Page 45

C8051F360/1/2/3/4/5/6/7/8/9 Figure 4.7. Typical QFN-28 Landing Diagram Rev. 1.0 45 ...

Page 46

C8051F360/1/2/3/4/5/6/7/8/9 Figure 4.8. QFN-28 Solder Paste Recommendation 46 Rev. 1.0 ...

Page 47

... P1.0-1.3 available on C8051F361/2/6/7/8/9 P1.7 P2.0 23-to-1 AMUX P2.7 P3.0 P3.1-3.4 available on C8051F360/1/6/8 P3.4 VDD Temp Sensor P1.0 P1.0-1.3 available on C8051F361/2/6/7/8/9 P1.7 P2.0 23-to-1 AMUX P2.7 P3.0 P3.1-3.4 available on C8051F360/1/6/8 P3.4 VREF GND Figure 5.1. ADC0 Functional Block Diagram C8051F360/1/2/3/4/5/6/7/8/9 AMX0P ADC0CN ...

Page 48

C8051F360/1/2/3/4/5/6/7/8/9 5.1. Analog Multiplexer AMUX0 selects the positive and negative inputs to the ADC. Any of the following may be selected as the positive input: the AMUX0 Port I/O inputs, the on-chip temperature sensor, or the positive power supply (V ...

Page 49

Temperature Sensor The typical temperature sensor transfer function is shown in Figure 5.2. The output voltage (V positive ADC input when the temperature sensor is selected by bits AMX0P4-0 in register AMX0P. (mV) 1200 1100 1000 900 800 700 ...

Page 50

C8051F360/1/2/3/4/5/6/7/8/9 5.00 4.00 3.00 2.00 1.00 0.00 -40.00 -20.00 -1.00 -2.00 -3.00 -4.00 -5.00 Figure 5.3. Temperature Sensor Error with 1-Point Calibration 50 40.00 0.00 20.00 Temperature (degrees C) Rev. 1.0 5.00 4.00 3.00 2.00 1.00 0.00 60.00 80.00 -1.00 ...

Page 51

... Important Note About Using CNVSTR: The CNVSTR input pin also functions as Port pin P0.7 on the C8051F360 devices and Port pin P0.6 on the C8051F361/2/6/7/8/9 devices. When the CNVSTR input is used as the ADC0 conversion source, the corresponding port pin should be skipped by the Digital Cross- bar. To configure the Crossbar to skip the port pin, set the appropriate bit to ‘ ...

Page 52

C8051F360/1/2/3/4/5/6/7/8/9 5.3.2. Tracking Modes According to Table 5.1, each ADC0 conversion must be preceded by a minimum tracking time for the con- verted result to be accurate. The AD0TM bit in register ADC0CN controls the ADC0 track-and-hold mode. In its ...

Page 53

Settling Time Requirements When the ADC0 input configuration is changed (i.e., a different AMUX0 selection is made), a minimum tracking time is required before an accurate conversion can be performed. This tracking time is determined by the AMUX0 resistance, ...

Page 54

... Notes: 1. Only applies to C8051F361/2/6/7/8/9 (32-pin and 28-pin); selection RESERVED on C8051F360 (48-pin) device. 2. Only applies to C8051F360/1/6/8 (48-pin and 32-pin); selection RESERVED on C8051F362/7/9 (28-pin) devices. 54 R/W R/W R/W AMX0P4 AMX0P3 AMX0P2 AMX0P1 Bit4 Bit3 ...

Page 55

... Notes: 1. Only applies to C8051F361/2/6/7/8/9 (32-pin and 28-pin); selection RESERVED on C8051F360 (48-pin) device. 2. Only applies to C8051F360/1/6/8 (48-pin and 32-pin); selection RESERVED on C8051F362/7/9 (28-pin) devices. C8051F360/1/2/3/4/5/6/7/8/9 R/W R/W R/W R/W Bit4 Bit3 Bit2 Bit1 ...

Page 56

C8051F360/1/2/3/4/5/6/7/8/9 SFR Definition 5.3. ADC0CF: ADC0 Configuration SFR Page: all pages SFR Address: 0xBC R/W R/W R/W AD0SC4 AD0SC3 AD0SC2 Bit7 Bit6 Bit5 Bits 7–3: AD0SC4–0: ADC0 SAR Conversion Clock Period Bits. SAR Conversion clock is derived from system clock ...

Page 57

SFR Definition 5.6. ADC0CN: ADC0 Control SFR Page: all pages (bit addressable) SFR Address: 0xE8 R/W R/W R/W AD0EN AD0TM AD0INT AD0BUSY AD0WINT AD0CM2 AD0CM1 AD0CM0 00000000 Bit7 Bit6 Bit5 Bit 7: AD0EN: ADC0 Enable Bit. 0: ADC0 Disabled. ADC0 ...

Page 58

C8051F360/1/2/3/4/5/6/7/8/9 5.4. Programmable Window Detector The ADC Programmable Window Detector continuously compares the ADC0 output registers to user-pro- grammed limits, and notifies the system when a desired condition is detected. This is especially effective in an interrupt-driven system, saving code ...

Page 59

SFR Definition 5.9. ADC0LTH: ADC0 Less-Than Data High Byte SFR Page: all pages SFR Address: 0xC6 R/W R/W R/W Bit7 Bit6 Bit5 Bits 7–0: High byte of ADC0 Less-Than Data Word. SFR Definition 5.10. ADC0LTL: ADC0 Less-Than Data Low Byte ...

Page 60

C8051F360/1/2/3/4/5/6/7/8/9 5.4.1. Window Detector In Single-Ended Mode Figure 5.6 shows two example window comparisons for right-justified, single-ended data, with ADC0LTH:ADC0LTL = 0x0080 (128d) and ADC0GTH:ADC0GTL = 0x0040 (64d). In single-ended mode, the input voltage can range from ‘0’ to VREF ...

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Window Detector In Differential Mode Figure 5.8 shows two example window comparisons for right-justified, differential data, with ADC0LTH:ADC0LTL = 0x0040 (+64d) and ADC0GTH:ADC0GTH = 0xFFFF (-1d). In differential mode, the measurable voltage between the input pins is between -VREF ...

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C8051F360/1/2/3/4/5/6/7/8/9 Table 5.1. ADC0 Electrical Characteristics V = 3.0 V, VREF = 2.40 V (REFSL=0), –40 to +85 °C unless otherwise specified. DD Parameter DC Accuracy Resolution Integral Nonlinearity Differential Nonlinearity Offset Error Full Scale Error Dynamic Performance (10 kHz ...

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... SFR Definition 6.1). When IDA0EN is set to ‘0’, the IDAC port pin (P0.4 for C8051F360, P0.1 for C8051F361/2/6/7/8/9) behaves as a normal GPIO pin. When IDA0EN is set to ‘1’, the digital output drivers and weak pullup for the IDAC pin are automatically disabled, and the pin is connected to the IDAC output. ...

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C8051F360/1/2/3/4/5/6/7/8/9 6.1.2. Update Output Based on Timer Overflow Similar to the ADC operation, in which an ADC conversion can be initiated by a timer overflow indepen- dently of the processor, the IDAC outputs can use a Timer overflow to schedule ...

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SFR Definition 6.1. IDA0CN: IDA0 Control SFR Page: all pages SFR Address: 0xB9 R/W R/W R/W IDA0EN IDA0CM Bit7 Bit6 Bit5 Bit 7: IDA0EN: IDA0 Enable. 0: IDA0 Disabled. 1: IDA0 Enabled. Bits 6–4: IDA0CM[2:0]: IDA0 Update Source Select bits. ...

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C8051F360/1/2/3/4/5/6/7/8/9 SFR Definition 6.3. IDA0L: IDA0 Data Word LSB SFR Page: all pages SFR Address: 0x96 R/W R/W R — Bit7 Bit6 Bit5 Bits 7–6: IDA0 Data Word Low-Order Bits. Lower 2 bits of the 10-bit Data Word. Bits 5–0: ...

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... Important Note about the VREF Pin: Port pin P0.3 on the C8051F360 device and P0.0 on C8051F361/2/6/7/89 devices is used as the external VREF input and as an output for the internal VREF. When using either an external voltage reference or the internal reference circuitry, the port pin should be configured as an analog pin, and skipped by the Digital Crossbar. To configure the port pin as an analog pin, set the appropriate bit to ‘ ...

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C8051F360/1/2/3/4/5/6/7/8/9 complete Port I/O configuration details. The TEMPE bit in register REF0CN enables/disables the tempera- ture sensor. While disabled, the temperature sensor defaults to a high impedance state and any ADC0 measurements performed on the sensor result in meaningless data. ...

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Table 7.1. Voltage Reference Electrical Characteristics V = 3.0 V; –40 to +85 °C unless otherwise specified. DD Parameter Output Voltage 25 °C ambient VREF Short-Circuit Current VREF Temperature Coefficient Load Regulation Load = 0 to 200 µA to AGND ...

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C8051F360/1/2/3/4/5/6/7/8/9 8. Comparators C8051F36x devices include two on-chip programmable voltage comparators, Comparator0 and Comparator1, shown in Figure 8.1 and Figure 8.2 (Note: the port pin Comparator inputs differ between C8051F36x devices. The first Port I/O pin shown is for C8051F360/3 ...

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CP1OUT CP1HYP1 CMX1N1 CP1HYP0 CMX1N0 CP1HYN1 CP1HYN0 CMX1P1 CMX1P0 P2.0 / P1.2 P2.5 / P1.6 P3.3 / P2.2 P3.7 / P2.6 P2.1 / P1.3 P2.6 / P1.7 P3.4 / P2.3 P4.0 / P2.7 Figure 8.2. Comparator1 Functional Block Diagram A ...

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C8051F360/1/2/3/4/5/6/7/8/9 CP0+ VIN+ + CP0 CP0- _ VIN- CIRCUIT CONFIGURATION Positive Hysteresis Voltage (Programmed with CP0HYP Bits) VIN- INPUTS VIN OUTPUT V OL Positive Hysteresis Disabled Figure 8.3. Comparator Hysteresis Plot The Comparator hysteresis is software-programmable via the ...

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SFR Definition 8.1. CPT0CN: Comparator0 Control SFR Page: all pages SFR Address: 0x9B R/W R R/W CP0EN CP0OUT CP0RIF Bit7 Bit6 Bit5 Bit 7: CP0EN: Comparator0 Enable Bit. 0: Comparator0 Disabled. 1: Comparator0 Enabled. Bit 6: CP0OUT: Comparator0 Output State ...

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... CMX0P1 CMX0P0 Bit4 Bit3 Bit2 Bit1 C8051F360/3 C8051F361/2/4/5/6/7/8/9 Negative Input Negative Input P1.5 P1.1 P2.4 P1.5 P3.2 P2.1 P3.6 P2.5 C8051F360/3 C8051F361/2/4/5/6/7/8/9 Positive Input Positive Input P1.4 P1.0 P2.3 P1.4 P3.1 P2.0 P3.5 P2.4 Rev. 1.0 R/W Reset Value 11111111 Bit0 ...

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SFR Definition 8.3. CPT0MD: Comparator0 Mode Selection SFR Page: all pages SFR Address: 0x9D R R R/W – – CP0RIE CP0FIE Bit7 Bit6 Bit5 Bits 7–6: UNUSED. Read = 00b, Write = don’t care. Bit 5: CP0RIE: Comparator0 Rising-Edge Interrupt ...

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C8051F360/1/2/3/4/5/6/7/8/9 SFR Definition 8.4. CPT1CN: Comparator1 Control SFR Page: all pages SFR Address: 0x9A R/W R R/W CP1EN CP1OUT CP1RIF Bit7 Bit6 Bit5 Bit 7: CP1EN: Comparator1 Enable Bit. 0: Comparator1 Disabled. 1: Comparator1 Enabled. Bit 6: CP1OUT: Comparator1 Output ...

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... CMX1P1 CMX1P0 Bit4 Bit3 Bit2 C8051F360/3 C8051F361/2/4/5/6/7/8/9 Negative Input Negative Input P2.1 P1.3 P2.6 P1.7 P3.4 P2.3 P4.0 P2.7 C8051F360/3 C8051F361/2/4/5/6/7/8/9 Positive Input Positive Input P2.0 P1.2 P2.5 P1.6 P3.3 P2.2 P3.7 P2.6 Rev. 1.0 R/W R/W Reset Value 11111111 Bit1 ...

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C8051F360/1/2/3/4/5/6/7/8/9 SFR Definition 8.6. CPT1MD: Comparator1 Mode Selection SFR Page: all pages SFR Address: 0x9C R R R/W – – CP1RIE Bit7 Bit6 Bit5 Bits 7–6: UNUSED. Read = 00b, Write = don’t care. Bit 5: CP1RIE: Comparator1 Rising-Edge Interrupt ...

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Table 8.1. Comparator Electrical Characteristics V = 3.0 V, –40 to +85 °C unless otherwise noted. DD Parameter CPx+ – CPx– = 100 mV Response Time: * Mode 0, Vcm = 1.5 V CPx+ – CPx– = –100 mV CPx+ ...

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C8051F360/1/2/3/4/5/6/7/8/9 9. CIP-51 Microcontroller The MCU system controller core is the CIP-51 microcontroller. The CIP-51 is fully compatible with the MCS-51™ instruction set; standard 803x/805x assemblers and compilers can be used to develop soft- ware. The MCU family has a ...

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ACCUMULATOR PSW DATA POINTER PC INCREMENTER PROGRAM COUNTER (PC) PRGM. ADDRESS REG. CONTROL RESET LOGIC CLOCK STOP POWER CONTROL IDLE Figure 9.1. CIP-51 Block Diagram 9.2. Programming and Debugging Support A C2-based serial interface is provided for in-system programming of ...

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C8051F360/1/2/3/4/5/6/7/8/9 9.3. Instruction Set The instruction set of the CIP-51 System Controller is fully compatible with the standard MCS-51™ instruc- tion set; standard 8051 development tools can be used to develop software for the CIP-51. All CIP-51 instructions are the ...

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Table 9.1. CIP-51 Instruction Set Summary (Continued) Mnemonic Description DEC A Decrement A DEC Rn Decrement register DEC direct Decrement direct byte DEC @Ri Decrement indirect RAM INC DPTR Increment Data Pointer MUL AB Multiply A and B DIV AB ...

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C8051F360/1/2/3/4/5/6/7/8/9 Table 9.1. CIP-51 Instruction Set Summary (Continued) Mnemonic Description MOV direct, @Ri Move indirect RAM to direct byte MOV direct, #data Move immediate to direct byte MOV @Ri, A Move A to indirect RAM MOV @Ri, direct Move direct ...

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Table 9.1. CIP-51 Instruction Set Summary (Continued) Mnemonic Description JZ rel Jump if A equals zero JNZ rel Jump if A does not equal zero CJNE A, direct, rel Compare direct byte to A and jump if not equal CJNE ...

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C8051F360/1/2/3/4/5/6/7/8/9 9.4. Memory Organization The memory organization of the CIP-51 System Controller is similar to that of a standard 8051. There are two separate memory spaces: program memory and data memory. Program and data memory share the same address space ...

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Data Memory The CIP-51 implements 256 bytes of internal RAM mapped into the data memory space from 0x00 through 0xFF. The lower 128 bytes of data memory are used for general purpose registers and memory. Either direct or indirect ...

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C8051F360/1/2/3/4/5/6/7/8/9 and each CALL pushes two record bits onto the register. (A POP or decrement SP pops one record bit, and a RET pops two record bits, also.) The stack record circuitry can also detect an overflow or underflow on ...

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Interrupt Logic CIP-51 Figure 9.3. SFR Page Stack Automatic hardware switching of the SFR Page on interrupts may be enabled or disabled as desired using the SFR Automatic Page Control Enable Bit located in the SFR Page Control Register (SFR0CN). ...

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C8051F360/1/2/3/4/5/6/7/8/9 9.4.6.3. SFR Page Stack Example The following is an example that shows the operation of the SFR Page Stack during interrupts. In this example, the SFR Page Control is left in the default enabled state (i.e., SFRPGEN = 1), ...

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SFRPAGE pushed to SFRNEXT Figure 9.5. SFR Page Stack After ADC0 Window Comparator Interrupt Occurs While in the ADC0 ISR, a PCA interrupt occurs. Recall the PCA interrupt is configured as a high priority interrupt, while the ADC0 interrupt is ...

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C8051F360/1/2/3/4/5/6/7/8/9 On exit from the PCA interrupt service routine, the CIP-51 will return to the ADC0 Window Comparator ISR. On execution of the RETI instruction, SFR Page 0x00 used to access the PCA registers will be auto- matically popped off ...

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On the execution of the RETI instruction in the ADC0 Window Comparator ISR, the value in SFRPAGE register is overwritten with the contents of SFRNEXT. The CIP-51 may now access the OSCICN SFR bits as it did prior to the ...

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C8051F360/1/2/3/4/5/6/7/8/9 SFR Definition 9.1. SFR0CN: SFR Page Control SFR Page: F SFR Address: 0xE5 R/W R/W R/W Reserved Reserved Reserved Reserved Reserved Reserved Reserved SFRPGEN 00000001 Bit7 Bit6 Bit5 Bits 7–1: RESERVED. Read = 0000000b. Must Write 0000000b. Bit 0: ...

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SFR Definition 9.3. SFRNEXT: SFR Next Register SFR Page: all pages SFR Address: 0x85 R/W R/W R/W Bit7 Bit6 Bit5 Bits 7–0: SFR Page Stack Bits: SFR page context is retained upon interrupts/return from interrupts byte SFR ...

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C8051F360/1/2/3/4/5/6/7/8/9 Table 9.2. Special Function Register (SFR) Memory Map 0(8) 1( SPI0CN PCA0L MAC0BL F P0MDIN E8 0 ADC0CN PCA0CPL1 PCA0CPH1 PCA0CPL2 PCA0CPH2 PCA0CPL3 PCA0CPH3 ACC P1MAT F XBR0 D8 0 ...

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Table 9.3. Special Function Registers SFRs are listed in alphabetical order. All undefined SFR locations are reserved. Register Address SFR Page ACC 0xE0 All Pages Accumulator ADC0CF 0xBC All Pages ADC0 Configuration ADC0CN 0xE8 All Pages ADC0 Control ADC0GTH 0xC4 ...

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C8051F360/1/2/3/4/5/6/7/8/9 Table 9.3. Special Function Registers (Continued) SFRs are listed in alphabetical order. All undefined SFR locations are reserved. Register Address SFR Page EMI0CF 0xC7 F EMI0CN 0xAA All Pages EMIF Control EMI0TC 0xF7 F FLKEY 0xB7 0 FLSCL 0xB6 ...

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Table 9.3. Special Function Registers (Continued) SFRs are listed in alphabetical order. All undefined SFR locations are reserved. Register Address SFR Page P0MAT 0xF3 0 P0MDIN 0xF1 F P0MDOUT 0xA4 F P0SKIP 0xD4 F P1 0x90 All Pages Port 1 ...

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C8051F360/1/2/3/4/5/6/7/8/9 Table 9.3. Special Function Registers (Continued) SFRs are listed in alphabetical order. All undefined SFR locations are reserved. Register Address SFR Page PCA0CPL2 0xEB All Pages PCA Module 2 Capture/Compare Low Byte PCA0CPL3 0xED All Pages PCA Module 3 ...

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Table 9.3. Special Function Registers (Continued) SFRs are listed in alphabetical order. All undefined SFR locations are reserved. Register Address SFR Page SP 0x81 All Pages Stack Pointer SPI0CFG 0xA1 All Pages SPI Configuration SPI0CKR 0xA2 All Pages SPI Clock ...

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C8051F360/1/2/3/4/5/6/7/8/9 9.4.7. Register Descriptions Following are descriptions of SFRs related to the operation of the CIP-51 System Controller. Reserved bits should not be set to logic ‘1’. Future product versions may use these bits to implement new features in which ...

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SFR Definition 9.8. PSW: Program Status Word SFR Page: all pages (bit addressable) SFR Address: 0xD0 R/W R/W R Bit7 Bit6 Bit5 Bit 7: CY: Carry Flag. This bit is set when the last arithmetic operation resulted ...

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C8051F360/1/2/3/4/5/6/7/8/9 SFR Definition 9.9. ACC: Accumulator SFR Page: all pages (bit addressable) SFR Address: 0xE0 R/W R/W R/W ACC.7 ACC.6 ACC.5 Bit7 Bit6 Bit5 Bits 7–0: ACC: Accumulator. This register is the accumulator for arithmetic operations. SFR Definition 9.10. B: ...

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Idle Mode Setting the Idle Mode Select bit (PCON.0) causes the CIP-51 to halt the CPU and enter Idle mode as soon as the instruction that sets the bit completes. data. All analog and digital peripherals can remain active ...

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C8051F360/1/2/3/4/5/6/7/8/9 SFR Definition 9.11. PCON: Power Control SFR Page: all pages SFR Address: 0x87 R/W R/W R/W Reserved Reserved Reserved Reserved Reserved Reserved Bit7 Bit6 Bit5 Bits 7–3: RESERVED. Read = 000000b. Must Write 000000b. Bit 1: STOP: STOP Mode ...

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Interrupt Handler The C8051F36x family includes an extended interrupt system supporting a total of 16 interrupt sources with two priority levels. The allocation of interrupt sources between on-chip peripherals and external input pins varies according to the specific version ...

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C8051F360/1/2/3/4/5/6/7/8/9 10.2. Interrupt Priorities Each interrupt source can be individually programmed to one of two priority levels: low or high. A low prior- ity interrupt service routine can be preempted by a high priority interrupt. A high priority interrupt cannot ...

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Table 10.1. Interrupt Summary (Continued) Interrupt Interrupt Source Vector Programmable Counter 0x005B Array Comparator0 0x0063 Comparator1 0x006B Timer 3 Overflow 0x0073 RESERVED 0x007B Port Match 0x0083 10.4. Interrupt Register Descriptions The SFRs used to enable the interrupt sources and set ...

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C8051F360/1/2/3/4/5/6/7/8/9 SFR Definition 10.1. IE: Interrupt Enable SFR Page: all pages (bit addressable) SFR Address: 0xA8 R/W R/W R/W EA ESPI0 ET2 Bit7 Bit6 Bit5 Bit 7: EA: Global Interrupt Enable. This bit globally enables/disables all interrupts. It overrides the ...

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SFR Definition 10.2. IP: Interrupt Priority SFR Page: all pages (bit addressable) SFR Address: 0xB8 R R/W R/W – PSPI0 PT2 Bit7 Bit6 Bit5 Bit 7: UNUSED. Read = 1b, Write = don't care. Bit 6: PSPI0: Serial Peripheral Interface ...

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C8051F360/1/2/3/4/5/6/7/8/9 SFR Definition 10.3. EIE1: Extended Interrupt Enable 1 SFR Page: all pages SFR Address: 0xE6 R/W R/W R/W ET3 ECP1 ECP0 Bit7 Bit6 Bit5 Bit 7: ET3: Enable Timer 3 Interrupt. This bit sets the masking of the Timer ...

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SFR Definition 10.4. EIP1: Extended Interrupt Priority 1 SFR Page: F SFR Address: 0xCE R/W R/W R/W PT3 PCP1 PCP0 Bit7 Bit6 Bit5 Bit 7: PT3: Timer 3 Interrupt Priority Control. This bit sets the priority of the Timer 3 ...

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C8051F360/1/2/3/4/5/6/7/8/9 SFR Definition 10.5. EIE2: Extended Interrupt Enable 2 SFR Page: all pages SFR Address: 0xE7 R/W R/W R/W – – – Bit7 Bit6 Bit5 Bits 7–2: UNUSED. Read = 000000b. Write = don’t care. Bit 1: EMAT: Enable Port ...

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External Interrupts The /INT0 and /INT1 external interrupt sources are configurable as active high or low, edge or level sensi- tive. The IN0PL (/INT0 Polarity) and IN1PL (/INT1 Polarity) bits in the IT01CF register select active high or active ...

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C8051F360/1/2/3/4/5/6/7/8/9 SFR Definition 10.7. IT01CF: INT0/INT1 Configuration SFR Page: all pages SFR Address: 0xE4 R/W R/W R/W IN1PL IN1SL2 IN1SL1 Bit7 Bit6 Bit5 Note: Refer to SFR Definition 21.1. “TCON: Timer Control” on page 252 for INT0/1 edge- or level-sensitive ...

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Multiply And Accumulate (MAC0) The C8051F36x devices include a multiply and accumulate engine which can be used to speed up many mathematical operations. MAC0 contains a 16-by-16 bit multiplier and a 40-bit adder, which can perform integer or fractional ...

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C8051F360/1/2/3/4/5/6/7/8/9 11.2. Integer and Fractional Math MAC0 is capable of interpreting the 16-bit inputs stored in MAC0A and MAC0B as signed integers or as signed fractional numbers. When the MAC0FM bit (MAC0CF.1) is cleared to ‘0’, the inputs are treated ...

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Operating in Multiply and Accumulate Mode MAC0 operates in Multiply and Accumulate (MAC) mode when the MAC0MS bit (MAC0CF.0) is cleared to ‘0’. When operating in MAC mode, MAC0 performs a 16-by-16 bit multiply on the contents of the ...

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C8051F360/1/2/3/4/5/6/7/8/9 11.6. Rounding and Saturation A Rounding Engine is included, which can be used to provide a rounded result when operating on frac- tional numbers. MAC0 uses an unbiased rounding algorithm to round the data stored in bits 31–16 of ...

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Multiply Only Example The example below implements the equation: MOV MAC0CF, #01h ; Use integer numbers, and multiply only mode (add to zero) MOV MAC0AH, #12h ; Load MAC0A register with 1234 hex = 4660 decimal MOV MAC0AL, #34h ...

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C8051F360/1/2/3/4/5/6/7/8/9 SFR Definition 11.1. MAC0CF: MAC0 Configuration SFR Page: 0 SFR Address: 0xD7 R R R/W – – MAC0SC MAC0SD MAC0CA MAC0SAT MAC0FM MAC0MS 00000000 Bit7 Bit6 Bit5 Bits 7–6: UNUSED: Read = 00b, Write = don’t care. Bit 5: ...

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SFR Definition 11.2. MAC0STA: MAC0 Status SFR Page: 0 SFR Address: 0xCF – – – Bit7 Bit6 Bit5 Bits 7–4: UNUSED: Read = 0000b, Write = don’t care. Bit 3: MAC0HO: Hard Overflow Flag. This bit is ...

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C8051F360/1/2/3/4/5/6/7/8/9 SFR Definition 11.4. MAC0AL: MAC0 A Low Byte SFR Page: 0 SFR Address: 0xA4 Bit7 Bit6 Bit5 Bits 7–0: Low Byte (bits 7–0) of MAC0 A Register. SFR Definition 11.5. MAC0BH: MAC0 B High Byte SFR ...

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SFR Definition 11.7. MAC0ACC3: MAC0 Accumulator Byte 3 SFR Page: 0 SFR Address: 0xD5 Bit7 Bit6 Bit5 Bits 7–0: Byte 3 (bits 31–24) of MAC0 Accumulator. Note:The contents of this register should not be changed by software ...

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C8051F360/1/2/3/4/5/6/7/8/9 SFR Definition 11.10. MAC0ACC0: MAC0 Accumulator Byte 0 SFR Page: 0 SFR Address: 0xD2 Bit7 Bit6 Bit5 Bits 7–0: Byte 0 (bits 7–0) of MAC0 Accumulator. Note:The contents of this register should not be changed by ...

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SFR Definition 11.13. MAC0RNDL: MAC0 Rounding Register Low Byte SFR Page: 0 SFR Address: 0xAE Bit7 Bit6 Bit5 Bits 7–0: Low Byte (bits 7–0) of MAC0 Rounding Register. C8051F360/1/2/3/4/5/6/7/8 Bit4 Bit3 Bit2 Bit1 ...

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C8051F360/1/2/3/4/5/6/7/8/9 12. Reset Sources Reset circuitry allows the controller to be easily placed in a predefined default condition. On entry to this reset state, the following occur: • CIP-51 halts program execution • Special Function Registers (SFRs) are initialized to ...

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Power-On Reset During power-up, the device is held in a reset state and the RST pin is driven low until delay occurs before the device is released from reset; the delay decreases as the V ...

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C8051F360/1/2/3/4/5/6/7/8/9 12.2. Power-Fail Reset/V DD When a power-down transition or power irregularity causes V monitor will drive the RST pin low and hold the CIP- reset state (see Figure 12.2). When level above V , ...

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SFR Definition 12.1. VDM0CN: V SFR Page: all pages SFR Address: 0xFF R VDMEN VDDSTAT Reserved Reserved Reserved Reserved Reserved Reserved Bit7 Bit6 Bit5 Bit 7: VDMEN: V Monitor Enable. DD This bit turns the V Monitor circuit ...

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C8051F360/1/2/3/4/5/6/7/8/9 12.6. PCA Watchdog Timer Reset The programmable Watchdog Timer (WDT) function of the Programmable Counter Array (PCA) can be used to prevent software from running out of control during a system malfunction. The PCA WDT function can be enabled ...

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SFR Definition 12.2. RSTSRC: Reset Source SFR Page: all pages SFR Address: 0xEF R R R/W – FERROR C0RSEF SWRSF Bit7 Bit6 Bit5 Note:For bits that act as both reset source enables (on a write) and reset indicator flags (on ...

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C8051F360/1/2/3/4/5/6/7/8/9 Table 12.1. Reset Electrical Characteristics –40 to +85 °C unless otherwise specified. Parameter I OL RST Output Low Voltage V DD RST Input High Voltage RST Input Low Voltage RST Input Pullup Impedance V POR Threshold ( ...

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Flash Memory All devices include either 32 kB (C8051F360/1/2/3/4/5/6/ (C8051F368/9) of on-chip, reprogram- mable Flash memory for program code or non-volatile data storage. The Flash memory can be pro- grammed in-system through the C2 interface, or ...

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C8051F360/1/2/3/4/5/6/7/8/9 erases will be disabled until the next system reset. Flash writes and erases will also be disabled if a Flash write or erase is attempted before the key codes have been written properly. The Flash lock resets after each ...

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Steps 3–8 must be repeated for each byte to be written For block Flash writes, the Flash write procedure is only performed after the last byte of each block is writ- ten with the MOVX write instruction. When writing to ...

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C8051F360/1/2/3/4/5/6/7/8/9 13.2. Security Options The CIP-51 provides security options to protect the Flash memory from inadvertent modification by soft- ware as well as to prevent the viewing of proprietary program code and constants. The Program Store Write Enable (bit PSWE ...

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Summary of Flash Security Options The level of Flash security depends on the Flash access method. The three Flash access methods that can be restricted are reads, writes, and erases from the C2 debug interface, user firmware executing on ...

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C8051F360/1/2/3/4/5/6/7/8/9 13.3. Flash Write and Erase Guidelines Any system which contains routines which write or erase Flash memory from software involves some risk that the write or erase routines will execute unintentionally if the CPU is operating outside its specified ...

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PSWE Maintenance 7. Reduce the number of places in code where the PSWE bit (b0 in PSCTL) is set to a '1'. There should be exactly one routine in code that sets PSWE to a '1' to write ...

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C8051F360/1/2/3/4/5/6/7/8/9 SFR Definition 13.1. SFR Page: 0 SFR Address: 0x8F R/W R/W R/W – – – Bit7 Bit6 Bit5 Bits 7–2: UNUSED. Read = 000000b, Write = don't care. Bit 1: PSEE: Program Store Erase Enable. Setting this bit allows ...

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Flash Read Timing On reset, the C8051F36x Flash read timing is configured for operation with system clocks MHz. If the system clock will not be increased above 25 MHz, then the Flash timing registers may be ...

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C8051F360/1/2/3/4/5/6/7/8/9 Table 13.2. Flash Electrical Characteristics V = 2.7 to 3.6 V; –40 to +85 °C. DD Parameter Conditions C8051F360/1/2/3/4/5/6/7 Flash Size C8051F368/9 Endurance Erase Cycle Time Write Cycle Time *Note: 1024 Bytes at location 0x7C00 to 0x7FFF are reserved. ...

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Branch Target Cache The C8051F36x device families incorporate a 32x4 byte branch target cache with a 4-byte prefetch engine. Because the access time of the Flash memory is 40 ns, and the minimum instruction time (C8051F360/1/2/3/4/5/6/7) ...

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C8051F360/1/2/3/4/5/6/7/8/9 The replacement algorithm is selected with the Cache Algorithm bit, CHALGM (CCH0TN.3). When CHALGM is cleared to ‘0’, the cache will use the rebound algorithm to replace cache locations. The rebound algorithm replaces locations in order from the beginning ...

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Certain types of instruction data or certain blocks of code can also be excluded from caching. The destina- tions of RETI instructions are, by default, excluded from caching. To enable caching of RETI destinations, the CHRETI bit (CCH0CN.3) can be ...

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C8051F360/1/2/3/4/5/6/7/8/9 Cache Push Operations Decrement CHSLOT CHSLOT = 27 Cache Pop Operations Increment CHSLOT Figure 14.3. Cache Lock Operation 148 TAG 0 SLOT 0 TAG 1 SLOT 1 TAG 2 SLOT 2 TAG 26 SLOT 26 TAG 27 SLOT 27 ...

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SFR Definition 14.1. CCH0CN: Cache Control SFR Page: F SFR Address: 0x84 R/W R/W R/W CHWREN CHRDEN CHPFEN CHFLSH Bit7 Bit6 Bit5 Bit 7: CHWREN: Cache Write Enable. This bit enables the processor to write to the cache memory. 0: ...

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C8051F360/1/2/3/4/5/6/7/8/9 SFR Definition 14.2. CCH0TN: Cache Tuning SFR Page: F SFR Address: 0xC9 R/W R/W R/W CHMSCTL Bit7 Bit6 Bit5 Bits 7–4: CHMSCTL: Cache Miss Penalty Accumulator (Bits 4–1). These are bits 4-1 of the Cache Miss Penalty Accumulator. To ...

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SFR Definition 14.3. CCH0LC: Cache Lock Control SFR Page: F SFR Address: 0xD2 R/W R/W R CHPUSH CHPOP RESERVED Bit7 Bit6 Bit5 Bit 7: CHPUSH: Cache Push Enable. This bit enables cache push operations, which will lock information in cache ...

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C8051F360/1/2/3/4/5/6/7/8/9 SFR Definition 14.4. CCH0MA: Cache Miss Accumulator SFR Page: F SFR Address: 0xD3 R R/W R/W CHMSOV Bit7 Bit6 Bit5 Bit 7: CHMSOV: Cache Miss Penalty Overflow. This bit indicates when the Cache Miss Penalty Accumulator has overflowed since ...

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External Data Memory Interface and On-Chip XRAM For C8051F36x devices, 1k Bytes of RAM are included on-chip and mapped into the external data memory space (XRAM). Additionally, an External Memory Interface (EMIF) is available on the C8051F360/3 devices, which ...

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C8051F360/1/2/3/4/5/6/7/8/9 15.2. Configuring the External Memory Interface Configuring the External Memory Interface consists of five steps: 1. Configure the Output Modes of the associated port pins as either push-pull or open-drain (push-pull is most common), and skip the associated pins ...

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Table 15.1. EMIF Pinout (C8051F360/3) Multiplexed Mode Signal Name Port Pin /RD /WR ALE D0/A0 D1/A1 D2/A2 D3/A3 D4/A4 D5/A5 D6/A6 D7/ A10 A11 A12 A13 A14 A15 – – – – – – – – SFR Definition ...

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C8051F360/1/2/3/4/5/6/7/8/9 SFR Definition 15.2. EMI0CF: External Memory Configuration SFR Page: F SFR Address: 0xC7 R/W R/W R/W – – – Bit7 Bit6 Bit5 Bits 7–5: UNUSED. Read = 000b. Write = don’t care. Bit 4: EMD2: EMIF Multiplex Mode Select. ...

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Multiplexed and Non-multiplexed Selection The External Memory Interface is capable of acting in a Multiplexed mode or a Non-multiplexed mode, depending on the state of the EMD2 (EMI0CF.4) bit. 15.4.1. Multiplexed Configuration In Multiplexed mode, the Data Bus and ...

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C8051F360/1/2/3/4/5/6/7/8/9 15.4.2. Non-multiplexed Configuration In Non-multiplexed mode, the Data Bus and the Address Bus pins are not shared. An example of a Non-multiplexed Configuration is shown in Figure 15.2. See Section “15.6.1. Non-multiplexed Mode” on page 162 for more information ...

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Memory Mode Selection The external data memory space can be configured in one of four modes, shown in Figure 15.3, based on the EMIF Mode bits in the EMI0CF register (SFR Definition 15.2). These modes are summarized below. More ...

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C8051F360/1/2/3/4/5/6/7/8/9 15.5.3. Split Mode with Bank Select When EMI0CF.[3:2] are set to ‘10’, the XRAM memory map is split into two areas, on-chip space and off-chip space. • Effective addresses below the internal XRAM size boundary will access on-chip XRAM ...

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SFR Definition 15.3. EMI0TC: External Memory Timing Control SFR Page: F SFR Address: 0xF7 R/W R/W R/W EAS1 EAS0 ERW3 Bit7 Bit6 Bit5 Bits 7–6: EAS1–0: EMIF Address Setup Time Bits. 00: Address setup time = 0 SYSCLK cycles. 01: ...

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C8051F360/1/2/3/4/5/6/7/8/9 15.6.1. Non-multiplexed Mode 15.6.1.1.16-bit MOVX: EMI0CF[4:2] = ‘101’, ‘110’, or ‘111’. ADDR[15:8] P3.4–P4.3 ADDR[7:0] P2 DATA[7:0] P1 /WR P4.5 /RD P4.4 ADDR[15:8] P3.4–P4.3 ADDR[7:0] P2 DATA[7:0] P1 /RD P4.4 /WR P4.5 Figure 15.4. Non-multiplexed 16-bit MOVX Timing 162 Nonmuxed ...

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MOVX without Bank Select: EMI0CF[4:2] = ‘101’ or ‘111’. ADDR[15:8] ADDR[7:0] P2 DATA[7:0] P1 /WR P4.5 /RD P4.4 ADDR[15:8] ADDR[7:0] P2 DATA[7:0] P1 /RD P4.4 /WR P4.5 Figure 15.5. Non-multiplexed 8-bit MOVX without Bank Select Timing C8051F360/1/2/3/4/5/6/7/8/9 Nonmuxed 8-bit ...

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C8051F360/1/2/3/4/5/6/7/8/9 15.6.1.3.8-bit MOVX with Bank Select: EMI0CF[4:2] = ‘110’. ADDR[15:8] P3.4–P4.3 ADDR[7:0] P2 DATA[7:0] P1 /WR P4.5 P4.4 /RD ADDR[15:8] P3.4–P4.3 ADDR[7:0] P2 DATA[7:0] P1 /RD P4.4 /WR P4.5 Figure 15.6. Non-multiplexed 8-bit MOVX with Bank Select Timing 164 Nonmuxed ...

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Multiplexed Mode 15.6.2.1.16-bit MOVX: EMI0CF[4:2] = ‘001’, ‘010’, or ‘011’. ADDR[15:8] P3.4–P4.3 EMIF ADDRESS (8 LSBs) from AD[7: ALEH ALE P0.0 /WR P4.5 /RD P4.4 ADDR[15:8] P3.4–P4.3 EMIF ADDRESS (8 LSBs) from AD[7: ALEH ALE ...

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C8051F360/1/2/3/4/5/6/7/8/9 15.6.2.2.8-bit MOVX without Bank Select: EMI0CF[4:2] = ‘001’ or ‘011’. ADDR[15:8] EMIF ADDRESS (8 LSBs) from AD[7: ALEH ALE P0.0 /WR P4.5 /RD P4.4 ADDR[15:8] EMIF ADDRESS (8 LSBs) from AD[7: ...

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MOVX with Bank Select: EMI0CF[4:2] = ‘010’. ADDR[15:8] P3.4–P4.3 EMIF ADDRESS (8 LSBs) from AD[7: ALEH ALE P0.0 /WR P4.5 /RD P4.4 ADDR[15:8] P3.4–P4.3 EMIF ADDRESS (8 LSBs) from AD[7: ...

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C8051F360/1/2/3/4/5/6/7/8/9 Table 15.2. AC Parameters for External Memory Interface Parameter Description T Address/Control Setup Time ACS T Address/Control Pulse Width ACW T Address/Control Hold Time ACH T Address Latch Enable High Time ALEH T Address Latch Enable Low Time ALEL ...

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Oscillators The C8051F36x devices include a programmable internal high-frequency oscillator, a programmable inter- nal low-frequency oscillator, and an external oscillator drive circuit. The internal high-frequency oscillator can be enabled, disabled, and calibrated using the OSCICN and OSCICL registers, as ...

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C8051F360/1/2/3/4/5/6/7/8/9 16.1.1. Internal Oscillator Suspend Mode When software writes a logic ‘1’ to SUSPEND (OSCICN.5), the internal oscillator is suspended. If the sys- tem clock is derived from the internal oscillator, the input clock to the peripheral or CIP-51 will ...

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SFR Definition 16.2. OSCICN: Internal Oscillator Control SFR Page: F SFR Address: 0xB7 R/W R R/W IOSCEN IFRDY SUSPEND Reserved Reserved Reserved Bit7 Bit6 Bit5 Bit 7: IOSCEN: Internal Oscillator Enable Bit. 0: Internal Oscillator Disabled. 1: Internal Oscillator Enabled. ...

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C8051F360/1/2/3/4/5/6/7/8/9 16.2.1. Calibrating the Internal L-F Oscillator Timers 2 and 3 include capture functions that can be used to capture the oscillator frequency, when run- ning from a known time base. When either Timer 2 or Timer 3 is configured ...

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... P0.5 and P0.6 (C8051F360/3) or P0.2 and P0.3 (C8051F361/2/4/5/6/7/8/9) are used as XTAL1 and XTAL2 respectively. When the external oscillator drive circuit is enabled in capacitor, RC, or CMOS clock mode, Port pin P0.6 (C8051F360/3) or P0.3 (C8051F361/2/4/5/6/7/8/9) is used as XTAL2. The Port I/O Crossbar should be configured to skip the Port pins used by the oscillator circuit; see Section “17.1. Priority Crossbar Decoder” ...

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C8051F360/1/2/3/4/5/6/7/8/9 SFR Definition 16.4. CLKSEL: System Clock Selection SFR Page: F SFR Address: 0x8F R/W R/W R/W Reserved Reserved CLKDIV1 CLKDIV0 Reserved CLKSL2 Bit7 Bit6 Bit5 Bits 7–6: RESERVED. Read = 00b. Must Write 00b. Bits 5–4: CLKDIV1-0: Output SYSCLK ...

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SFR Definition 16.5. OSCXCN: External Oscillator Control SFR Page: F SFR Address: 0xB6 R R/W R/W XTLVLD XOSCMD2 XOSCMD1 XOSCMD0 Reserved Bit7 Bit6 Bit5 Bit 7: XTLVLD: Crystal Oscillator Valid Flag. (Valid only when XOSCMD = 11x.) 0: Crystal Oscillator ...

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C8051F360/1/2/3/4/5/6/7/8/9 16.5. External Crystal Example If a crystal or ceramic resonator is used as an external oscillator source for the MCU, the circuit should be configured as shown in Figure 16.1, Option 1. The External Oscillator Frequency Control value (XFCN) ...

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External RC Example network is used as an external oscillator source for the MCU, the circuit should be configured as shown in Figure 16.1, Option 2. The capacitor should be no greater than 100 pF; however ...

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C8051F360/1/2/3/4/5/6/7/8/9 16.8. Phase-Locked Loop (PLL) A Phase-Locked-Loop (PLL) is included, which is used to multiply the internal oscillator or an external clock source to achieve higher CPU operating frequencies. The PLL circuitry is designed to produce an output frequency between ...

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Powering on and Initializing the PLL To set up and use the PLL as the system clock after power-up of the device, the following procedure should be implemented: Step 1. Ensure that the reference clock to be used (internal ...

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C8051F360/1/2/3/4/5/6/7/8/9 To shut down the PLL, the system clock should be switched to the internal oscillator or a stable external clock source, using the CLKSEL register. Next, disable the PLL by setting PLLEN (PLL0CN.1) to ‘0’. Finally, the PLL can ...

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SFR Definition 16.8. PLL0MUL: PLL Clock Scaler SFR Page: F SFR Address: 0xB1 R/W R/W R/W PLLN7 PLLN6 PLLN5 Bit7 Bit6 Bit5 Bits 7–0: PLLN7–0: PLL Multiplier. These bits select the multiplication factor of the divided PLL reference clock. When ...

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C8051F360/1/2/3/4/5/6/7/8/9 Table 16.3. PLL Frequency Characteristics –40 to +85 °C unless otherwise specified. Parameter Input Frequency (Divided Reference Frequency) PLL Output Frequency *Note: The maximum operating frequency of the C8051F366/7/8 MHz. Table 16.4. PLL Lock Timing Characteristics –40 ...

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... Ports and one 7-bit-wide Port. On the other devices (C8051F361/2/4/5/6/7/8/9), port pins are three byte-wide Ports and one partial port. Each of the Port pins can be defined as general-purpose I/O (GPIO) or analog input/output; Port pins P0.0–P3.7 can be assigned to one of the internal digital resources as shown in Figure 17 ...

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C8051F360/1/2/3/4/5/6/7/8/9 /WEAK-PULLUP PUSH-PULL /PORT-OUTENABLE PORT-OUTPUT Analog Select ANALOG INPUT PORT-INPUT Figure 17.2. Port I/O Cell Block Diagram 184 VIO VIO (WEAK) GND Rev. 1.0 PORT PAD ...

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... UART0. When a digital resource is selected, the least-significant unassigned Port pin is assigned to that resource (excluding UART0, which will be assigned to specific port pins (P0.1 and P0.2 in the C8051F360/3 devices, P0.4 and P0.5 in the C8051F361/2/4/5/6/7/8/9 devices Port pin is assigned, the Crossbar skips that pin when assigning the next selected resource. Additionally, the Crossbar will skip Port pins whose associated bits in the PnSKIP registers are set ...

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... UART0 pin assignments are fixed for bootloading purposes: UART TX0 is always assigned to P0.1 (C8051F360/3) or P0.4 (C8051F361/2/4/5/6/7/8/9); UART RX0 is always assigned to P0.2 (C8051F360/3) or P0.5 (C8051F361/2/4/5/6/7/8/9). Standard Port I/Os appear contiguously starting at P0.0 after prioritized functions and skipped pins are assigned. Important Note: The SPI can be operated in either 3-wire or 4-wire modes, depending on the state of the NSSMD1-NSSMD0 bits in register SPI0CN ...

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Port I/O Initialization Port I/O initialization consists of the following steps: Step 1. Select the input mode (analog or digital) for all Port pins, using the Port Input Mode register (PnMDIN). Step 2. Select the output mode (open-drain or ...

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... SPI I/O routed to Port pins. Note that the SPI can be assigned either GPIO pins. Bit 0: URT0E: UART I/O Output Enable 0: UART I/O unavailable at Port pin. 1: UART TX0, RX0 routed to Port pins P0.1 and P0.2 (C8051F360/3) or P0.4 and P0.5 (C8051F361/2/4/5/6/7/8/9). 188 R/W R/W R/W ...

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SFR Definition 17.2. XBR1: Port I/O Crossbar Register 1 SFR Page: F SFR Address: 0xE2 R/W R/W R/W WEAKPUD XBARE T1E Bit7 Bit6 Bit5 Bit 7: WEAKPUD: Port I/O Weak Pullup Disable. 0: Weak Pullups enabled (except for Ports whose ...

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C8051F360/1/2/3/4/5/6/7/8/9 17.3. General Purpose Port I/O Port pins that remain unassigned by the Crossbar and are not used by analog peripherals can be used for general purpose I/O. Ports P0-P3 are accessed through corresponding special function registers (SFRs) that are ...

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SFR Definition 17.4. P0MDIN: Port0 Input Mode SFR Page: F SFR Address: 0xF1 R/W R/W R/W Bit7 Bit6 Bit5 Bits 7–0: Analog Input Configuration Bits for P0.7-P0.0 (respectively). Port pins configured as analog inputs have their weak pullup, digital driver, ...

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C8051F360/1/2/3/4/5/6/7/8/9 SFR Definition 17.6. P0SKIP: Port0 Skip SFR Page: F SFR Address: 0xD4 R/W R/W R/W Bit7 Bit6 Bit5 Bits 7–0: P0SKIP[7:0]: Port0 Crossbar Skip Enable Bits. These bits select Port pins to be skipped by the Crossbar Decoder. Port ...

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SFR Definition 17.9. P1: Port1 SFR Page: all pages (bit addressable) SFR Address: 0x90 R/W R/W R/W P1.7 P1.6 P1.5 Bit7 Bit6 Bit5 Bits 7–0: P1.[7:0] Write - Output appears on I/O pins per Crossbar Registers. 0: Logic Low Output. ...

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C8051F360/1/2/3/4/5/6/7/8/9 SFR Definition 17.11. P1MDOUT: Port1 Output Mode SFR Page: F SFR Address: 0xA5 R/W R/W R/W Bit7 Bit6 Bit5 Bits 7–0: Output Configuration Bits for P1.7-P1.0 (respectively): ignored if corresponding bit in regis- ter P1MDIN is logic ‘0’. 0: ...

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SFR Definition 17.14. P1MASK: Port1 Mask SFR Page: 0 SFR Address: 0xE2 R/W R/W R/W Bit7 Bit6 Bit5 Bits 7–0: P1MASK[7:0]: Port1 Mask Value. These bits select which Port pins will be compared to the value stored in P1MAT. 0: ...

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C8051F360/1/2/3/4/5/6/7/8/9 SFR Definition 17.16. P2MDIN: Port2 Input Mode SFR Page: F SFR Address: 0xF3 R/W R/W R/W Bit7 Bit6 Bit5 Bits 7–0: Analog Input Configuration Bits for P2.7-P2.0 (respectively). Port pins configured as analog inputs have their weak pullup, digital ...

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SFR Definition 17.18. P2SKIP: Port2 Skip SFR Page: F SFR Address: 0xD6 R/W R/W R/W Bit7 Bit6 Bit5 Bits 7–0: P2SKIP[7:0]: Port2 Crossbar Skip Enable Bits. These bits select Port pins to be skipped by the Crossbar Decoder. Port pins ...

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C8051F360/1/2/3/4/5/6/7/8/9 SFR Definition 17.21. SFR Page: all pages (bit addressable) SFR Address: 0xB0 R/W R/W R/W P3.7 P3.6 P3.5 Bit7 Bit6 Bit5 Bits 7–0: P3.[7:0] Write - Output appears on I/O pins per Crossbar Registers. 0: Logic Low Output. 1: ...

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SFR Definition 17.23. SFR Page: F SFR Address: 0xAF R/W R/W R/W Bit7 Bit6 Bit5 Bits 7–0: Output Configuration Bits for P3.7-P3.0 (respectively): ignored if corresponding bit in regis- ter P3MDIN is logic ‘0’. 0: Corresponding P3.n Output is open-drain. ...

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C8051F360/1/2/3/4/5/6/7/8/9 SFR Definition 17.25. SFR Page: all pages SFR Address: 0xB5 R R/W R/W – P4.6 P4.5 Bit7 Bit6 Bit5 Bit 7: UNUSED. Read = 0b. Write = don’t care. Bits 6–0: P4.[6:0] Write - Output appears on I/O pins ...

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