C8051F581-IQ Silicon Laboratories Inc, C8051F581-IQ Datasheet
C8051F581-IQ
Manufacturer Part Number
C8051F581-IQ
Description
IC 8051 MCU 128K FLASH 48-QFP
Manufacturer
Silicon Laboratories Inc
Series
C8051F58xr
Datasheet
1.C8051F581-IQ.pdf
(1 pages)
Specifications of C8051F581-IQ
Program Memory Type
FLASH
Program Memory Size
128KB (128K x 8)
Package / Case
48-QFP
Mfg Application Notes
LIN Bootloader AppNote
Core Processor
8051
Core Size
8-Bit
Speed
50MHz
Connectivity
EBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
POR, PWM, Temp Sensor, WDT
Number Of I /o
40
Ram Size
8.25K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.25 V
Data Converters
A/D 32x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Processor Series
C8051F5x
Core
8051
Data Bus Width
8 bit
Data Ram Size
8448 B
Interface Type
I2C, SPI, UART
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
40
Number Of Timers
6
Operating Supply Voltage
1.8 V to 5.25 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F580DK
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit, 32 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1566
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
C8051F581-IQ
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
Company:
Part Number:
C8051F581-IQR
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
Analog Peripherals
12-Bit ADC, 5 V input signal; up to 32 external inputs
-
-
-
-
Built-in Temperature Sensor (±3 °C)
Three Comparators
Precision Internal Voltage Reference
V
On-Chip Debug
-
-
-
-
Temperature Range: –40 to +125 °C
Operating Voltage: 1.8 to 5.25 V
-
Development Kit: C8051F580DK
Automotive
DD
±1 LSB INL; guaranteed monotonic
Programmable throughput up to 200 ksps
Data-dependent windowed interrupt generator
Programmable gain maximizes input signal span
On-chip debug circuitry facilitates full speed, non-intrusive in-system
debug (no emulator required)
Provides breakpoints, single stepping, watch-points
Inspect/modify memory, registers, and stack
Superior performance to emulation systems using ICE-chips, target
pods, and sockets
Multiple power saving sleep and shutdown modes
Monitor/Brown-out Detector
C2CK/RST
VREGIN
GNDA
VDDA
GND
VDD
C2D
Internal Oscillator
Programming
Power On
Hardware
Voltage Regulator
Debug /
Reset
(±0.5%)
System Clock Setup
(LDO)
Reset
Clock Multiplier
50 MIPS, 128 kB Flash, 12-Bit ADC, 48-Pin Automotive MCU
CIP-51 8051 Controller
Copyright © 2008 by Silicon Laboratories
128 kB Flash Program
External Oscillator
XTAL1
Core (50 MHz)
256 Byte RAM
8 kB XRAM
Memory
XTAL2
SFR
Bus
High-Speed 8051 µC Core
-
-
Memory
-
-
Digital Peripherals
-
-
-
-
-
Clock Sources
-
-
Ordering Part Numbers
-
-
Pipelined instruction architecture; executes 70% of instructions in one or
two system clocks
Up to 50 MIPS throughput
128 kB Flash; in-system programmable; flexible security features
8448 bytes data RAM (256 + 8 kB)
Up to 40 digital I/O; all are 5 V push-pull
Hardware I
Two independent programmable 16-bit counter array with six capture/
compare modules
Six general-purpose 16-bit counter/timers
External Memory Interface (EMIF)
Internal programmable ±0.5% oscillator: Up to 50 MHz
External oscillator: Crystal, RC, C, or CMOS Clock
C8051F581-IM, 48-Pin QFN (RoHS-compliant), 7 x 7 mm
C8051F581-IQ, 48-Pin QFP (RoHS-compliant), 9 x 9 mm
VDD
Timers 0,
PCA/WDT
1,2,3,4,5
CP0, CP0A
CP2, CP2A
External Memory Interface
Comparator 0
Comparator 2
UART0
UART1
channel
12-bit
200ksps
ADC
Analog Peripherals
Digital Peripherals
2 x 6
SPI
I2C
Port I/O Configuration
Crossbar Control
Reference
Voltage
VREF
2
C, SPI™, and two UART serial ports available concurrently
+
+
-
-
M
A
U
X
CP1, CP1A
VREF
Comparator 1
Crossbar
Decoder
Priority
VDD
VREF
P0 – P3
Temp
Sensor
GND
+
-
Drivers
Drivers
Drivers
Drivers
Drivers
Port 0
Port 1
Port 2
Port 3
Port 4
C8051F581
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
P4.0
P4.1
P4.2
P4.3
P4.4
P4.5
P4.6
P4.7
VIO
2
2
11.21.2008
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