IC 8051 MCU 32K FLASH 100TQFP

C8051F046-GQ

Manufacturer Part NumberC8051F046-GQ
DescriptionIC 8051 MCU 32K FLASH 100TQFP
ManufacturerSilicon Laboratories Inc
SeriesC8051F04x
C8051F046-GQ datasheets
 


Specifications of C8051F046-GQ

Core Processor8051Core Size8-Bit
Speed25MHzConnectivityCAN, EBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART
PeripheralsBrown-out Detect/Reset, POR, PWM, Temp Sensor, WDTNumber Of I /o64
Program Memory Size32KB (32K x 8)Program Memory TypeFLASH
Ram Size4.25K x 8Voltage - Supply (vcc/vdd)2.7 V ~ 3.6 V
Data ConvertersA/D 13x10bOscillator TypeInternal
Operating Temperature-40°C ~ 85°CPackage / Case100-TQFP, 100-VQFP
Processor SeriesC8051F0xCore8051
Data Bus Width8 bitData Ram Size4.25 KB
Interface TypeCAN, SMBus, SPI, UARTMaximum Clock Frequency25 MHz
Number Of Programmable I/os64Number Of Timers5
Operating Supply Voltage2.7 V to 3.6 VMaximum Operating Temperature+ 85 C
Mounting StyleSMD/SMT3rd Party Development ToolsPK51, CA51, A51, ULINK2
Development Tools By SupplierC8051F040DKMinimum Operating Temperature- 40 C
On-chip Adc10 bit, 13 ChannelOn-chip Dac12 bit, 2 Channel
Package100TQFPDevice Core8051
Family NameC8051F04xMaximum Speed25 MHz
Lead Free Status / RoHS StatusLead free / RoHS CompliantEeprom Size-
Other names336-1211  
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Analog Peripherals
-
10 or 12-Bit SAR ADC
12-bit (C8051F040/1) or
10-bit (C8051F042/3/4/5/6/7) resolution
± 1 LSB INL, guaranteed no missing codes
Programmable throughput up to 100 ksps
13 External Inputs; single-ended or differential
SW programmable high voltage difference amplifier
Programmable amplifier gain: 16, 8, 4, 2, 1, 0.5
Data-dependent windowed interrupt generator
Built-in temperature sensor
-
8-bit SAR ADC (C8051F040/1/2/3 only)
Programmable throughput up to 500 ksps
8 External Inputs, single-ended or differential
Programmable amplifier gain: 4, 2, 1, 0.5
-
Two 12-bit DACs (C8051F040/1/2/3 only)
Can synchronize outputs to timers for jitter-free wave-
form generation
-
Three Analog Comparators
Programmable hysteresis/response time
-
Voltage Reference
-
Precision V
Monitor/Brown-Out Detector
DD
On-Chip JTAG Debug & Boundary Scan
-
On-chip debug circuitry facilitates full- speed, non-
intrusive in-circuit/in-system debugging
-
Provides breakpoints, single-stepping, watchpoints,
stack monitor; inspect/modify memory and registers
-
Superior performance to emulation systems using
ICE-chips, target pods, and sockets
-
IEEE1149.1 compliant boundary scan
-
Complete development kit
C8051F041/2/3
Rev. 1.5 12/05
C8051F040/1/2/3/4/5/6/7
Mixed Signal ISP Flash MCU Family
High-Speed 8051 µC Core
-
Pipelined instruction architecture; executes 70% of
instruction set in 1 or 2 system clocks
-
Up to 25 MIPS throughput with 25 MHz clock
-
20 vectored interrupt sources
Memory
-
4352 bytes internal data RAM (4 k + 256)
-
64 kB (C8051F040/1/2/3/4/5)
or 32 kB (C8051F046/7) Flash; in-system program-
mable in 512-byte sectors
-
External 64 kB data memory interface (programma-
ble multiplexed or non-multiplexed modes)
Digital Peripherals
-
8 byte-wide port I/O (C8051F040/2/4/6); 5 V tolerant
-
4 byte-wide port I/O (C8051F041/3/5/7); 5 V tolerant
-
Bosch Controller Area Network (CAN 2.0B), hard-
ware SMBus™ (I
two UART serial ports available concurrently
-
Programmable 16-bit counter/timer array with
6 capture/compare modules
-
5 general purpose 16-bit counter/timers
-
Dedicated watch-dog timer; bi-directional reset pin
Clock Sources
-
Internal calibrated programmable oscillator: 3 to
24.5 MHz
-
External oscillator: crystal, RC, C, or clock
-
Real-time clock mode using Timer 2, 3, 4, or PCA
Supply Voltage: 2.7 to 3.6 V
-
Multiple power saving sleep and shutdown modes
100-Pin and 64-Pin TQFP Packages Available
-
Temperature Range: –40 to +85 °C
ANALOG PERIPHERALS
CAN
TEMP
2.0B
SENSOR
12/10-bit
UART0
100 ksps
PGA
UART1
ADC
SMBus
VREF
SPI Bus
PCA
8-bit
HV
Timer 0
DIFF
500 ksps
PGA
AMP
ADC
Timer 1
Timer 2
12-Bit
+
+
+
DAC
12-Bit
Timer 3
DAC
-
-
-
Timer 4
VOLTAGE COMPARATORS
ONLY
HIGH-SPEED CONTROLLER CORE
8051 CPU
64 kB/32 kB
4352 B
(25 MIPS)
ISP FLASH
20
DEBUG
CLOCK
INTERRUPTS
CIRCUITRY
CIRCUIT
Copyright © 2005 by Silicon Laboratories
2
C™ Compatible), SPI™, and
DIGITAL I/O
Port 0
Port 1
Port 2
Port 3
Port 4
Port 5
Port 6
Port 7
64 pin
100 pin
JTAG
SRAM
SANITY
CONTROL
C8051F04x

C8051F046-GQ Summary of contents

  • Page 1

    ... MIPS throughput with 25 MHz clock - 20 vectored interrupt sources Memory - 4352 bytes internal data RAM ( 256 (C8051F040/1/2/3/4/5) (C8051F046/7) Flash; in-system program- mable in 512-byte sectors - External 64 kB data memory interface (programma- ble multiplexed or non-multiplexed modes) Digital Peripherals - 8 byte-wide port I/O (C8051F040/2/4/6 tolerant - 4 byte-wide port I/O (C8051F041/3/5/7) ...

  • Page 2

    C8051F040/1/2/3/4/5/6/7 2 Rev. 1.5 ...

  • Page 3

    Table of Contents 1. System Overview.................................................................................................... 19 1.1. CIP-51™ Microcontroller Core.......................................................................... 25 1.1.1. Fully 8051 Compatible.............................................................................. 25 1.1.2. Improved Throughput ............................................................................... 25 1.1.3. Additional Features .................................................................................. 26 1.2. On-Chip Memory............................................................................................... 27 1.3. JTAG Debug and Boundary Scan..................................................................... 28 1.4. Programmable ...

  • Page 4

    C8051F040/1/2/3/4/5/6/7 7.3.2. Window Detector in Differential Mode .................................................... 102 8. DACs, 12-Bit Voltage Mode (C8051F040/1/2/3 Only) ......................................... 105 8.1. DAC Output Scheduling.................................................................................. 106 8.1.1. Update Output On-Demand ................................................................... 106 8.1.2. Update Output Based on Timer Overflow .............................................. 106 8.2. DAC ...

  • Page 5

    Oscillator Drive Circuit...................................................................... 175 14.3.System Clock Selection.................................................................................. 175 14.4.External Crystal Example ............................................................................... 177 14.5.External RC Example ..................................................................................... 178 14.6.External Capacitor Example ........................................................................... 178 15. Flash Memory ....................................................................................................... 179 15.1.Programming The Flash Memory ................................................................... 179 15.2.Non-volatile Data Storage .............................................................................. 180 ...

  • Page 6

    C8051F040/1/2/3/4/5/6/7 18.1.2.Example Timing Calculation for 1 Mbit/Sec Communication ................. 229 18.2.CAN Registers................................................................................................ 231 18.2.1.CAN Controller Protocol Registers......................................................... 231 18.2.2.Message Object Interface Registers ...................................................... 231 18.2.3.Message Handler Registers................................................................... 232 18.2.4.CIP-51 MCU Special Function Registers ............................................... 232 18.2.5.Using CAN0ADR, CAN0DATH, and CANDATL ...

  • Page 7

    Masked Address ............................................................... 271 21.4.Broadcast Addressing .................................................................................... 271 21.5.Frame and Transmission Error Detection....................................................... 272 22. UART1.................................................................................................................... 277 22.1.Enhanced Baud Rate Generation................................................................... 278 22.2.Operational Modes ......................................................................................... 279 22.2.1.8-Bit UART ............................................................................................. 279 22.2.2.9-Bit UART ............................................................................................. 280 22.3.Multiprocessor Communications .................................................................... ...

  • Page 8

    C8051F040/1/2/3/4/5/6 OTES 8 Rev. 1.5 ...

  • Page 9

    List of Figures 1. System Overview Figure 1.1. C8051F040/2 Block Diagram ................................................................. 21 Figure 1.2. C8051F041/3 Block Diagram ................................................................. 22 Figure 1.3. C8051F044/6 Block Diagram ................................................................. 23 Figure 1.4. C8051F045/7 Block Diagram ................................................................. 24 Figure 1.5. Comparison of Peak MCU ...

  • Page 10

    C8051F040/1/2/3/4/5/6/7 Figure 6.5. ADC0 Equivalent Input Circuits.............................................................. 78 Figure 6.6. Temperature Sensor Transfer Function ................................................. 79 Figure 6.7. ADC0 Data Word Example .................................................................... 83 Figure 6.8. 10-Bit ADC0 Window Interrupt Example:  Right Justified Single-Ended Data ........................................................ 85 Figure 6.9. ...

  • Page 11

    External Data Memory Interface and On-Chip XRAM Figure 16.1. Multiplexed Configuration Example.................................................... 191 Figure 16.2. Non-multiplexed Configuration Example ............................................ 192 Figure 16.3. EMIF Operating Modes ...................................................................... 193 Figure 16.4. Non-multiplexed 16-bit MOVX Timing ................................................ 196 Figure 16.5. Non-multiplexed 8-bit ...

  • Page 12

    C8051F040/1/2/3/4/5/6/7 22. UART1 Figure 22.1. UART1 Block Diagram ....................................................................... 277 Figure 22.2. UART1 Baud Rate Logic .................................................................... 278 Figure 22.3. UART Interconnect Diagram .............................................................. 279 Figure 22.4. 8-Bit UART Timing Diagram............................................................... 279 Figure 22.5. 9-Bit UART Timing Diagram............................................................... 280 Figure ...

  • Page 13

    List of Tables 1. System Overview Table 1.1. Product Selection Guide ......................................................................... 20 2. Absolute Maximum Ratings Table 2.1. Absolute Maximum Ratings* .................................................................. 35 3. Global DC Electrical Characteristic Table 3.1. Global DC Electrical Characteristics ....................................................... 36 4. Pinout and ...

  • Page 14

    C8051F040/1/2/3/4/5/6/7 18. Controller Area Network (CAN0) Table 18.1. Background System Information ........................................................ 229 Table 18.2. CAN Register Index and Reset Values .............................................. 233 19. System Management BUS/I Table 19.1. SMB0STA Status Codes and States .................................................. 252 20. Enhanced Serial Peripheral ...

  • Page 15

    List of Registers SFR Definition 5.1. AMX0CF: AMUX0 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 49 SFR Definition 5.2. AMX0SL: ...

  • Page 16

    C8051F040/1/2/3/4/5/6/7 SFR Definition 12.3. SFR Next Register: SFRNEXT . . . . . . . . . . . . . . . . . . . . . . . . . 143 SFR Definition 12.4. SFR Last Register: ...

  • Page 17

    SFR Definition 17.19. P5MDOUT: Port5 Output Mode . . . . . . . . . . . . . . . . . . . . . . . . 223 SFR Definition 17.20. P6: Port6 Data . . ...

  • Page 18

    C8051F040/1/2/3/4/5/6/7 SFR Definition 24.7. PCA0CPHn: PCA0 Capture Module High Byte . . . . . . . . . . . . . 316 JTAG Register Definition 25.1. IR: JTAG Instruction Register . . . . . . . . ...

  • Page 19

    ... True 8-bit 500 ksps 8-channel ADC with PGA and analog multiplexer (C8051F040/1/2/3) • Two 12-bit DACs with programmable update scheduling (C8051F040/1/2/3) • (C8051F040/1/2/3/4/ (C8051F046/7) of in-system programmable Flash memory • 4352 (4096 + 256) bytes of on-chip RAM • External Data Memory Interface with 64 kB address space 2 • ...

  • Page 20

    ... C8051F044- 4352    C8051F045 4352    C8051F045- 4352    C8051F046 4352    C8051F046- 4352    C8051F047 4352    C8051F047- 4352 20      ...

  • Page 21

    VDD VDD Digital Power VDD DGND DGND DGND AV+ AV+ Analog Power AV+ AGND AGND AGND TCK Boundary Scan JTAG TMS TDI Logic Debug HW TDO Reset /RST V DD WDT MONEN Monitor External XTAL1 Oscillator XTAL2 Circuit System Clock ...

  • Page 22

    C8051F040/1/2/3/4/5/6/7 VDD VDD Digital Power VDD DGND DGND DGND AV+ Analog Power AV+ AGND AGND TCK Boundary Scan JTAG TMS TDI Logic Debug HW TDO Reset /RST V DD WDT MONEN Monitor External XTAL1 Oscillator XTAL2 Circuit System Clock VREF ...

  • Page 23

    VDD VDD Digital Power VDD DGND DGND DGND AV+ AV+ Analog Power AV+ AGND AGND AGND TCK Boundary Scan JTAG TMS TDI Logic Debug HW TDO Reset /RST V DD WDT MONEN Monitor External XTAL1 Oscillator XTAL2 Circuit System Clock ...

  • Page 24

    C8051F040/1/2/3/4/5/6/7 VDD VDD Digital Power VDD DGND DGND DGND AV+ Analog Power AV+ AGND AGND TCK Boundary Scan JTAG TMS TDI Logic Debug HW TDO Reset /RST V DD WDT MONEN Monitor External XTAL1 Oscillator XTAL2 Circuit System Clock VREF ...

  • Page 25

    CIP-51™ Microcontroller Core 1.1.1. Fully 8051 Compatible The C8051F04x family of devices utilizes Silicon Labs' proprietary CIP-51 microcontroller core. The CIP fully compatible with the MCS-51™ instruction set; standard 803x/805x assemblers and compilers can be used to ...

  • Page 26

    C8051F040/1/2/3/4/5/6/7 1.1.3. Additional Features The C8051F04x MCU family includes several key enhancements to the CIP-51 core and peripherals to improve overall performance and ease of use in end applications. The extended interrupt handler provides 20 interrupt sources into the CIP-51 ...

  • Page 27

    ... EMIF). The EMIF is also configurable for multiplexed or non-multiplexed address/data lines. The MCU's program memory consists (C8051F040/1/2/3/4/ (C8051F046/7) of Flash. This memory may be reprogrammed in-system in 512 byte sectors, and requires no special off-chip pro- gramming voltage ...

  • Page 28

    C8051F040/1/2/3/4/5/6/7 1.3. JTAG Debug and Boundary Scan The C8051F04x family has on-chip JTAG boundary scan and debug circuitry that provides non-intrusive, full speed, in-circuit debugging using the production part installed in the end application, via the four-pin JTAG interface. The ...

  • Page 29

    Programmable Digital I/O and Crossbar The standard 8051 Ports ( and 3) are available on the MCUs. The C8051F040/2/4/6 have 4 addi- tional 8-bit ports ( and 7) for a total of 64 general-purpose I/O ...

  • Page 30

    C8051F040/1/2/3/4/5/6/7 1.5. Programmable Counter Array The C8051F04x MCU family includes an on-board Programmable Counter/Timer Array (PCA) in addition to the five 16-bit general purpose counter/timers. The PCA consists of a dedicated 16-bit counter/timer time base with six programmable capture/compare modules. ...

  • Page 31

    Controller Area Network The C8051F04x family of devices feature a Controller Area Network (CAN) controller that implements serial communication using the CAN protocol. The CAN controller facilitates communication on a CAN net- work in accordance with the Bosch specification ...

  • Page 32

    C8051F040/1/2/3/4/5/6/7 1.8. 12/10-Bit Analog to Digital Converter The C8051F040/1 devices have an on-chip 12-bit SAR ADC (ADC0) with a 9-channel input multiplexer and programmable gain amplifier. With a maximum throughput of 100 ksps, the ADC offers true 12-bit per- formance ...

  • Page 33

    Analog to Digital Converter (C8051F040/1/2/3 Only) The C8051F040/1/2/3 devices have an on-board 8-bit SAR ADC (ADC2) with an 8-channel input multi- plexer and programmable gain amplifier. This ADC features a 500 ksps maximum throughput and true 8- bit ...

  • Page 34

    C8051F040/1/2/3/4/5/6/7 1.10. Comparators and DACs Each C8051F040/1/2/3 MCU has two 12-bit DACs, and all C8051F04x devices have three comparators on chip. The MCU data and control interface to each comparator and DAC is via the Special Function Regis- ters. The ...

  • Page 35

    Absolute Maximum Ratings Table 2.1. Absolute Maximum Ratings* Parameter Ambient temperature under bias Storage Temperature Voltage on any Pin (except V , Port I/O, and JTAG DD pins) with respect to DGND Voltage on any Port I/O Pin, /RST, ...

  • Page 36

    C8051F040/1/2/3/4/5/6/7 3. Global DC Electrical Characteristic Table 3.1. Global DC Electrical Characteristics –40 to +85 °C, 25 MHz System Clock unless otherwise specified. Parameter 1 Analog Supply Voltage Analog Supply Current Internal REF, ADC, DAC, Com- parators all active Analog ...

  • Page 37

    Pinout and Package Definitions Pin Numbers Name F040/2/4/6 F041/3/5/7 V 37, 64, 90 24, 41 DGND 38, 63, 89 25, 40, 56 AV AGND 9, 10 TMS 1 58 ...

  • Page 38

    C8051F040/1/2/3/4/5/6/7 Table 4.1. Pin Definitions (Continued) Pin Numbers Name F040/2/4/6 F041/3/5/7 AIN0 AIN0 AIN0 HVCAP 22 13 HVREF 23 14 HVAIN HVAIN CANTX 7 2 CANRX 6 1 DAC0 100 ...

  • Page 39

    Table 4.1. Pin Definitions (Continued) Pin Numbers Name F040/2/4/6 F041/3/5/7 P1.0/AIN2.0/ P1.1/AIN2.1/ P1.2/AIN2. A10 P1.3/AIN2. A11 P1.4/AIN2. A12 P1.5/AIN2. A13 P1.6/AIN2. A14 P1.7/AIN2. A15 ...

  • Page 40

    C8051F040/1/2/3/4/5/6/7 Table 4.1. Pin Definitions (Continued) Pin Numbers Name F040/2/4/6 F041/3/5/7 P3.0/AD0/ P3.1/AD1/ P3.2/AD2/ P3.3/AD3/ P3.4/AD4/ P3.5/AD5/ P3.6/AD6/ P3.7/AD7/ P4.0 98 P4.1 97 P4.2 ...

  • Page 41

    Table 4.1. Pin Definitions (Continued) Pin Numbers Name F040/2/4/6 F041/3/5/7 P4.4 94 P4.5/ALE 93 P4.6/RD 92 P4.7/WR 91 P5.0/A8 88 P5.1/A9 87 P5.2/A10 86 P5.3/A11 85 P5.4/A12 84 P5.5/A13 83 P5.6/A14 82 P5.7/A15 81 P6.0/A8m/A0 80 P6.1/A9m/A1 79 P6.2/A10m/A2 78 ...

  • Page 42

    C8051F040/1/2/3/4/5/6/7 Table 4.1. Pin Definitions (Continued) Pin Numbers Name F040/2/4/6 F041/3/5/7 P6.4/A12m/A4 76 P6.5/A13m/A5 75 P6.6/A14m/A6 74 P6.7/A15m/A7 73 P7.0/AD0/D0 72 P7.1/AD1/D1 71 P7.2/AD2/D2 70 P7.3/AD3/D3 69 P7.4/AD4/D4 68 P7.5/AD5/D5 67 P7.6/AD6/D6 66 P7.7/AD7/ Type Description D I/O ...

  • Page 43

    TMS 1 TCK 2 TDI 3 TDO 4 /RST 5 CANRX 6 CANTX 7 AV+ 8 AGND 9 AGND 10 AV+ 11 VREF 12 C8051F040/2/4/6 AGND 13 AV+ 14 VREFD 15 VREF0 16 VREF2 17 AIN0.0 18 AIN0.1 19 AIN0.2 ...

  • Page 44

    C8051F040/1/2/3/4/5/6/7 100 PIN 1 DESIGNATOR Figure 4.2. TQFP-100 Package Drawing Rev. 1.5 MIN NOM MAX (mm) (mm) (mm 1.20 A1 0.05 - 0.15 A2 0.95 ...

  • Page 45

    CANRX 1 CANTX 2 AV+ 3 AGND 4 AGND 5 AV+ 6 VREF 7 VREFA 8 C8051F041/3/5/7 AIN0.0 9 AIN0.1 10 AIN0.2 11 AIN0.3 12 HVCAP 13 HVREF 14 HVAIN+ 15 HVAIN- 16 Figure 4.3. TQFP-64 Pinout Diagram C8051F040/1/2/3/4/5/6/7 Rev. ...

  • Page 46

    C8051F040/1/2/3/4/5/6 PIN 1 DESIGNATOR Figure 4.4. TQFP-64 Package Drawing Rev. 1.5 MIN NOM MAX (mm) (mm) (mm 1.20 A1 0.05 - 0.15 A2 0.95 ...

  • Page 47

    ADC (ADC0, C8051F040/1 Only) The ADC0 subsystem for the C8051F040/1 consists of a 9-channel, configurable analog multiplexer (AMUX0), a programmable gain amplifier (PGA0), and a 100 ksps, 12-bit successive-approximation-regis- ter ADC with integrated track-and-hold and Programmable Window Detector ...

  • Page 48

    C8051F040/1/2/3/4/5/6/7 5.1.1. Analog Input Configuration The analog multiplexer routes signals from external analog input pins, Port 3 I/O pins (See “17.1.5. Configuring Port 1, 2, and 3 Pins as Analog Inputs” on page Amplifier, and an on-chip temperature sensor as ...

  • Page 49

    SFR Definition 5.1. AMX0CF: AMUX0 Configuration Bit7 Bit6 Bit5 Bits7-4: UNUSED. Read = 0000b; Write = don’t care Bit3: PORT3IC: Port 3 even/odd Pin Input Pair Configuration Bit 0: Port 3 even and odd ...

  • Page 50

    C8051F040/1/2/3/4/5/6/7 Table 5.1. AMUX Selection Chart (AMX0AD3–0 and AMX0CF3–0 bits) 0000 0001 0000 AIN0.0 AIN0.1 +(AIN0.0) 0001 -(AIN0.1) 0010 AIN0.0 AIN0.1 +(AIN0.0) 0011 -(AIN0.1) 0100 AIN0.0 AIN0.1 +(AIN0.0) 0101 -(AIN0.1) 0110 AIN0.0 AIN0.1 +(AIN0.0) 0111 -(AIN0.1) 1000 AIN0.0 AIN0.1 +(AIN0.0) ...

  • Page 51

    SFR Definition 5.3. AMX0PRT: Port 3 Pin Selection R/W R/W R/W PAIN7EN PAIN6EN PAIN5EN PAIN4EN PAIN3EN PAIN2EN PAIN1EN PAIN0EN 00000000 Bit7 Bit6 Bit5 Bit7: PAIN7EN: Pin 7 Analog Input Enable Bit 0: P3.7 is not selected as an analog input ...

  • Page 52

    C8051F040/1/2/3/4/5/6/7 5.2. High-Voltage Difference Amplifier The High Voltage Difference Amplifier (HVDA) can be used to measure high differential voltages peak-to-peak, reject high common-mode voltages up to ±60 V, and condition the signal voltage range to be ...

  • Page 53

    SFR Definition 5.4. HVA0CN: High Voltage Difference Amplifier Control R HVDAEN - - Bit7 Bit6 Bit5 Bit7: HVDAEN: High Voltage Difference Amplifier (HVDA) Enable Bit. 0: The HVDA is disabled. 1: The HVDA is enabled. Bits6-3: Reserved. Bits2-0: ...

  • Page 54

    C8051F040/1/2/3/4/5/6/7 5.3. ADC Modes of Operation ADC0 has a maximum conversion speed of 100 ksps. The ADC0 conversion clock is derived from the sys- tem clock divided by the value held in the ADC0SC bits of register ADC0CF. 5.3.1. Starting ...

  • Page 55

    A. ADC Timing for External Trigger Source CNVSTR (AD0CM[1:0]=10) SAR Clocks Low Power ADC0TM=1 or Convert ADC0TM=0 Track Or Convert B. ADC Timing for Internal Trigger Sources Timer 2, Timer 3 Overflow; Write '1' to AD0BUSY (AD0CM[1:0]=00, 01, 11) 1 ...

  • Page 56

    C8051F040/1/2/3/4/5/6/7 5.3.3. Settling Time Requirements A minimum tracking time is required before an accurate conversion can be performed. This tracking time is determined by the ADC0 MUX resistance, the ADC0 sampling capacitance, any external source resis- tance, and the accuracy ...

  • Page 57

    Figure 5.6. Temperature Sensor Transfer Function C8051F040/1/2/3/4/5/6 0.00286(TEMP ) + 0.776 TEMP C for PGA Gain = 1 50 100 Rev. 1.5 (Celsius) 57 ...

  • Page 58

    C8051F040/1/2/3/4/5/6/7 SFR Definition 5.5. ADC0CF: ADC0 Configuration Register R/W R/W R/W AD0SC4 AD0SC3 AD0SC2 Bit7 Bit6 Bit5 Bits7-3: AD0SC4-0: ADC0 SAR Conversion Clock Period Bits SAR Conversion clock is derived from system clock by the following equation, where AD0SC refers ...

  • Page 59

    SFR Definition 5.6. ADC0CN: ADC0 Control R/W R/W R/W AD0EN AD0TM AD0INT AD0BUSY AD0CM1 AD0CM0 Bit7 Bit6 Bit5 Bit7: AD0EN: ADC0 Enable Bit. 0: ADC0 Disabled. ADC0 is in low-power shutdown. 1: ADC0 Enabled. ADC0 is active and ready for ...

  • Page 60

    C8051F040/1/2/3/4/5/6/7 SFR Definition 5.7. ADC0H: ADC0 Data Word MSB R/W R/W R/W Bit7 Bit6 Bit5 Bits7-0: ADC0 Data Word High-Order Bits. For AD0LJST = 0: Bits 7-4 are the sign extension of Bit3. Bits 3-0 are the upper 4 bits ...

  • Page 61

    ADC0 Data Word appears in the ADC0 Data Word Registers as follows: ADC0H[3:0]:ADC0L[7:0], if AD0LJST = 0 (ADC0H[7:4] will be sign-extension of ADC0H.3 for a differential reading, otherwise = 0000b). ADC0H[7:0]:ADC0L[7:4], if AD0LJST = 1 (ADC0L[3:0] = 0000b). Example: ...

  • Page 62

    C8051F040/1/2/3/4/5/6/7 5.4. ADC0 Programmable Window Detector The ADC0 Programmable Window Detector continuously compares the ADC0 output to user-programmed limits, and notifies the system when an out-of-bound condition is detected. This is especially effective in an interrupt-driven system, saving code space ...

  • Page 63

    SFR Definition 5.12. ADC0LTL: ADC0 Less-Than Data Low Byte R/W R/W R/W Bit7 Bit6 Bit5 Bits7-0: Low byte of ADC0 Less-Than Data Word. Input Voltage ADC Data (AD0 - AGND) Word REF x (4095/4096) 0x0FFF AD0WINT not affected 0x0201 REF ...

  • Page 64

    C8051F040/1/2/3/4/5/6/7 Input Voltage ADC Data (AD0 - AD1) Word REF x (2047/2048) 0x07FF AD0WINT not affected 0x0101 REF x (256/2048) 0x0100 ADC0LTH:ADC0LTL 0x00FF AD0WINT=1 0x0000 REF x (-1/2048) 0xFFFF ADC0GTH:ADC0GTL 0xFFFE AD0WINT not affected 0xF800 -REF Given: AMX0SL = 0x00, ...

  • Page 65

    Input Voltage ADC Data (AD0 - AGND) Word REF x (4095/4096) 0xFFF0 AD0WINT not affected 0x2010 REF x (512/4096) 0x2000 ADC0LTH:ADC0LTL 0x1FF0 AD0WINT=1 0x1010 REF x (256/4096) 0x1000 ADC0GTH:ADC0GTL 0x0FF0 AD0WINT not affected 0x0000 0 Given: AMX0SL = 0x00, AMX0CF ...

  • Page 66

    C8051F040/1/2/3/4/5/6/7 Input Voltage ADC Data (AD0 - AD1) Word REF x (2047/2048) 0x7FF0 AD0WINT not affected 0x1010 REF x (256/2048) 0x1000 ADC0LTH:ADC0LTL 0x0FF0 AD0WINT=1 0x0000 REF x (-1/2048) 0xFFF0 ADC0GTH:ADC0GTL 0xFFE0 AD0WINT not affected 0x8000 -REF Given: AMX0SL = 0x00, ...

  • Page 67

    Table 5.2. 12-Bit ADC0 Electrical Characteristics V = 3.0 V, AV+ = 3.0 V, VREF = 2.40 V (REFBE = 0), PGA Gain = 1, –40 to +85 °C unless otherwise specified. DD Parameter DC Accuracy Resolution Integral Nonlinearity Differential ...

  • Page 68

    C8051F040/1/2/3/4/5/6/7 Table 5.3. High-Voltage Difference Amplifier Electrical Characteristics V = 3.0 V, AV 3.0 V, –40 to +85 °C unless otherwise specified. DD REF Parameter Analog Inputs Differential range Common Mode Range Analog Output Output ...

  • Page 69

    ADC (ADC0, C8051F042/3/4/5/6/7 Only) The ADC0 subsystem for the C8051F042/3/4/5/6/7 consists of a 9-channel, configurable analog multi- plexer (AMUX0), a programmable gain amplifier (PGA0), and a 100 ksps, 10-bit successive-approxima- tion-register ADC with integrated track-and-hold and Programmable Window ...

  • Page 70

    C8051F040/1/2/3/4/5/6/7 6.1.1. Analog Input Configuration The analog multiplexer routes signals from external analog input pins, Port 3 I/O pins (programmed to be analog inputs), a High Voltage Difference Amplifier, and an on-chip temperature sensor as shown in Figure 6.2. AIN0.0 ...

  • Page 71

    SFR Definition 6.1. AMX0CF: AMUX0 Configuration Bit7 Bit6 Bit5 Bits7-4: UNUSED. Read = 0000b; Write = don’t care Bit3: PORT3IC: Port 3 even/odd Pin Input Pair Configuration Bit 0: Port 3 even and odd ...

  • Page 72

    C8051F040/1/2/3/4/5/6/7 Table 6.1. AMUX Selection Chart (AMX0AD3-0 and AMX0CF3-0 bits) 0000 0001 0000 AIN0.0 AIN0.1 +(AIN0.0) 0001 -(AIN0.1) 0010 AIN0.0 AIN0.1 +(AIN0.0) 0011 -(AIN0.1) 0100 AIN0.0 AIN0.1 +(AIN0.0) 0101 -(AIN0.1) 0110 AIN0.0 AIN0.1 +(AIN0.0) 0111 -(AIN0.1) 1000 AIN0.0 AIN0.1 +(AIN0.0) ...

  • Page 73

    SFR Definition 6.3. AMX0PRT: Port 3 Pin Selection R/W R/W R/W PAIN7EN PAIN6EN PAIN5EN PAIN4EN PAIN3EN PAIN2EN PAIN1EN PAIN0EN 00000000 Bit7 Bit6 Bit5 Bit7: PAIN7EN: Pin 7 Analog Input Enable Bit 0: P3.7 is not selected as an analog input ...

  • Page 74

    C8051F040/1/2/3/4/5/6/7 6.2. High-Voltage Difference Amplifier The High-Voltage Difference Amplifier (HVDA) can be used to measure high differential voltages peak-to-peak, reject high common-mode voltages up to ±60 V, and condition the signal voltage range to be suitable ...

  • Page 75

    SFR Definition 6.4. HVA0CN: High Voltage Difference Amplifier Control R HVDAEN - - Bit7 Bit6 Bit5 Bit7: HVDAEN: High Voltage Difference Amplifier (HVDA) Enable Bit. 0: The HVDA is disabled. 1: The HVDA is enabled. Bits6-3: Reserved. Bits2-0: ...

  • Page 76

    C8051F040/1/2/3/4/5/6/7 6.3. ADC Modes of Operation ADC0 has a maximum conversion speed of 100 ksps. The ADC0 conversion clock is derived from the sys- tem clock divided by the value held in the ADC0SC bits of register ADC0CF. 6.3.1. Starting ...

  • Page 77

    A. ADC Timing for External Trigger Source CNVSTR (AD0CM[1:0]=10) SAR Clocks Low Power ADC0TM=1 or Convert ADC0TM=0 Track Or Convert B. ADC Timing for Internal Trigger Sources Timer 2, Timer 3 Overflow; Write '1' to AD0BUSY (AD0CM[1:0]=00, 01, 11) 1 ...

  • Page 78

    C8051F040/1/2/3/4/5/6/7 6.3.3. Settling Time Requirements A minimum tracking time is required before an accurate conversion can be performed. This tracking time is determined by the ADC0 MUX resistance, the ADC0 sampling capacitance, any external source resis- tance, and the accuracy ...

  • Page 79

    Figure 6.6. Temperature Sensor Transfer Function C8051F040/1/2/3/4/5/6 0.00286(TEMP ) + 0.776 TEMP C for PGA Gain = 1 50 100 Rev. 1.5 (Celsius) 79 ...

  • Page 80

    C8051F040/1/2/3/4/5/6/7 SFR Definition 6.5. ADC0CF: ADC0 Configuration R/W R/W R/W AD0SC4 AD0SC3 AD0SC2 Bit7 Bit6 Bit5 Bits7-3: AD0SC4-0: ADC0 SAR Conversion Clock Period Bits SAR Conversion clock is derived from system clock by the following equation, where AD0SC refers to ...

  • Page 81

    SFR Definition 6.6. ADC0CN: ADC0 Control R/W R/W R/W AD0EN AD0TM AD0INT AD0BUSY AD0CM1 AD0CM0 Bit7 Bit6 Bit5 Bit7: AD0EN: ADC0 Enable Bit. 0: ADC0 Disabled. ADC0 is in low-power shutdown. 1: ADC0 Enabled. ADC0 is active and ready for ...

  • Page 82

    C8051F040/1/2/3/4/5/6/7 SFR Definition 6.7. ADC0H: ADC0 Data Word MSB R/W R/W R/W Bit7 Bit6 Bit5 Bits7-0: ADC0 Data Word High-Order Bits. For AD0LJST = 0: Bits 7-2 are the sign extension of Bit 1. Bits 0 and 1 are the ...

  • Page 83

    ADC Data Word appears in the ADC Data Word Registers as follows: ADC0H[1:0]:ADC0L[7:0], if ADLJST = 0 (ADC0H[7:2] will be sign-extension of ADC0H.1 for a differential reading, otherwise = 000000b). ADC0H[7:0]:ADC0L[7:6], if ADLJST = 1 (ADC0L[5:0] = 000000b). Example: ...

  • Page 84

    C8051F040/1/2/3/4/5/6/7 6.4. ADC0 Programmable Window Detector The ADC0 Programmable Window Detector continuously compares the ADC0 output to user-programmed limits, and notifies the system when an out-of-bound condition is detected. This is especially effective in an interrupt-driven system, saving code space ...

  • Page 85

    SFR Definition 6.12. ADC0LTL: ADC0 Less-Than Data Low Byte R/W R/W R/W Bit7 Bit6 Bit5 Bits7-0: Low byte of ADC0 Less-Than Data Word. Input Voltage ADC Data (AD0 - AGND) Word REF x (1023/1024) 0x03FF AD0WINT not affected 0x0201 REF ...

  • Page 86

    C8051F040/1/2/3/4/5/6/7 Input Voltage ADC Data (AD0 - AD1) Word REF x (511/512) 0x01FF AD0WINT not affected 0x0101 REF x (256/512) 0x0100 ADC0LTH:ADC0LTL 0x00FF AD0WINT=1 0x0000 REF x (-1/512) 0xFFFF ADC0GTH:ADC0GTL 0xFFFE AD0WINT not affected 0xFE00 -REF Given: AMX0SL = 0x00, ...

  • Page 87

    Input Voltage ADC Data (AD0 - AGND) Word REF x (1023/1024) 0xFFC0 AD0WINT not affected 0x8040 REF x (512/1024) 0x8000 ADC0LTH:ADC0LTL 0x7FC0 AD0WINT=1 0x4040 REF x (256/1024) 0x4000 ADC0GTH:ADC0GTL 0x3FC0 AD0WINT not affected 0x0000 0 Given: AMX0SL = 0x00, AMX0CF ...

  • Page 88

    C8051F040/1/2/3/4/5/6/7 Input Voltage ADC Data (AD0 - AD1) Word REF x (511/512) 0x7FC0 AD0WINT not affected 0x4040 REF x (256/512) 0x4000 ADC0LTH:ADC0LTL 0x3FC0 AD0WINT=1 0x0000 REF x (-1/512) 0xFFC0 ADC0GTH:ADC0GTL 0xFF80 AD0WINT not affected 0x8000 -REF Given: AMX0SL = 0x00, ...

  • Page 89

    Table 6.2. 10-Bit ADC0 Electrical Characteristics V = 3.0 V, AV 2.40 V (REFBE = 0), PGA Gain = 1, –40 to +85 °C unless otherwise specified. DD REF Parameter DC Accuracy Resolution Integral Nonlinearity ...

  • Page 90

    C8051F040/1/2/3/4/5/6/7 Table 6.3. High-Voltage Difference Amplifier Electrical Characteristics V = 3.0 V, AV 3.0 V, –40 to +85 °C unless otherwise specified. DD REF Parameter Analog Inputs Differential range Common Mode Range Analog Output Output ...

  • Page 91

    ADC (ADC2, C8051F040/1/2/3 Only) The ADC2 subsystem for the C8051F040/1/2/3 consists of an 8-channel, configurable analog multiplexer, a programmable gain amplifier, and a 500 ksps, 8-bit successive-approximation-register ADC with inte- grated track-and-hold (see block diagram in Figure 7.1). ...

  • Page 92

    C8051F040/1/2/3/4/5/6/7 7.2. ADC2 Modes of Operation ADC2 has a maximum conversion speed of 500 ksps. The ADC2 conversion clock (SAR2 clock divided version of the system clock, determined by the AD2SC bits in the ADC2CF register (system clock ...

  • Page 93

    A. ADC Timing for External Trigger Source CNVSTR2/CNVSTR0 (AD2CM[2:0]=010) SAR2 Clocks Low Power AD2TM=1 or Convert AD2TM=0 Track or Convert B. ADC Timing for Internal Trigger Source Write '1' to AD2BUSY, Timer 3 Overflow, Timer 2 Overflow, Write '1' to ...

  • Page 94

    C8051F040/1/2/3/4/5/6/7 7.2.3. Settling Time Requirements A minimum tracking time is required before an accurate conversion can be performed. This tracking time is determined by the ADC2 MUX resistance, the ADC2 sampling capacitance, any external source resis- tance, and the accuracy ...

  • Page 95

    SFR Definition 7.1. AMX2CF: AMUX2 Configuration Bit7 Bit6 Bit5 Bits7-4: UNUSED. Read = 0000b; Write = don’t care Bit3: PIN67IC: P1.6, P1.7 Input Pair Configuration Bit 0: P1.6 and P1.7 are independent single-ended inputs ...

  • Page 96

    C8051F040/1/2/3/4/5/6/7 Table 7.1. AMUX Selection Chart (AMX2AD2-0 and AMX2CF3-0 bits) 000 001 0000 P1.0 P1.1 +(P1.0) -(P1.0) 0001 -(P1.1) +(P1.1) 0010 P1.0 P1.1 +(P1.0) -(P1.0) 0011 -(P1.1) +(P1.1) 0100 P1.0 P1.1 +(P1.0) -(P1.0) 0101 -(P1.1) +(P1.1) 0110 P1.0 P1.1 +(P1.0) ...

  • Page 97

    SFR Definition 7.3. ADC2CF: ADC2 Configuration R/W R/W R/W AD2SC4 AD2SC3 AD2SC2 Bit7 Bit6 Bit5 Bits7-3: AD2SC4-0: ADC2 SAR Conversion Clock Period Bits SAR Conversion clock is derived from system clock by the following equation, where AD2SC refers to the ...

  • Page 98

    C8051F040/1/2/3/4/5/6/7 SFR Definition 7.4. ADC2CN: ADC2 Control R/W R/W R/W AD2EN AD2TM AD2INT AD2BUSY AD2CM2 AD2CM1 Bit7 Bit6 Bit5 Bit7: AD2EN: ADC2 Enable Bit. 0: ADC2 Disabled. ADC2 is in low-power shutdown. 1: ADC2 Enabled. ADC2 is active and ready ...

  • Page 99

    SFR Definition 7.5. ADC2: ADC2 Data Word R/W R/W R/W Bit7 Bit6 Bit5 Bits7-0: ADC2 Data Word. 8-bit ADC Data Word appears in the ADC2 Data Word Register as follows: Example: ADC2 Data Word Conversion Map, AIN1.0 Input (AMX2SL = ...

  • Page 100

    C8051F040/1/2/3/4/5/6/7 7.3. ADC2 Programmable Window Detector The ADC2 Programmable Window Detector continuously compares the ADC2 output to user-programmed limits, and notifies the system when an out-of-bound condition is detected. This is especially effective in an interrupt-driven system, saving code space ...

  • Page 101

    ADC2 Input Voltage (P1.x - GND) REF x (255/256) 0xFF AD2WINT not affected 0x21 REF x (32/256) 0x20 ADC2LT 0x1F 0x11 REF x (16/256) 0x10 ADC2GT 0x0F AD2WINT not affected 0x00 0 Figure 7.5. ADC Window Compare Examples, Single-Ended Mode ...

  • Page 102

    C8051F040/1/2/3/4/5/6/7 7.3.2. Window Detector in Differential Mode Figure 7.6 shows two example window comparisons for differential mode, with ADC2LT = 0x10 (+16d) and ADC2GT = 0xFF (–1d). Notice that in Differential mode, the codes vary from –VREF to VREF x ...

  • Page 103

    Table 7.2. ADC2 Electrical Characteristics V = 3.0 V, AV 2.40 V (REFBE = 0), PGA2 = 1, –40 to +85 °C unless otherwise specified. DD REF2 Parameter DC Accuracy Resolution Integral Nonlinearity Differential Nonlinearity ...

  • Page 104

    C8051F040/1/2/3/4/5/6/7 104 Rev. 1.5 ...

  • Page 105

    DACs, 12-Bit Voltage Mode (C8051F040/1/2/3 Only) Each C8051F040/1/2/3 devices include two on-chip 12-bit voltage-mode Digital-to-Analog Converters (DACs). Each DAC has an output swing (VREF – 1 LSB) for a corresponding input code range of 0x000 ...

  • Page 106

    C8051F040/1/2/3/4/5/6/7 8.1. DAC Output Scheduling Each DAC features a flexible output update mechanism which allows for seamless full-scale changes and supports jitter-free updates for waveform generation. The following examples are written in terms of DAC0, but DAC1 operation is identical. ...

  • Page 107

    SFR Definition 8.1. DAC0H: DAC0 High Byte R/W R/W R/W Bit7 Bit6 Bit5 Bits7-0: DAC0 Data Word Most Significant Byte. SFR Definition 8.2. DAC0L: DAC0 Low Byte R/W R/W R/W Bit7 Bit6 Bit5 Bits7-0: DAC0 Data Word Least Significant Byte. ...

  • Page 108

    C8051F040/1/2/3/4/5/6/7 SFR Definition 8.3. DAC0CN: DAC0 Control R DAC0EN - - Bit7 Bit6 Bit5 Bit7: DAC0EN: DAC0 Enable Bit. 0: DAC0 Disabled. DAC0 Output pin is disabled; DAC0 is in low-power shutdown mode. 1: DAC0 Enabled. DAC0 Output ...

  • Page 109

    SFR Definition 8.4. DAC1H: DAC1 High Byte R/W R/W R/W Bit7 Bit6 Bit5 Bits7-0: DAC1 Data Word Most Significant Byte. SFR Definition 8.5. DAC1L: DAC1 Low Byte R/W R/W R/W Bit7 Bit6 Bit5 Bits7-0: DAC1 Data Word Least Significant Byte. ...

  • Page 110

    C8051F040/1/2/3/4/5/6/7 SFR Definition 8.6. DAC1CN: DAC1 Control R/W R/W R/W DAC1EN - - Bit7 Bit6 Bit5 Bit7: DAC1EN: DAC1 Enable Bit. 0: DAC1 Disabled. DAC1 Output pin is disabled; DAC1 is in low-power shutdown mode. 1: DAC1 Enabled. DAC1 Output ...

  • Page 111

    Table 8.1. DAC Electrical Characteristics V = 3.0 V, AV 2.40 V (REFBE = 0), No Output Load unless otherwise specified. DD REF Parameter Static Performance Resolution Integral Nonlinearity Differential Nonlinearity No Output Filter ...

  • Page 112

    C8051F040/1/2/3/4/5/6/7 112 Rev. 1.5 ...

  • Page 113

    Voltage Reference (C8051F040/2/4/6) The voltage reference circuit offers full flexibility in operating the ADC and DAC modules. Three voltage ref- erence input pins allow each ADC and the two DACs (C8051F040/2 only) to reference an external voltage reference or ...

  • Page 114

    C8051F040/1/2/3/4/5/6/7 SFR Definition 9.1. REF0CN: Reference Control R/W R/W R Bit7 Bit6 Bit5 Bits7-5: UNUSED. Read = 000b; Write = don’t care. Bit4: AD0VRS: ADC0 Voltage Reference Select 0: ADC0 voltage reference from VREF0 pin. 1: ADC0 ...

  • Page 115

    Table 9.1. Voltage Reference Electrical Characteristics V = 3.0 V, AV+ = 3.0 V, –40 to +85°C unless otherwise specified. DD Parameter Internal Reference (REFBE = 1) Output Voltage 25 °C ambient VREF Short-Circuit Current VREF Temperature Coefficient Load Regulation ...

  • Page 116

    C8051F040/1/2/3/4/5/6/7 116 Rev. 1.5 ...

  • Page 117

    Voltage Reference (C8051F041/3/5/7) The internal voltage reference circuit consists of a 1.2 V, temperature stable bandgap voltage reference generator and a gain-of-two output buffer amplifier. The internal reference may be routed via the VREF pin to external system components ...

  • Page 118

    C8051F040/1/2/3/4/5/6/7 SFR Definition 10.1. REF0CN: Reference Control R/W R/W R Bit7 Bit6 Bit5 Bits7-5: UNUSED. Read = 000b; Write = don’t care. Bit4: AD0VRS: ADC0 Voltage Reference Select 0: ADC0 voltage reference from VREFA pin. 1: ADC0 ...

  • Page 119

    Table 10.1. Voltage Reference Electrical Characteristics V = 3.0 V, AV+ = 3.0 V, –40 to +85 °C unless otherwise specified. DD Parameter Internal Reference (REFBE = 1) Output Voltage 25 °C ambient VREF Short-Circuit Current VREF Temperature Coefficient Load ...

  • Page 120

    C8051F040/1/2/3/4/5/6/7 120 Rev. 1.5 ...

  • Page 121

    Comparators C8051F04x family of devices include three on-chip programmable voltage comparators, shown in Figure 11.1. Each comparator offers programmable response time and hysteresis. When assigned to a Port pin, the Comparator output may be configured as open drain or ...

  • Page 122

    C8051F040/1/2/3/4/5/6/7 CPn+ VIN+ + CPn CPn- _ VIN- CIRCUIT CONFIGURATION Positive Hysteresis Voltage (Programmed with CPnHYP Bits) VIN- INPUTS VIN OUTPUT V OL Positive Hysteresis Disabled Figure 11.2. Comparator Hysteresis Plot The hysteresis of the Comparator is software-programmable ...

  • Page 123

    Comparator Inputs The Port pins selected as comparator inputs should be configured as analog inputs in the Port 2 Input Con- figuration Register (for details on Port configuration, see tal Inputs” on page 206). The inputs for Comparator are ...

  • Page 124

    C8051F040/1/2/3/4/5/6/7 SFR Definition 11.1. CPTnCN: Comparator 0, 1, and 2 Control R/W R R/W CPnEN CPnOUT CPnRIF Bit7 Bit6 Bit5 SFR Address: CPT0CN: 0x88; CPT1CN: 0x88; CPT2CN: 0x88 SFR Pages: CPT0CN:page 1;CPT1CN:page 2; CPT2CN:page 3 Bit7: CPnEN: Comparator Enable Bit. ...

  • Page 125

    SFR Definition 11.2. CPTnMD: Comparator Mode Selection R/W R/W R CPnRIE Bit7 Bit6 Bit5 SFR Address: CPT0MD: 0x89; CPT1MD: 0x89;CPT2MD: 0x89 SFR Page: CPT0MD:page 1;CPT1MD:page 2; CPT2MD:page 3 Bits7-6: UNUSED. Read = 00b, Write = don’t care. Bit ...

  • Page 126

    C8051F040/1/2/3/4/5/6/7 Table 11.1. Comparator Electrical Characteristics V = 3.0 V, –40 to +85 °C unless otherwise specified. DD Parameter CPn+ – CPn– = 100 mV Response Time, Mode 0 CPn+ – CPn– CPn+ – CPn– = 100 ...

  • Page 127

    CIP-51 Microcontroller The MCU system controller core is the CIP-51 microcontroller. The CIP-51 is fully compatible with the MCS-51™ instruction set; standard 803x/805x assemblers and compilers can be used to develop soft- ware. The MCU family has a superset ...

  • Page 128

    C8051F040/1/2/3/4/5/6/7 Performance The CIP-51 employs a pipelined architecture that greatly increases its instruction throughput over the stan- dard 8051 architecture standard 8051, all instructions except for MUL and DIV take system clock cycles to execute, ...

  • Page 129

    Instruction Set The instruction set of the CIP-51 System Controller is fully compatible with the standard MCS-51™ instruc- tion set; standard 8051 development tools can be used to develop software for the CIP-51. All CIP-51 instructions are the binary ...

  • Page 130

    C8051F040/1/2/3/4/5/6/7 Table 12.1. CIP-51 Instruction Set Summary (Continued) Mnemonic Description DEC Rn Decrement register DEC direct Decrement direct byte DEC @Ri Decrement indirect RAM INC DPTR Increment Data Pointer MUL AB Multiply A and B DIV AB Divide A by ...

  • Page 131

    Table 12.1. CIP-51 Instruction Set Summary (Continued) Mnemonic Description MOV direct, #data Move immediate to direct byte MOV @Ri, A Move A to indirect RAM MOV @Ri, direct Move direct byte to indirect RAM MOV @Ri, #data Move immediate to ...

  • Page 132

    C8051F040/1/2/3/4/5/6/7 Table 12.1. CIP-51 Instruction Set Summary (Continued) Mnemonic Description JNZ rel Jump if A does not equal zero CJNE A, direct, rel Compare direct byte to A and jump if not equal CJNE A, #data, rel Compare immediate to ...

  • Page 133

    ... Flash memory, orga- nized in a contiguous block from addresses 0x0000 to 0xFFFF (C8051F040/1/2/3/4/5) and 0x0000 to 0x7FFF (C8051F046/7). Note: 512 bytes from 0xFE00 to 0xFFFF (C8051F040/1/2/3/4/5 only) of this mem- ory are reserved for factory use and are not available for user program storage. ...

  • Page 134

    C8051F040/1/2/3/4/5/6/7 12.2.2. Data Memory The CIP-51 implements 256 bytes of internal RAM mapped into the data memory space from 0x00 through 0xFF. The lower 128 bytes of data memory are used for general purpose registers and scratch pad mem- ory. ...

  • Page 135

    RET pops two record bits, also.) The stack record circuitry can also detect an overflow or underflow on the 32-bit shift register, and can notify the debug software even with the MCU running at speed. 12.2.6. Special Function ...

  • Page 136

    C8051F040/1/2/3/4/5/6/7 Interrupt Logic Figure 12.3. SFR Page Stack Automatic hardware switching of the SFR Page on interrupts may be enabled or disabled as desired using the SFR Automatic Page Control Enable Bit located in the SFR Page Control Register (SFRPGCN). ...

  • Page 137

    Figure 12.4. SFR Page Stack While Using SFR Page 0x0F To Access Port 5 While CIP-51 executes in-line code (writing values to Port 5 in this example), an ADC2 Window Compara- tor Interrupt occurs. The CIP-51 vectors ...

  • Page 138

    C8051F040/1/2/3/4/5/6/7 SFRPAGE on ADC2 SFRPAGE pushed to SFRNEXT Figure 12.5. SFR Page Stack After ADC2 Window Comparator Interrupt Occurs While in the ADC2 ISR, a PCA interrupt occurs. Recall the PCA interrupt is configured as a high priority interrupt, while ...

  • Page 139

    SFRPAGE pushed to SFRNEXT SFRNEXT pushed to SFRLAST Figure 12.6. SFR Page Stack Upon PCA Interrupt Occurring During an ADC2 ISR On exit from the PCA interrupt service routine, the CIP-51 will return to the ADC2 Window Comparator ISR. On ...

  • Page 140

    C8051F040/1/2/3/4/5/6/7 SFRNEXT popped to SFRPAGE SFRLAST popped to SFRNEXT Figure 12.7. SFR Page Stack Upon Return From PCA Interrupt On the execution of the RETI instruction in the ADC2 Window Comparator ISR, the value in SFRPAGE register is overwritten with ...

  • Page 141

    SFRNEXT popped to SFRPAGE Figure 12.8. SFR Page Stack Upon Return From ADC2 Window Interrupt Note that in the above example, all three bytes in the SFR Page Stack are accessible via the SFRPAGE, SFRNEXT, and SFRLAST special function registers. ...

  • Page 142

    C8051F040/1/2/3/4/5/6/7 SFR Definition 12.1. SFR Page Control Register: SFRPGCN Bit7 Bit6 Bit5 Bits7-1: Reserved. Bit0: SFRPGEN: SFR Automatic Page Control Enable. Upon interrupt the C8051 Core will vector to the specified interrupt service routine ...

  • Page 143

    SFR Definition 12.3. SFR Next Register: SFRNEXT R/W R/W R/W Bit7 Bit6 Bit5 Bits7-0: SFR page context is retained upon interrupts/return from interrupts byte SFR Page Stack: SFRPAGE is the first entry, SFRNEXT is the second, and ...

  • Page 144

    C8051F040/1/2/3/4/5/6/7 Table 12.2. Special Function Register (SFR) Memory Map 0(8) 1(9) 2( SPI0CN PCA0L PCA0H CAN0CN (ALL PAGES) ADC0CN PCA0CPL2 PCA0CPH2 PCA0CPL3 PCA0CPH3 PCA0CPL4 PCA0CPH4 E8 ADC2CN P6 PCA0CPL5 ...

  • Page 145

    Table 12.2. Special Function Register (SFR) Memory Map (Continued 0(8) 1(9) 2( (ALL PAGES) SADDR0 IE A8 (ALL PAGES) EMI0TC EMI0CN P2 A0 (ALL PAGES) SCON0 SBUF0 SPI0CFG SCON1 SBUF1 98 ...

  • Page 146

    C8051F040/1/2/3/4/5/6/7 Table 12.3. Special Function Registers SFRs are listed in alphabetical order. All undefined SFR locations are reserved. Register Address SFR Page ACC 0xE0 All Pages Accumulator ADC0CF 0xBC 0 ADC0CN 0xE8 0 ADC0GTH 0xC5 0 ADC0GTL 0xC4 0 ADC0H ...

  • Page 147

    Table 12.3. Special Function Registers (Continued) SFRs are listed in alphabetical order. All undefined SFR locations are reserved. Register Address SFR Page 3 0xD2 1 DAC1L DPH 0x83 All Pages Data Pointer High DPL 0x82 All Pages Data Pointer Low ...

  • Page 148

    C8051F040/1/2/3/4/5/6/7 Table 12.3. Special Function Registers (Continued) SFRs are listed in alphabetical order. All undefined SFR locations are reserved. Register Address SFR Page PCA0CPH4 0xEE 0 PCA0CPH5 0xE2 0 PCA0CPL0 0xFB 0 PCA0CPL1 0xFD 0 PCA0CPL2 0xE9 0 PCA0CPL3 0xEB ...

  • Page 149

    Table 12.3. Special Function Registers (Continued) SFRs are listed in alphabetical order. All undefined SFR locations are reserved. Register Address SFR Page SPI0CFG 0x9A 0 SPI0CKR 0x9D 0 SPI0CN 0xF8 0 SPI0DAT 0x9B 0 SSTA0 0x91 0 TCON 0x88 0 ...

  • Page 150

    C8051F040/1/2/3/4/5/6/7 12.2.7. Register Descriptions Following are descriptions of SFRs related to the operation of the CIP-51 System Controller. Reserved bits should not be set to logic 1. Future product versions may use these bits to implement new features, in which ...

  • Page 151

    SFR Definition 12.8. PSW: Program Status Word R/W R/W R Bit7 Bit6 Bit5 Bit7: CY: Carry Flag. This bit is set when the last arithmetic operation resulted in a carry (addition borrow (subtraction ...

  • Page 152

    C8051F040/1/2/3/4/5/6/7 SFR Definition 12.9. ACC: Accumulator R/W R/W R/W ACC.7 ACC.6 ACC.5 Bit7 Bit6 Bit5 Bits7-0: ACC: Accumulator. This register is the accumulator for arithmetic operations. SFR Definition 12.10 Register R/W R/W R/W B.7 B.6 B.5 Bit7 Bit6 ...

  • Page 153

    Interrupt Handler The CIP-51 includes an extended interrupt system supporting a total of 20 interrupt sources with two prior- ity levels. The allocation of interrupt sources between on-chip peripherals and external inputs pins varies according to the specific version ...

  • Page 154

    C8051F040/1/2/3/4/5/6/7 12.3.2. External Interrupts The external interrupt sources (/INT0 and /INT1) are configurable as active-low level-sensitive or active- low edge-sensitive inputs depending on the setting of bits IT0 (TCON.0) and IT1 (TCON.2). IE0 (TCON.1) and IE1 (TCON.3) serve as the ...

  • Page 155

    Table 12.4. Interrupt Summary (Continued) Interrupt Priority Interrupt Source Vector Order Comparator 1 0x005B 11 Comparator 2 0x0063 12 Timer 3 0x0073 14 ADC0 End of 0x007B 15 Conversion Timer 4 0x0083 16 ADC2 Window 0x0093 17 Comparator ADC2 End ...

  • Page 156

    C8051F040/1/2/3/4/5/6/7 12.3.3. Interrupt Priorities Each interrupt source can be individually programmed to one of two priority levels: low or high. A low prior- ity interrupt service routine can be preempted by a high priority interrupt. A high priority interrupt cannot ...

  • Page 157

    SFR Definition 12.11. IE: Interrupt Enable R/W R/W R/W EA IEGF0 ET2 Bit7 Bit6 Bit5 Bit7: EA: Enable All Interrupts. This bit globally enables/disables all interrupts. It overrides the individual interrupt mask set- tings. 0: Disable all interrupt sources. 1: ...

  • Page 158

    C8051F040/1/2/3/4/5/6/7 SFR Definition 12.12. IP: Interrupt Priority R/W R/W R PT2 Bit7 Bit6 Bit5 Bits7-6: UNUSED. Read = 11b, Write = don't care. Bit5: PT2: Timer 2 Interrupt Priority Control. This bit sets the priority of the Timer ...

  • Page 159

    SFR Definition 12.13. EIE1: Extended Interrupt Enable 1 R/W R/W R/W CP2IE CP1IE Bit7 Bit6 Bit5 Bit7: Reserved. Read = 0b, Write = don’t care. Bit6: CP2IE: Enable Comparator (CP2) Interrupt. This bit sets the masking of the CP2 interrupt. ...

  • Page 160

    C8051F040/1/2/3/4/5/6/7 SFR Definition 12.14. EIE2: Extended Interrupt Enable 2 R/W R/W R/W - ES1 ECAN0 Bit7 Bit6 Bit5 Bit7: Reserved Bit6: ES1: Enable UART1 Interrupt. This bit sets the masking of the UART1 interrupt. 0: Disable UART1 interrupt. 1: Enable ...

  • Page 161

    SFR Definition 12.15. EIP1: Extended Interrupt Priority 1 R/W R/W R/W - PCP2 PCP1 Bit7 Bit6 Bit5 Bit7: Reserved. Bit6: PCP2: Comparator2 (CP2) Interrupt Priority Control. This bit sets the priority of the CP2 interrupt. 0: CP2 interrupt set to ...

  • Page 162

    C8051F040/1/2/3/4/5/6/7 SFR Definition 12.16. EIP2: Extended Interrupt Priority 2 R/W R/W R/W - EP1 PX7 Bit7 Bit6 Bit5 Bit7: Reserved. Bit6: EP1: UART1 Interrupt Priority Control. This bit sets the priority of the UART1 interrupt. 0: UART1 interrupt set to ...

  • Page 163

    Power Management Modes The CIP-51 core has two software programmable power management modes: Idle and Stop. Idle mode halts the CPU while leaving the external peripherals and internal clocks active. In Stop mode, the CPU is halted, all interrupts ...

  • Page 164

    C8051F040/1/2/3/4/5/6/7 12.17.2.Stop Mode Setting the Stop Mode Select bit (PCON.1) causes the CIP-51 to enter Stop mode as soon as the instruc- tion that sets the bit completes. In Stop mode, the CPU and internal oscillators are stopped, effectively shutting ...

  • Page 165

    Reset Sources Reset circuitry allows the controller to be easily placed in a predefined default condition. On entry to this reset state, the following occur: • CIP-51 halts program execution • Special Function Registers (SFRs) are initialized to their ...

  • Page 166

    C8051F040/1/2/3/4/5/6/7 13.1. Power-On Reset The C8051F04x family incorporates a power supply monitor that holds the MCU in the reset state until V rises above the V level during power-up. See Figure 13.2 for timing diagram, and refer to Table 13.1 ...

  • Page 167

    The MCU will remain in reset until at least 12 clock cycles after the active-low /RST signal is removed. The PINRSF flag (RST- SRC.0) is set on exit ...

  • Page 168

    C8051F040/1/2/3/4/5/6/7 13.7.1. Enable/Reset WDT The watchdog timer is both enabled and reset by writing 0xA5 to the WDTCN register. The user's applica- tion software should include periodic writes of 0xA5 to WDTCN as needed to prevent a watchdog timer overflow. ...

  • Page 169

    SFR Definition 13.1. WDTCN: Watchdog Timer Control R/W R/W R/W Bit7 Bit6 Bit5 Bits7-0: WDT Control Writing 0xA5 both enables and reloads the WDT. Writing 0xDE followed within 4 system clocks by 0xAD disables the WDT. Writing 0xFF locks out ...

  • Page 170

    C8051F040/1/2/3/4/5/6/7 SFR Definition 13.2. RSTSRC: Reset Source R R/W R/W - CNVRSEF C0RSEF SWRSEF WDTRSF MCDRSF Bit7 Bit6 Bit5 Bit7: Reserved. Bit6: CNVRSEF: Convert Start Reset Source Enable and Flag Write: 0: CNVSTR0 is not a reset source. 1: CNVSTR0 ...

  • Page 171

    Table 13.1. Reset Electrical Characteristics –40 to +85 °C unless otherwise specified. Parameter RST Output Low Voltage I OL RST Input High Voltage RST Input Low Voltage RST Input Leakage Current RST = 0 for /RST Output Valid ...

  • Page 172

    C8051F040/1/2/3/4/5/6/7 172 Rev. 1.5 ...

  • Page 173

    Oscillators Option 3 XTAL1 XTAL2 Option 4 XTAL1 Option 2 Option 1 VDD XTAL1 Figure 14.1. Oscillator Diagram 14.1. Programmable Internal Oscillator All C8051F04x devices include a programmable internal oscillator that defaults as the system clock after a system ...

  • Page 174

    C8051F040/1/2/3/4/5/6/7 SFR Definition 14.1. OSCICL: Internal Oscillator Calibration R/W R/W R/W Bit7 Bit6 Bit5 Bits 7-0: OSCICL: Internal Oscillator Calibration Register This register calibrates the internal oscillator period. The reset value for OSCICL defines the internal oscillator base frequency. The ...

  • Page 175

    Table 14.1. Internal Oscillator Electrical Characteristics –40 to +85 °C unless otherwise specified. Parameter Calibrated Internal Oscillator  Frequency Internal Oscillator Supply Current OSCICN (from External Clock Frequency T (External Clock High Time) XCH T ...

  • Page 176

    C8051F040/1/2/3/4/5/6/7 SFR Definition 14.4. OSCXCN: External Oscillator Control R R/W R/W XTLVLD XOSCMD2 XOSCMD1 XOSCMD0 Bit7 Bit6 Bit5 Bit7: XTLVLD: Crystal Oscillator Valid Flag. (Read only when XOSCMD = 11x.) 0: Crystal Oscillator is unused or not yet stable. 1: ...

  • Page 177

    External Crystal Example If a crystal or ceramic resonator is used as an external oscillator source for the MCU, the circuit should be configured as shown in Figure 14.1, Option 1. The External Oscillator Frequency Control value (XFCN) should ...

  • Page 178

    C8051F040/1/2/3/4/5/6/7 14.5. External RC Example network is used as an external oscillator source for the MCU, the circuit should be configured as shown in Figure 14.1, Option 2. The capacitor should be no greater than 100 pF; ...

  • Page 179

    ... Flash Memory The C8051F04x family includes 128 (C8051F040/1/2/3/4/ 128 (C8051F046/7) of on- chip, reprogrammable Flash memory for program code and non-volatile data storage. The Flash memory can be programmed in-system, a single byte at a time, through the JTAG interface or by software using the MOVX write instructions. Once cleared to logic 0, a Flash bit must be erased to set it back to logic 1. The bytes would typically be erased (set to 0xFF) before being reprogrammed. Flash write and erase opera- tions are automatically timed by hardware for proper execution ...

  • Page 180

    ... C8051F040/1/2/3/4/5/6/7 3/4/5) and all locations above 0x8000 (C8051F046/7) are reserved. Flash writes and erases targeting the reserved area should be avoided. Table 15.1. Flash Electrical Characteristics V = 2 –40 to +85 ° Parameter 1 Flash Size C8051F040/1/2/3/4/5 C8051F046/7 Endurance Erase Cycle Time Write Cycle Time Notes: 1 ...

  • Page 181

    ... Scratchpad Memory Reserved 0xFE00 Read Lock Byte 0xFDFF Write/Erase Lock Byte 0xFDFE 0xFDFD Program/Data Memory Space Software Read Limit 0x0000 C8051F046/7 Reserved 0x8000 Read Lock Byte 0x7FFF Write/Erase Lock Byte 0x7FFE 0x7FFD Program/Data Memory Space Software Read Limit 0x0000 Rev. 1.5 ...

  • Page 182

    ... This erasure can only be performed via JTAG non-security byte in the 0xFBFF-0xFDFF (C8051F040/1/2/3/4/5) or 0x7DFF-0x7FFF (C8051F046/7) page is addressed during the JTAG era- sure, only that page (including the security bytes) will be erased. ...

  • Page 183

    Summary of Flash Security Options There are three Flash access methods supported on the C8051F04x devices; 1) Accessing Flash through the JTAG debug interface, 2) Accessing Flash from firmware residing below the Flash Access Limit, and 3) Accessing Flash ...

  • Page 184

    C8051F040/1/2/3/4/5/6/7 SFR Definition 15.1. FLACL: Flash Access Limit R/W R/W R/W Bit7 Bit6 Bit5 Bits 7-0: FLACL: Flash Access Limit. This register holds the high byte of the 16-bit program memory read/write/erase limit address. The entire 16-bit access limit address ...

  • Page 185

    SFR Definition 15.3. PSCTL: Program Store Read/Write Control R/W R/W R Bit7 Bit6 Bit5 Bits7-3: UNUSED. Read = 00000b, Write = don't care. Bit2: SFLE: Scratchpad Flash Memory Access Enable When this bit is set, Flash reads ...

  • Page 186

    C8051F040/1/2/3/4/5/6/7 186 Rev. 1.5 ...

  • Page 187

    External Data Memory Interface and On-Chip XRAM The C8051F04x MCUs include on-chip RAM mapped into the external data memory space (XRAM), as well as an External Data Memory Interface which can be used to access off-chip ...

  • Page 188

    C8051F040/1/2/3/4/5/6/7 16.2. Configuring the External Memory Interface Configuring the External Memory Interface consists of five steps: 1. Select EMIF on Low Ports (P3, P2, P1, and P0) or High Ports (P7, P6, P5, and P4). 2. Configure the Output Modes ...

  • Page 189

    SFR Definition 16.1. EMI0CN: External Memory Interface Control R/W R/W R/W PGSEL7 PGSEL6 PGSEL5 Bit7 Bit6 Bit5 Bits7-0: PGSEL[7:0]: XRAM Page Select Bits. The XRAM Page Select Bits provide the high byte of the 16-bit external data memory address when ...

  • Page 190

    C8051F040/1/2/3/4/5/6/7 SFR Definition 16.2. EMI0CF: External Memory Configuration R/W R/W R PRTSEL Bit7 Bit6 Bit5 Bits7-6: Unused. Read = 00b. Write = don’t care. Bit5: PRTSEL: EMIF Port Select. 0: EMIF active on P0-P3. 1: EMIF active on ...

  • Page 191

    Multiplexed and Non-multiplexed Selection The External Memory Interface is capable of acting in a Multiplexed mode or a Non-multiplexed mode, depending on the state of the EMD2 (EMI0CF.4) bit. 16.4.1. Multiplexed Configuration In Multiplexed mode, the Data Bus and ...

  • Page 192

    C8051F040/1/2/3/4/5/6/7 16.4.2. Non-multiplexed Configuration In Non-multiplexed mode, the Data Bus and the Address Bus pins are not shared. An example of a Non- multiplexed Configuration is shown in Figure 16.2. See page 196 for more information about Non-multiplexed operation. A[15:0] ...

  • Page 193

    Memory Mode Selection The external data memory space can be configured in one of four modes, shown in Figure 16.3, based on the EMIF Mode bits in the EMI0CF register (SFR Definition 16.2). These modes are summarized below. More ...

  • Page 194

    C8051F040/1/2/3/4/5/6/7 16.5.3. Split Mode with Bank Select When EMI0CF.[3:2] are set to ‘10’, the XRAM memory map is split into two areas, on-chip space and off- chip space. • Effective addresses below the 4k boundary will access on-chip XRAM space. ...

  • Page 195

    SFR Definition 16.3. EMI0TC: External Memory Timing Control R/W R/W R/W EAS1 EAS0 ERW3 Bit7 Bit6 Bit5 Bits7-6: EAS1-0: EMIF Address Setup Time Bits. 00: Address setup time = 0 SYSCLK cycles. 01: Address setup time = 1 SYSCLK cycle. ...

  • Page 196

    C8051F040/1/2/3/4/5/6/7 16.6.1. Non-multiplexed Mode 16.6.1.1.16-bit MOVX: EMI0CF[4:2] = ‘101’, ‘110’, or ‘111’. ADDR[15:8] P1/P5 ADDR[7:0] P2/P6 DATA[7:0] P3/P7 /WR P0.7/P4.7 /RD P0.6/P4.6 ADDR[15:8] P1/P5 ADDR[7:0] P2/P6 DATA[7:0] P3/P7 /RD P0.6/P4.6 /WR P0.7/P4.7 Figure 16.4. Non-multiplexed 16-bit MOVX Timing 196 Nonmuxed ...

  • Page 197

    MOVX without Bank Select: EMI0CF[4:2] = ‘101’ or ‘111’. ADDR[15:8] ADDR[7:0] P2/P6 DATA[7:0] P3/P7 /WR P0.7/P4.7 /RD P0.6/P4.6 ADDR[15:8] ADDR[7:0] P2/P6 DATA[7:0] P3/P7 /RD P0.6/P4.6 /WR P0.7/P4.7 Figure 16.5. Non-multiplexed 8-bit MOVX without Bank Select Timing C8051F040/1/2/3/4/5/6/7 Nonmuxed 8-bit ...

  • Page 198

    C8051F040/1/2/3/4/5/6/7 16.6.1.3.8-bit MOVX with Bank Select: EMI0CF[4:2] = ‘110’. ADDR[15:8] P1/P5 ADDR[7:0] P2/P6 DATA[7:0] P3/P7 /WR P0.7/P4.7 /RD P0.6/P4.6 ADDR[15:8] P1/P5 ADDR[7:0] P2/P6 DATA[7:0] P3/P7 /RD P0.6/P4.6 /WR P0.7/P4.7 Figure 16.6. Non-multiplexed 8-bit MOVX with Bank Select Timing 198 Nonmuxed ...

  • Page 199

    Multiplexed Mode 16.6.2.1.16-bit MOVX: EMI0CF[4:2] = ‘001’, ‘010’, or ‘011’. ADDR[15:8] P2/P6 EMIF ADDRESS (8 LSBs) from AD[7:0] P3/P7 T ALEH ALE P0.5/P4.5 /WR P0.7/P4.7 /RD P0.6/P4.6 ADDR[15:8] P2/P6 EMIF ADDRESS (8 LSBs) from AD[7:0] P3/P7 T ALEH ALE ...

  • Page 200

    C8051F040/1/2/3/4/5/6/7 16.6.2.2.8-bit MOVX without Bank Select: EMI0CF[4:2] = ‘001’ or ‘011’. ADDR[15:8] EMIF ADDRESS (8 LSBs) from AD[7:0] P3/ ALEH ALE P0.5/P4.5 /WR P0.7/P4.7 /RD P0.6/P4.6 ADDR[15:8] EMIF ADDRESS (8 LSBs) from AD[7:0] P3/ ...