C8051F046-GQ Silicon Laboratories Inc, C8051F046-GQ Datasheet - Page 179

• Manufacturer Part Number: C8051F046-GQ
• Description: IC 8051 MCU 32K FLASH 100TQFP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F04xr

Specifications of C8051F046-GQ

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: CAN, EBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 64
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 4.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 13x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Processor Series: C8051F0x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 4.25 KB
• Interface Type: CAN, SMBus, SPI, UART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 64
• Number Of Timers: 5
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F040DK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 13 Channel
• On-chip Dac: 12 bit, 2 Channel
• Package: 100TQFP
• Device Core: 8051
• Family Name: C8051F04x
• Maximum Speed: 25 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 336-1211

15. Flash Memory
The C8051F04x family includes 64 kB + 128 (C8051F040/1/2/3/4/5) or 32 kB + 128 (C8051F046/7) of on-
chip, reprogrammable Flash memory for program code and non-volatile data storage. The Flash memory
can be programmed in-system, a single byte at a time, through the JTAG interface or by software using the
MOVX write instructions. Once cleared to logic 0, a Flash bit must be erased to set it back to logic 1. The
bytes would typically be erased (set to 0xFF) before being reprogrammed. Flash write and erase opera-
tions are automatically timed by hardware for proper execution; data polling to determine the end of the
write/erase operation is not required. The CPU is stalled during write/erase operations while the device
peripherals remain active. Interrupts that occur during Flash write/erase operations are held, and are then
serviced in their priority order once the Flash operation has completed. Refer to Table 15.1 for the electri-
cal characteristics of the Flash memory.
15.1. Programming The Flash Memory
The simplest means of programming the Flash memory is through the JTAG interface using programming
tools provided by Silicon Labs or a third party vendor. This is the only means for programming a non-initial-
ized device. For details on the JTAG commands to program Flash memory, see
gramming Commands” on page
The Flash memory can be programmed by software using the MOVX write instruction with the address and
data byte to be programmed provided as normal operands. Before writing to Flash memory using MOVX,
Flash write operations must be enabled by setting the PSWE Program Store Write Enable bit (PSCTL.0) to
logic 1. This directs the MOVX writes to Flash memory instead of to XRAM, which is the default target. The
PSWE bit remains set until cleared by software. To avoid errant Flash writes, it is recommended that inter-
rupts be disabled while the PSWE bit is logic 1.
Flash memory is read using the MOVC instruction. MOVX reads are always directed to XRAM, regardless
of the state of PSWE.
Note: To ensure the integrity of Flash memory contents, it is strongly recommended that the on-chip V
monitor be enabled by connecting the V
cutes code that writes and/or erases Flash memory from software. See “Reset Sources” on page 165 for
more information.
A write to Flash memory can clear bits but cannot set them; only an erase operation can set bits in Flash.
A byte location to be programmed must be erased before a new value can be written. The Flash
memory is organized in 512-byte pages. The erase operation applies to an entire page (setting all bytes in
the page to 0xFF). The following steps illustrate the algorithm for programming Flash by user software.
Write/Erase timing is automatically controlled by hardware. Note that code execution in the 8051 is stalled
while the Flash is being programmed or erased. Note that 512 bytes at locations 0xFE00 (C8051F040/1/2/
Step 1. Disable interrupts.
Step 2. Set FLWE (FLSCL.0) to enable Flash writes/erases via user software.
Step 3. Set PSEE (PSCTL.1) to enable Flash erases.
Step 4. Set PSWE (PSCTL.0) to redirect MOVX commands to write to Flash.
Step 5. Use the MOVX command to write a data byte to any location within the 512-byte page to
Step 6. Clear PSEE to disable Flash erases
Step 7. Use the MOVX command to write a data byte to the desired byte location within the
Step 8. Clear the PSWE bit to redirect MOVX commands to the XRAM data space.
Step 9. Re-enable interrupts.
be erased.
erased 512-byte page. Repeat this step until all desired bytes are written (within the target
page).
321.
DD
monitor enable pin (MONEN) to V
Rev. 1.5
C8051F040/1/2/3/4/5/6/7
DD
Section “25.2. Flash Pro-
in any system that exe-
179
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