C8051F046-GQ Silicon Laboratories Inc, C8051F046-GQ Datasheet - Page 204

• Manufacturer Part Number: C8051F046-GQ
• Description: IC 8051 MCU 32K FLASH 100TQFP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F04xr

Specifications of C8051F046-GQ

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: CAN, EBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 64
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 4.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 13x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Processor Series: C8051F0x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 4.25 KB
• Interface Type: CAN, SMBus, SPI, UART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 64
• Number Of Timers: 5
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F040DK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 13 Channel
• On-chip Dac: 12 bit, 2 Channel
• Package: 100TQFP
• Device Core: 8051
• Family Name: C8051F04x
• Maximum Speed: 25 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 336-1211

C8051F040/1/2/3/4/5/6/7
The C8051F04x family of devices have a wide array of digital resources which are available through the
four lower I/O Ports: P0, P1, P2, and P3. Each of the pins on P0, P1, P2, and P3, can be defined as a Gen-
eral-Purpose I/O (GPIO) pin or can be controlled by a digital peripheral or function (like UART0 or /INT1 for
example), as shown in Figure 17.2. The system designer controls which digital functions are assigned
pins, limited only by the number of pins available. This resource assignment flexibility is achieved through
the use of a Priority Crossbar Decoder. The state of a Port I/O pin can always be read from its associated
Data register regardless of whether that pin has been assigned to a digital peripheral or behaves as GPIO.
The Port pins on Ports 1, 2, and 3 can be used as Analog Inputs to ADC2 (C8051F040/1/2/3 only), Analog
Voltage Comparators, and ADC0, respectively.
An External Memory Interface, which is active during the execution of an off-chip MOVX instruction, can be
active on either the lower Ports or the upper Ports. See
and On-Chip XRAM” on page 187
17.1. Ports 0 through 3 and the Priority Crossbar Decoder
The Priority Crossbar Decoder, or “Crossbar”, allocates and assigns Port pins on Port 0 through Port 3 to
the digital peripherals (UARTs, SMBus, PCA, Timers, etc.) on the device using a priority order. The Port
pins are allocated in order starting with P0.0 and continue through P3.7, if necessary. The digital peripher-
als are assigned Port pins in a priority order which is listed in Figure 17.3, with UART0 having the highest
priority and CNVSTR2 having the lowest priority.
204
Highest
Priority
Lowest
Priority
Latches
Port
/SYSCLK
CNVSTR0
CNVSTR2
T2, T2EX,
T3, T3EX,
T4,T4EX,
Comptr.
Outputs
UART0
UART1
SMBus
T0, T1,
/INT0,
/INT1
PCA
P0
P1
P2
P3
SPI
Figure 17.2. Port I/O Functional Block Diagram
(P0.0-P0.7)
(P1.0-P1.7)
(P2.0-P2.7)
(P3.0-P3.7)
8
8
8
8
2
4
2
2
6
2
8
for more information about the External Memory Interface.
XBR0, XBR1, XBR2,
P2MDIN, P3MDIN
XBR3 P1MDIN,
Crossbar
Decoder
To External
Registers
Priority
Rev. 1.5
Digital
Interface
Memory
(EMIF)
Section “16. External Data Memory Interface
8
8
8
8
P0MDOUT, P1MDOUT,
P2MDOUT, P3MDOUT
Comparators
Registers
ADC2
ADC0
Input
Input
Cells
Cells
Cells
Cells
To
To
To
P0
I/O
P1
I/O
P2
I/O
P3
I/O
External
Pins
P0.0
P0.7
P1.0
P1.7
P2.0
P2.7
P3.0
P3.7
Highest
Priority
Lowest
Priority