C8051F046-GQ Silicon Laboratories Inc, C8051F046-GQ Datasheet - Page 206

• Manufacturer Part Number: C8051F046-GQ
• Description: IC 8051 MCU 32K FLASH 100TQFP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F04xr

Specifications of C8051F046-GQ

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: CAN, EBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 64
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 4.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 13x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Processor Series: C8051F0x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 4.25 KB
• Interface Type: CAN, SMBus, SPI, UART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 64
• Number Of Timers: 5
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F040DK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 13 Channel
• On-chip Dac: 12 bit, 2 Channel
• Package: 100TQFP
• Device Core: 8051
• Family Name: C8051F04x
• Maximum Speed: 25 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 336-1211

C8051F040/1/2/3/4/5/6/7
SFR Definition 17.7, SFR Definition 17.10, and SFR Definition 17.13), a set of SFRs which are both byte-
and bit-addressable. The output states of Port pins that are allocated by the Crossbar are controlled by the
digital peripheral that is mapped to those pins. Writes to the Port Data registers (or associated Port bits)
will have no effect on the states of these pins.
A Read of a Port Data register (or Port bit) will always return the logic state present at the pin itself, regard-
less of whether the Crossbar has allocated the pin for peripheral use or not. An exception to this occurs
during the execution of a read-modify-write instruction (ANL, ORL, XRL, CPL, INC, DEC, DJNZ, JBC,
CLR, SET, and the bitwise MOV operation). During the read cycle of the read-modify-write instruction, it is
the contents of the Port Data register, not the state of the Port pins themselves, which is read.
Because the Crossbar registers affect the pinout of the peripherals of the device, they are typically config-
ured in the initialization code of the system before the peripherals themselves are configured. Once config-
ured, the Crossbar registers are typically left alone.
Once the Crossbar registers have been properly configured, the Crossbar is enabled by setting XBARE
(XBR2.4) to a logic 1. Until XBARE is set to a logic 1, the output drivers on Ports 0 through 3 are
explicitly disabled in order to prevent possible contention on the Port pins while the Crossbar reg-
isters and other registers which can affect the device pinout are being written.
The output drivers on Crossbar-assigned input signals (like RX0, for example) are explicitly disabled; thus
the values of the Port Data registers and the PnMDOUT registers have no effect on the states of these
pins.
17.1.2. Configuring the Output Modes of the Port Pins
The output drivers on Ports 0 through 3 remain disabled until the Crossbar is enabled by setting XBARE
(XBR2.4) to a logic 1.
The output mode of each port pin can be configured to be either Open-Drain or Push-Pull. In the Push-Pull
configuration, writing a logic 0 to the associated bit in the Port Data register will cause the Port pin to be
driven to GND, and writing a logic 1 will cause the Port pin to be driven to V
. In the Open-Drain configu-
DD
ration, writing a logic 0 to the associated bit in the Port Data register will cause the Port pin to be driven to
GND, and a logic 1 will cause the Port pin to assume a high-impedance state. The Open-Drain configura-
tion is useful to prevent contention between devices in systems where the Port pin participates in a shared
interconnection in which multiple outputs are connected to the same physical wire (like the SDA signal on
an SMBus connection).
The output modes of the Port pins on Ports 0 through 3 are determined by the bits in the associated
PnMDOUT registers (See SFR Definition 17.6, SFR Definition 17.9, SFR Definition 17.12, and SFR Defini-
tion 17.15). For example, a logic 1 in P3MDOUT.7 will configure the output mode of P3.7 to Push-Pull; a
logic 0 in P3MDOUT.7 will configure the output mode of P3.7 to Open-Drain. All Port pins default to Open-
Drain output.
The PnMDOUT registers control the output modes of the port pins regardless of whether the Crossbar has
allocated the Port pin for a digital peripheral or not. The exceptions to this rule are: the Port pins connected
to SDA, SCL, RX0 (if UART0 is in Mode 0), and RX1 (if UART1 is in Mode 0) are always configured as
Open-Drain outputs, regardless of the settings of the associated bits in the PnMDOUT registers.
17.1.3. Configuring Port Pins as Digital Inputs
A Port pin is configured as a digital input by setting its output mode to “Open-Drain” in the PnMDOUT reg-
ister and writing a logic 1 to the associated bit in the Port Data register. For example, P3.7 is configured as
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