MC908SR12MFAE Freescale Semiconductor, MC908SR12MFAE Datasheet
MC908SR12MFAE
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MC908SR12MFAE Summary of contents
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MC68HC908SR12 MC68HC08SR12 Data Sheet M68HC08 Microcontrollers MC68HC908SR12 Rev. 5.0 07/2004 freescale.com ...
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... The following revision history table summarizes changes contained in this document. For your convenience, the page number designators have been linked to the appropriate location. Freescale and the Freescale logo are trademarks of Freescale Semiconductor, Inc. This product incorporates SuperFlash® technology licensed from SST. MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 Freescale Semiconductor http://www ...
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... ROM part: MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 Page Number(s) for ADC 373, 381 DD 248 323, 254, 293 120 167 169 — timer 181 327, 329 338, 339 and Table 24-5 . 374, 376 DD — 382 393 Freescale Semiconductor ...
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... Section 15. Analog-to-Digital Converter (ADC 231 Section 16. Serial Communications Interface (SCI 251 Section 17. Multi-Master IIC Interface (MMIIC 291 Section 18. Input/Output (I/O) Ports . . . . . . . . . . . . . . . 317 Section 19. External Interrupt (IRQ 335 MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 Freescale Semiconductor (CONFIG & MOR List of Sections List of Sections Data Sheet 5 ...
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... Section 21. Computer Operating Properly (COP 351 Section 22. Low-Voltage Inhibit (LVI 357 Section 23. Break Module (BRK 363 Section 24. Electrical Specifications 371 Section 25. Mechanical Specifications . . . . . . . . . . . . . 387 Section 26. Ordering Information . . . . . . . . . . . . . . . . . 391 Appendix A. MC68HC08SR12 . . . . . . . . . . . . . . . . . . . . 393 Data Sheet 6 MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 List of Sections Freescale Semiconductor ...
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... MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 Freescale Semiconductor Section 1. General Description Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 Power Supply Pins (V DD Oscillator Pins (OSC1 and OSC2 External Reset Pin (RST External Interrupt Pin (IRQ1) ...
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... FLASH Page Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . . 66 FLASH Mass Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . . 67 FLASH Program Operation .68 FLASH Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70 FLASH Block Protect Register . . . . . . . . . . . . . . . . . . . . . . . 70 (CONFIG & MOR) Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74 Configuration Register 1 (CONFIG1 Configuration Register 2 (CONFIG2 Mask Option Register (MOR MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 Table of Contents Freescale Semiconductor ...
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... MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 Freescale Semiconductor Section 6. Central Processor Unit (CPU) Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Condition Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Arithmetic/Logic Unit (ALU Low-Power Modes ...
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... Oscillator Output Frequency Signal (CGMXCLK 126 CGM Reference Clock (CGMRCLK 126 CGM VCO Clock Output (CGMVCLK 127 CGM Base Clock Output (CGMOUT 127 CGM CPU Interrupt (CGMINT 127 CGM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 PLL Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 Table of Contents ) . . . . . . . . . . . . . . . . . . . . . . 126 ) . . . . . . . . . . . . . . . . . . . . . 126 Freescale Semiconductor ...
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... MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 Freescale Semiconductor PLL Bandwidth Control Register . . . . . . . . . . . . . . . . . . . .130 PLL Multiplier Select Registers . . . . . . . . . . . . . . . . . . . . . 132 PLL VCO Range Select Register . . . . . . . . . . . . . . . . . . . .133 PLL Reference Divider Select Register . . . . . . . . . . . . . . . 134 Interrupts .135 Special Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135 Stop Mode ...
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... SIM Break Flag Control Register . . . . . . . . . . . . . . . . . . . . 164 Section 10. Monitor ROM (MON) Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .165 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .166 Entering Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 Break Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 Baud Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .173 Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 Security 178 MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 Table of Contents Freescale Semiconductor ...
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... TIM Counter Modulo Registers . . . . . . . . . . . . . . . . . . . . . 199 11.10.4 TIM Channel Status and Control Registers . . . . . . . . . . . . 200 11.10.5 TIM Channel Registers 203 12.1 12.2 MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 Freescale Semiconductor Section 11. Timer Interface Module (TIM) Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .181 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 Pin Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 Functional Description ...
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... PWM Period and Resolution 214 PWM Automatic Phase Control . . . . . . . . . . . . . . . . . . . . . . .215 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 Wait Mode 216 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 Section 14. Analog Module Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .221 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .223 MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 Table of Contents Freescale Semiconductor ...
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... MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 Freescale Semiconductor On-Chip Temperature Sensor . . . . . . . . . . . . . . . . . . . . . . 223 Two-Stage Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 Amplifier Response Time . . . . . . . . . . . . . . . . . . . . . . . . . . 224 Current Flow Detection Amplifier . . . . . . . . . . . . . . . . . . . . 225 Current Flow Detect Output . . . . . . . . . . . . . . . . . . . . . . . . 225 Interrupts .225 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .225 Stop Mode ...
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... Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262 Character Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262 Character Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . 262 Data Sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264 Framing Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266 Baud Rate Tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . .266 Receiver Wakeup 269 Receiver Interrupts 270 Error Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270 MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 Table of Contents ) . . . . . . . . . . . . . . . . . . . . . 240 ). . . . . . . . . . . . . . . . . . . . . 240 ). . . . . . . . . . . . . 241 REFH ) . . . . . . . . . . . . . 241 REFL Freescale Semiconductor ...
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... MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 Freescale Semiconductor Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .271 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .271 SCI During Break Module Interrupts .272 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272 TxD (Transmit Data 272 RxD (Receive Data 273 I/O Registers 273 SCI Control Register 1 ...
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... Port A LED Control Register (LEDA 323 Port 323 Port B Data Register (PTB 324 Data Direction Register B (DDRB 325 Port 327 Port C Data Register (PTC 327 Data Direction Register C (DDRC 329 Port C LED Control Register (LEDC 330 MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 Table of Contents Freescale Semiconductor ...
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... Keyboard Module During Break Interrupts . . . . . . . . . . . . . . . 350 MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 Freescale Semiconductor Port 331 Port D Data Register (PTD 331 Data Direction Register D (DDRD 332 Section 19. External Interrupt (IRQ) Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .335 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335 Functional Description ...
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... Section 22. Low-Voltage Inhibit (LVI) Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .357 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .358 Polled LVI Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 359 Forced Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . . . .360 Voltage Hysteresis Protection . . . . . . . . . . . . . . . . . . . . . . 360 LVI Trip Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 360 LVI Status Register 361 MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 Table of Contents Freescale Semiconductor ...
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... MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 Freescale Semiconductor LVI Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .361 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .362 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .362 Section 23. Break Module (BRK) Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .363 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 364 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .364 Flag Protection During Break Interrupts ...
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... Section 25. Mechanical Specifications Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .387 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 387 48-Pin Plastic Low Quad Flat Pack (LQFP 388 42-Pin Shrink Dual In-Line Package (SDIP 389 Section 26. Ordering Information Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .391 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 391 MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 391 MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 Table of Contents Freescale Semiconductor ...
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... A.5 A.6 A.7 A.8 A.8.1 A.8.2 A.8.3 A.9 MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 Freescale Semiconductor Appendix A. MC68HC08SR12 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .393 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 394 MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 394 Memory Map 394 Mask Option Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397 Reserved Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397 Monitor ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .397 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397 5 ...
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... Table of Contents Data Sheet 24 MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 Table of Contents Freescale Semiconductor ...
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... MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 Freescale Semiconductor Title MC68HC908SR12 Block Diagram . . . . . . . . . . . . . . . . . . . . . . 39 48-Pin LQFP Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . 40 42-Pin SDIP Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Power Supply Bypassing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Memory Map Control, Status, and Data Registers . . . . . . . . . . . . . . . . . . . . .48 FLASH I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . 64 FLASH Control Register (FLCR) ...
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... SIM I/O Register Summary .144 CGM Clock Signals 145 External Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .147 Internal Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 Sources of Internal Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 POR Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 Interrupt Entry Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 Interrupt Recovery Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 List of Figures Page Freescale Semiconductor ...
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... PWM Automatic Phase Control . . . . . . . . . . . . . . . . . . . . . . .215 13-5 PWM Control Register (PWMCR 217 13-6 PWM Clock Control Register (PWMCCR 218 13-7 PWM Data Register 0 (PWMDR0 219 13-8 PWM Data Register 1 (PWMDR1 219 MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 Freescale Semiconductor Title List of Figures List of Figures Page Data Sheet ...
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... SCI Status Register 1 (SCS1 282 16-13 Flag Clearing Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285 16-14 SCI Status Register 2 (SCS2 286 16-15 SCI Data Register (SCDR .287 16-16 SCI Baud Rate Register (SCBR 288 Data Sheet 28 Title MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 List of Figures Page Freescale Semiconductor ...
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... Port C I/O Circuit 329 18-12 Port A LED Control Register (LEDA 330 18-13 Port D Data Register (PTD 331 18-14 Data Direction Register D (DDRD 332 18-15 Port D I/O Circuit 332 MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 Freescale Semiconductor Title Transmit/Receive Modes . . . . . . . . . . . . . . . . . . . . . . . . . . 312 List of Figures List of Figures Page ...
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... RC vs. Bus Frequency (3V @25° .379 24-3 MMIIC Signal Timings 383 25-1 48-Pin LQFP (Case #932-02 388 25-2 42-Pin SDIP (Case #858-01 389 A-1 A-2 Data Sheet 30 Title MC68HC08SR12 Block Diagram . . . . . . . . . . . . . . . . . . . . . 395 MC68HC08SR12 Memory Map . . . . . . . . . . . . . . . . . . . . . . 396 MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 List of Figures Page Freescale Semiconductor ...
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... READSP (Read Stack Pointer) Command . . . . . . . . . . . . . . . 177 10-9 RUN (Run User Program) Command . . . . . . . . . . . . . . . . . . . 177 11-1 Pin Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 11-2 Prescaler Selection 197 MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 Freescale Semiconductor Title Vector Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 CGMXCLK Clock Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 CGMXCLK Clock Selection ...
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... Port A Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322 18-3 PTB2 and PTB3 Pin Configurations . . . . . . . . . . . . . . . . . . . .325 18-4 Port B Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326 18-5 PTC0 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328 18-6 Port C Pin Functions 330 18-7 Port D Pin Functions 333 Data Sheet 32 Title MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 List of Tables Page Freescale Semiconductor ...
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... FLASH Memory Electrical Characteristics . . . . . . . . . . . . . . . 386 26-1 MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 391 A-1 A-2 A-3 A-4 MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 Freescale Semiconductor Title Summary of MC68HC08SR12 and MC68HC908SR12 Differences . . . . . . . . . . . . . . . . . . . . . 394 5V DC Electrical Characteristics 398 3V DC Electrical Characteristics 399 MC68HC08SR12 Order Numbers . . . . . . . . . . . . . . . . . . . . . 401 List of Tables ...
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... List of Tables Data Sheet 34 MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 List of Tables Freescale Semiconductor ...
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... MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 Freescale Semiconductor Section 1. General Description Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 Power Supply Pins (V DD Oscillator Pins (OSC1 and OSC2 External Reset Pin (RST External Interrupt Pin (IRQ1) ...
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... Serial communications interface module (SCI security feature is absolutely secure. However, Freescale’s strategy is to make reading or copying the FLASH difficult for unauthorized users. Data Sheet 36 MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 General Description 1 feature Freescale Semiconductor ...
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... Features of the CPU08 include the following: • • • MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 Freescale Semiconductor System Management Bus (SMBus), version 1.0/1.1 (Multi-master IIC bus) 14-channel, 10-bit analog-to-digital converter (ADC), with auto-scan mode for 4 channels Current sensor with programmable amplifier Temperature sensor (– ...
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... Fast 16/8 divide instruction • Binary-coded decimal (BCD) instructions • Optimization for controller applications • Efficient C language support 1.4 MCU Block Diagram Figure 1-1 Data Sheet 38 shows the structure of the MC68HC908SR12. MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 General Description Freescale Semiconductor ...
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M68HC08 CPU CPU ARITHMETIC/LOGIC REGISTERS UNIT (ALU) CONTROL AND STATUS REGISTERS — 96 BYTES USER FLASH — 12,288 BYTES USER RAM — 512 BYTES MONITOR ROM — 368 BYTES USER FLASH VECTORS — 38 BYTES OSCILLATORS AND CLOCK GENERATOR MODULE ...
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... PTD1/KBI1 PTD2/KBI2 PTD3/KBI3 NC: No connection Data Sheet VDD VSS 8 9 IRQ1 10 RST 11 12 Figure 1-2. 48-Pin LQFP Pin Assignments MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 General Description 36 VREFH 35 VREFL 34 OPIN2/ATD1 33 PTC7/ATD12 32 PTA0/ATD2 VSSAM 31 30 OPIN1/ATD0 29 PTB4/T2CH0 28 PTB5/T2CH1 27 PTB6/IRQ2 26 PTA6/T1CH0 PTD7/KBI7 25 Freescale Semiconductor ...
Page 41
... Pin Functions Description of pin functions are provided here. MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 Freescale Semiconductor VDDA 1 PTC5/ATD10 2 3 PTC4/ATD9 PTA5/ATD7 4 5 CGMXFC PTC3/ATD8 6 PTD0/KBI0 7 VDD 8 OSC1 9 OSC2 10 VSS 11 PTD1/KBI1 12 IRQ1 13 PTD2/KBI2 14 RST 15 PTD3/KBI3 16 PTB0/SDA0 17 PTB1/SCL0 18 PTB2/SDA1/TxD 19 PTB3/SCL1/RxD 20 PTD4/KBI4 21 Pins not available on 42-pin package ...
Page 42
... The MCU operates SS MCU 0.1 µ NOTE: Component values shown represent typical applications. Figure 1-4. Power Supply Bypassing Section 7. Oscillator (OSC) (CGM). MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 General Description Figure 1 and Section 8. Clock Freescale Semiconductor ...
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... Section 15. Analog-to-Digital Converter 1.6.9 External Filter Capacitor Pin (CGMXFC) CGMXFC is an external filter capacitor connection for the CGM. See Section 8. Clock Generator Module MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 Freescale Semiconductor Section 9. System Integration Module Section 19. External Interrupt ) DDA is the power supply pin for the analog circuits of the MCU. ...
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... Section 11. Timer Interface Module (MMIIC). Ports, Section 15. Analog-to-Digital (ADC), Section 13. Pulse Width Modulator Module. Section 18. Input/Output (I/O) Ports MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 General Description Section 14. (ADC). Section 18. (TIM), (ADC). Ports, Section 19. (TIM), (SCI), and Section 17. (PWM), and and (KBI). Freescale Semiconductor ...
Page 45
... Unimplemented Memory Locations Accessing an unimplemented location can cause an illegal address reset. In the memory map document, unimplemented locations are shaded. MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 Freescale Semiconductor Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Unimplemented Memory Locations . . . . . . . . . . . . . . . . . . . . . 45 Reserved Memory Locations . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Input/Output (I/O) Section Figure 2-1, includes: • ...
Page 46
... Mask option register, MOR • $FFFF; COP control register, COPCTL Data registers are shown in locations. Data Sheet 46 Figure 2-1 and in register figures in this document, Figure 2-2, Table 2-1 MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 Memory Map is a list of vector Freescale Semiconductor ...
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... MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 Freescale Semiconductor $0000 I/O Registers ↓ $005F $0060 ↓ 512 Bytes $025F $0260 Unimplemented ↓ 48,544 Bytes $BFFF $C000 FLASH Memory ↓ 12,288 Bytes $EFFF $F000 Unimplemented ↓ 3,584 Bytes $FDFF $FE00 SIM Break Status Register (SBSR) ...
Page 48
... MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 Memory Map Bit 0 PTA3 PTA2 PTA1 PTA0 PTB3 PTB2 PTB1 PTB0 PTC3 PTC2 PTC1 PTC0 PTD3 PTD2 PTD1 PTD0 DDRA3 DDRA2 DDRA1 DDRA0 DDRB3 DDRB2 DDRB1 DDRB0 DDRC3 DDRC2 DDRC1 DDRC0 DDRD3 DDRD2 DDRD1 DDRD0 Reserved Freescale Semiconductor ...
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... Unimplemented Write: Reset: Read: $0012 Unimplemented Write: Reset: Read: SCI Control Register 1 $0013 Write: (SCC1) Reset Unaffected Figure 2-2. Control, Status, and Data Registers (Sheet 2 of 12) MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 Freescale Semiconductor Bit LEDA5 LEDA4 LEDC7 LEDC6 LEDC5 LEDC4 ...
Page 50
... ICLKEN RCLKEN XCLKEN Indeterminate = Unimplemented MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 Memory Map Bit RWU SBK ORIE NEIE FEIE PEIE BKF RPF SCR2 SCR1 SCR0 KEYF 0 IMASKK MODEK ACKK KBIE3 KBIE2 KBIE1 KBIE0 IRQ2F 0 IMASK2 MODE2 ACK2 CDOEN SCIBDSRC Reserved Freescale Semiconductor ...
Page 51
... Timer 1 Channel 0 Status $0025 and Control Register Write: (T1SC0) Reset: Read: Timer 1 Channel 0 $0026 Register High Write: (T1CH0H) Reset Unaffected Figure 2-2. Control, Status, and Data Registers (Sheet 4 of 12) MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 Freescale Semiconductor Bit COPRS LVISTOP LVIRSTD LVIPWRD LVI5OR3 TOF ...
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... TSTOP 0 TRST Bit Bit Bit Bit CH0F CH0IE MS0B MS0A Indeterminate = Unimplemented MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 Memory Map Bit Bit ELS1B ELS1A TOV1 CH1MAX Bit Bit PS2 PS1 PS0 Bit Bit Bit Bit ELS0B ELS0A TOV0 CH0MAX Reserved Freescale Semiconductor ...
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... Read: PLL Multiplier Select $0039 Register Low Write: (PMSL) Reset: Read: PLL VCO Range Select $003A Register Write: (PMRS) Reset Unaffected Figure 2-2. Control, Status, and Data Registers (Sheet 6 of 12) MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 Freescale Semiconductor Bit Bit Bit CH1F ...
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... Reset: Read: $0043 Unimplemented Write: Reset: Read: $0044 Unimplemented Write: Reset Unaffected Figure 2-2. Control, Status, and Data Registers (Sheet 7 of 12) Data Sheet 54 Bit Indeterminate = Unimplemented MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 Memory Map Bit 0 RDS3 RDS2 RDS1 RDS0 Reserved Freescale Semiconductor ...
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... MMIIC Data Receive $004D Register Write: (MDDRR) Reset: Read: MMIIC CRC Data Register $004E Write: (MMCRDR) Reset Unaffected Figure 2-2. Control, Status, and Data Registers (Sheet 8 of 12) MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 Freescale Semiconductor Bit TBIF TBR2 TBR1 TBR0 MMAD7 MMAD6 MMAD5 MMAD4 ...
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... COCO AIEN ADCO ADCH4 ADIV2 ADIV1 ADIV0 ADICLK Indeterminate = Unimplemented MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 Memory Map Bit 0 0 MMBR2 MMBR1 MMBR0 PCH2 PCH1 PCH0 PCLK1 PCLK0 PHD3 PHD2 PHD1 PHD0 ADCH3 ADCH2 ADCH1 ADCH0 MODE1 MODE0 Reserved Freescale Semiconductor ...
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... Write: (SBSR) Reset: Note: Writing a logic 0 clears SBSW. Read: SIM Reset Status Register $FE01 Write: (SRSR) POR Unaffected Figure 2-2. Control, Status, and Data Registers (Sheet 10 of 12) MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 Freescale Semiconductor Bit ADx ADx ADx ADx ADx ...
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... IF5 IF4 IF3 IF14 IF13 IF12 IF11 BPR7 BPR6 BPR5 BPR4 Indeterminate = Unimplemented MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 Memory Map Bit IF2 IF1 IF10 IF9 IF8 IF7 IF17 IF16 IF15 HVEN MASS ERASE PGM BPR3 BPR2 BPR1 BPR0 Reserved Freescale Semiconductor ...
Page 59
... Mask Option Register (MOR)* $FF80 Write: Erased: Reset: * MOR is a non-volatile FLASH register; write by programming. Read: COP Control Register $FFFF Write: (COPCTL) Reset Unaffected Figure 2-2. Control, Status, and Data Registers (Sheet 12 of 12) MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 Freescale Semiconductor Bit Bit Bit ...
Page 60
... IRQ2 Vector (Low) $FFFA IRQ1 Vector (High) IF1 $FFFB IRQ1 Vector (Low) $FFFC SWI Vector (High) — $FFFD SWI Vector (Low) $FFFE Reset Vector (High) — $FFFF Reset Vector (Low) MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 Memory Map Vector Freescale Semiconductor ...
Page 61
... Before processing an interrupt, the CPU uses five bytes of the stack to save the contents of the CPU registers. NOTE: For M6805 compatibility, the H register is not stacked. MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 Freescale Semiconductor Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 Random-Access Memory (RAM) Data Sheet 61 ...
Page 62
... The stack pointer decrements during pushes and increments during pulls. NOTE: Be careful when using nested subroutines. The CPU may overwrite data in the RAM during a subroutine or during the interrupt stacking operation. Data Sheet 62 MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 Random-Access Memory (RAM) Freescale Semiconductor ...
Page 63
... This memory can be read, programmed, and erased from a single external supply. The program and erase operations are enabled through the use of an internal charge pump. MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 Freescale Semiconductor Section 4. FLASH Memory Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 FLASH Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 FLASH Page Erase Operation ...
Page 64
... No security feature is absolutely secure. However, Freescale’s strategy is to make reading or copying the FLASH difficult for unauthorized users. Data Sheet 64 Bit BPR7 BPR6 BPR5 BPR4 Unimplemented MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 FLASH Memory Bit 0 HVEN MASS ERASE PGM BPR3 BPR2 BPR1 BPR0 Freescale Semiconductor ...
Page 65
... PGM — Program Control Bit This read/write bit configures the memory for program operation. PGM is interlocked with the ERASE bit such that both bits cannot be equal set the same time. MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 Freescale Semiconductor $FE08 Bit ...
Page 66
... RAM. While these operations must be performed in the order as shown, but other unrelated operations may occur between the steps. Data Sheet 66 (10µs). nvs (1ms). Erase (5µs). nvh (1µs), the memory can be accessed again in read rcv MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 FLASH Memory Freescale Semiconductor ...
Page 67
... FLASH memory; the code must be executed from RAM. While these operations must be performed in the order as shown, but other unrelated operations may occur between the steps. MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 Freescale Semiconductor register. address range. (10µs). nvs (4ms) ...
Page 68
... Do not exceed t Characteristics. Data Sheet 68 (10µs). nvs (5µs). pgs (30µs). Prog (5µs). nvh (1µs), the memory can be accessed again in read rcv maximum. See 24.18 FLASH Memory Prog MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 FLASH Memory Freescale Semiconductor ...
Page 69
... Prog This row program algorithm assumes the row programmed are initially erased. Figure 4-3. FLASH Programming Flowchart MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 Freescale Semiconductor shows a flowchart representation for programming the 1 Set PGM bit 2 Write any data to any FLASH address within the row address range desired ...
Page 70
... Start address of FLASH block protect Data Sheet 70 $FE09 Bit BPR7 BPR6 BPR5 BPR4 Figure 4-4. FLASH Block Protect Register (FLBPR Figure 4-5. FLASH Block Protect Start Address MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 FLASH Memory Bit 0 BPR3 BPR2 BPR1 BPR0 16-bit memory address BPR[7:1] Freescale Semiconductor ...
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... FLASH memory, at $FFFF. With this mechanism, the protect start address can be XX00 or XX80 (at page boundaries) within the FLASH memory. Examples of protect start address: MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 Freescale Semiconductor BPR[7:0] Start of Address of Protect Range $00 or $01 The entire FLASH memory is protected. ...
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... FLASH Memory Data Sheet 72 MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 FLASH Memory Freescale Semiconductor ...
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... This section describes the configuration registers, CONFIG1 and CONFIG2; and the mask option register, MOR. The configuration registers enable or disable these options: MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 Freescale Semiconductor Configuration and Mask Option Registers (CONFIG & MOR) Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74 Configuration Register 1 (CONFIG1 Configuration Register 2 (CONFIG2) ...
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... MCU recommended that these registers be written immediately after reset. The configuration registers are located at $001D and $001F. The configurations register may be read at anytime. Data Sheet 74 Configuration and Mask Option Registers (CONFIG & MOR) Freescale Semiconductor Bit STOP_ ...
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... When the LVIPWRD bit is clear, setting the LVISTOP bit enables the LVI to operate during stop mode. Reset clears LVISTOP. (See Section 22. Low-Voltage Inhibit MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 Freescale Semiconductor Configuration and Mask Option Registers (CONFIG & MOR) Configuration and Mask Option Registers (CONFIG & MOR) $001F Bit 7 ...
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... LVI’s turn-on time and there exists a period in start-up where the LVI is not protecting the MCU. Data Sheet 76 Configuration and Mask Option Registers (CONFIG & MOR) Freescale Semiconductor (LVI).) (LVI).) (LVI).) The voltage mode selected for the LVI voltage trip points for each of MC68HC908SR12• ...
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... Module (CGM) Reset clears this bit. MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 Freescale Semiconductor Configuration and Mask Option Registers (CONFIG & MOR) Configuration and Mask Option Registers (CONFIG & MOR STOP instruction enabled 0 = STOP instruction treated as illegal opcode (COP) ...
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... Reset clears the CDOEN bit PCO/PWMO/CD pin enabled as CD output pin PTC0/PWM/CD pin disabled as CD output pin, Data Sheet 78 Configuration and Mask Option Registers (CONFIG & MOR) Freescale Semiconductor and subsection OSCCLK0 ...
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... Bits 5–0 — Should be left as 1’s. MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 Freescale Semiconductor Configuration and Mask Option Registers (CONFIG & MOR) Configuration and Mask Option Registers (CONFIG & MOR Internal data bus clock Oscillator clock, CGMXCLK, is used as clock source for SCI ...
Page 80
... NOTE: The internal oscillator is a free running oscillator and is available after each POR or reset turned-off in stop mode by clearing the STOP_ICLKEN bit in CONFIG2. Data Sheet 80 Configuration and Mask Option Registers (CONFIG & MOR) Freescale Semiconductor OSC2 pin — — Not used ICLK f Internal oscillator generates the CGMXCLK ...
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... M68HC05 CPU. The CPU08 Reference Manual (Freescale document order number CPU08RM/AD) contains a description of the CPU instruction set, addressing modes, and architecture. MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 Freescale Semiconductor Section 6. Central Processor Unit (CPU) Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Index Register ...
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... Low-power stop and wait modes 6.4 CPU Registers Figure 6-1 the memory map. Data Sheet 82 shows the five CPU registers. CPU registers are not part of MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 Central Processor Unit (CPU) Freescale Semiconductor ...
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... Accumulator The accumulator is a general-purpose 8-bit register. The CPU uses the accumulator to hold operands and the results of arithmetic/logic operations. Read: Write: Reset: MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 Freescale Semiconductor Figure 6-1. CPU Registers Bit Unaffected by reset Figure 6-2. Accumulator (A) Central Processor Unit (CPU) ...
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... The CPU uses the contents of the stack pointer to determine the conditional address of the operand. Data Sheet 84 Bit Indeterminate Figure 6-3. Index Register (H:X) MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 Central Processor Unit (CPU) Bit Freescale Semiconductor ...
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... Read: Write: Reset: 6.4.5 Condition Code Register The 8-bit condition code register contains the interrupt mask and five flags that indicate the results of the instruction just executed. Bits 6 and MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 Freescale Semiconductor Bit ...
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... The DAA instruction uses the states of the H and C flags to determine the appropriate correction factor Carry between bits 3 and carry between bits 3 and 4 Data Sheet 86 Bit Indeterminate Figure 6-6. Condition Code Register (CCR) MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 Central Processor Unit (CPU Bit Freescale Semiconductor ...
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... Z — Zero flag The CPU sets the zero flag when an arithmetic operation, logic operation, or data manipulation produces a result of $00. MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 Freescale Semiconductor 1 = Interrupts disabled 0 = Interrupts enabled 1 = Negative result 0 = Non-negative result 1 = Zero result ...
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... Clears the interrupt mask (I bit) in the condition code register, enabling interrupts. After exit from wait mode by interrupt, the I bit remains clear. After exit by reset, the I bit is set. • Disables the CPU clock Data Sheet 88 MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 Central Processor Unit (CPU) Freescale Semiconductor ...
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... Instruction Set Summary 6.9 Opcode Map See MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 Freescale Semiconductor Clears the interrupt mask (I bit) in the condition code register, enabling external interrupts. After exit from stop mode by external interrupt, the I bit remains clear. After exit by reset, the I bit is set. ...
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... SP2 9EDB IMM DIR EXT IX2 – IX1 SP1 9EE4 ff 4 SP2 9ED4 DIR INH 48 1 INH 58 1 IX1 SP1 9E68 ff 5 DIR INH 47 1 INH 57 1 IX1 SP1 9E67 DIR (b0 DIR (b1 DIR (b2 DIR (b3 DIR (b4 DIR (b5 DIR (b6 DIR (b7 Freescale Semiconductor ...
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... BNE rel Branch if Not Equal BPL rel Branch if Plus BRA rel Branch Always MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 Freescale Semiconductor Description PC ← (PC rel ? ( ← (PC rel ? ( ← (PC rel ? (N ⊕ ← (PC +rel ? ( ⊕ – – – – – – REL PC ← (PC rel ? ( ← (PC rel ? ( ← ...
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... DIR (b2 DIR (b3 DIR (b4 DIR (b5 DIR (b6 DIR (b7 DIR (b0 DIR (b1 DIR (b2 DIR (b3 DIR (b4 DIR (b5 DIR (b6 DIR (b7 DIR (b0 DIR (b1 DIR (b2 DIR (b3 DIR (b4 DIR (b5 DIR (b6 DIR (b7 DIR IMM IMM IX1 IX SP1 9E61 DIR INH 4F 1 INH 5F 1 INH 8C 1 IX1 SP1 9E6F ff 4 Freescale Semiconductor ...
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... DECX Decrement DEC opr,X DEC ,X DEC opr,SP DIV Divide MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 Freescale Semiconductor Description (A) – (M) M ← (M) = $FF – (M) A ← (A) = $FF – (M) X ← (X) = $FF – (M) M ← (M) = $FF – (M) M ← (M) = $FF – (M) M ← (M) = $FF – (M) (H:X) – ...
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... FC 2 DIR EXT IX2 IX1 IMM DIR EXT IX2 – IX1 SP1 9EE6 ff 4 SP2 9ED6 IMM – DIR IMM DIR EXT IX2 – IX1 SP1 9EEE ff 4 SP2 9EDE DIR INH 48 1 INH 58 1 IX1 SP1 9E68 ff 5 Freescale Semiconductor ...
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... PULH Pull H from Stack PULX Pull X from Stack ROL opr ROLA ROLX Rotate Left through Carry ROL opr,X ROL ,X ROL opr,SP MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 Freescale Semiconductor Description ← (M) (M) Destination Source H:X ← (H: (IX+D, DIX+) X:A ← (X) × (A) M ← –(M) = $00 – (M) A ← ...
Page 96
... INH 56 1 IX1 SP1 9E66 INH IMM DIR EXT IX2 IX1 SP1 9EE2 ff 4 SP2 9ED2 DIR EXT IX2 – IX1 SP1 9EE7 ff 4 SP2 9ED7 – DIR DIR EXT IX2 – IX1 SP1 9EEF ff 4 SP2 9EDF Freescale Semiconductor ...
Page 97
... TST opr,SP TSX Transfer SP to H:X TXA Transfer TXS Transfer H MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 Freescale Semiconductor Description A ← (A) – (M) PC ← (PC Push (PCL) SP ← (SP) – 1; Push (PCH) SP ← (SP) – 1; Push (X) SP ← (SP) – 1; Push (A) SP ← (SP) – 1; Push (CCR) SP ← (SP) – ← 1 PCH ← ...
Page 98
... Logical AND | Logical OR ⊕ Logical EXCLUSIVE Contents of –( ) Negation (two’s complement) # Immediate value « Sign extend ← Loaded with ? If : Concatenated with Set or cleared — Not affected MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 Central Processor Unit (CPU) Effect on CCR Freescale Semiconductor ...
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Bit Manipulation Branch Read-Modify-Write DIR DIR REL DIR INH MSB LSB BRSET0 BSET0 BRA NEG NEGA 3 DIR 2 DIR 2 REL 2 DIR 1 INH ...
Page 100
... Central Processor Unit (CPU) Data Sheet 100 MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 Central Processor Unit (CPU) Freescale Semiconductor ...
Page 101
... MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 Freescale Semiconductor Section 7. Oscillator (OSC) Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 Clock Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 CGM Reference Clock Selection . . . . . . . . . . . . . . . . . . . . 104 TBM Reference Clock Selection . . . . . . . . . . . . . . . . . . . . 105 Internal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 RC Oscillator 106 X-tal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 I/O Signals ...
Page 102
... The RC and crystal oscillator cannot run concurrently; one is disabled while the other is selected; because the RC and x-tal circuits share the same OSC1 pin. Figure Data Sheet 102 7-1. shows the block diagram of the oscillator module. MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 Oscillator (OSC) Freescale Semiconductor ...
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... OSCSEL1 OSCSEL0 7.3 Clock Selection Reference clocks are selectable for the following sub-systems: • • MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 Freescale Semiconductor To CGM and others CGMXCLK MOR MUX XCLK X-TAL OSCILLATOR OSC1 OSC2 Figure 7-1. Oscillator Module Block Diagram CGMXCLK and CGMRCLK — Reference clock for clock generator module (CGM) and other MCU sub-systems other than TBM and COP ...
Page 104
... BUS RC oscillator generates the CGMXCLK. RCCLK f Internal oscillator is available after each POR BUS or reset. Inverting X-tal oscillator generates the CGMXCLK. XCLK output of Internal oscillator is available after each POR X-TAL or reset. MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 Oscillator (OSC Bit Comments Freescale Semiconductor ...
Page 105
... Due to the simplicity of the internal oscillator, it does not have the accuracy and stability of the RC oscillator or the x-tal oscillator. Therefore, the ICLK is not suitable where an accurate bus clock is required and it should not be used as the CGMRCLK to the CGM PLL. MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 Freescale Semiconductor (CONFIG2). $001D Bit 7 6 ...
Page 106
... Data Sheet 106 shows the logical representation of components of the From SIM SIMOSCEN CONFIG2 STOP_ICLKEN Figure 7-4. Internal Oscillator EXT EXT MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 Oscillator (OSC) From SIM To Clock Selection MUX and COP BUS CLOCK ICLK EN INTERNAL OSCILLATOR OSC2 Freescale Semiconductor ...
Page 107
... The oscillator configuration uses five components: • • • • • MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 Freescale Semiconductor From SIM SIMOSCEN CONFIG2 STOP_RCLKEN MCU Section 24. for component value requirements. V Figure 7-5 ...
Page 108
... OSC1 pin is an input to the crystal oscillator amplifier or the input to the RC oscillator circuit. Data Sheet 108 From SIM SIMOSCEN CONFIG2 OSC1 for component value requirements. Figure 7-6. Crystal Oscillator ) is included in the diagram to follow strict Pierce S MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 Oscillator (OSC) To Clock Selection MUX XCLK OSC2 Freescale Semiconductor ...
Page 109
... The OSCCLK is the reference clock that drives the timebase module. See 7.8 Low Power Modes The WAIT and STOP instructions put the MCU in low-power consumption standby modes. MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 Freescale Semiconductor Section 12. Timebase Module Oscillator (OSC) Oscillator (OSC) Low Power Modes (TBM). ...
Page 110
... The internal oscillator clock continues operation in stop mode. It can be disabled by setting the STOP_ICLKEN bit to logic 1 before entering stop mode. 7.9 Oscillator During Break Mode The oscillator continues to drive CGMXCLK when the device enters the break state. Data Sheet 110 MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 Oscillator (OSC) Freescale Semiconductor ...
Page 111
... MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 Freescale Semiconductor Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113 Oscillator Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 Phase-Locked Loop Circuit (PLL 116 PLL Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 Acquisition and Tracking Modes . . . . . . . . . . . . . . . . . . . . 118 Manual and Automatic PLL Bandwidth Modes 118 Programming the PLL ...
Page 112
... Special Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .136 CGM During Break Interrupts 136 Acquisition/Lock Time Specifications . . . . . . . . . . . . . . . . . . . 137 Acquisition/Lock Time Definitions .137 Parametric Influences on Reaction Time . . . . . . . . . . . . . . 137 Choosing a Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 Clock Generator Module (CGM) Freescale Semiconductor ...
Page 113
... Figure 8-1 Figure 8-2 MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 Freescale Semiconductor Phase-locked loop with output frequency in integer multiples of an integer dividend of the crystal reference Low-frequency crystal operation with low-power operation and high-output frequency resolution Programmable prescaler for power-of-two increases in frequency ...
Page 114
... Figure 8-1. CGM Block Diagram MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 Clock Generator Module (CGM) To SIM (and COP) To Timebase Module (TBM) T0 ADC, Analog Module A CGMOUT ÷ SIM B S* SIMDIV2 *WHEN CGMOUT = B From SIM CGMPCLK CGMVCLK To PWM, Analog Module CGMINT To SIM Freescale Semiconductor ...
Page 115
... When AUTO = 0, PLLF and LOCK read as clear. 3. When AUTO = 1, ACQ is read-only. 4. When PLLON = 0 or VRS7:VRS0 = $0, BCS is forced clear and is read-only. 5. When PLLON = 1, the PLL programming register is read-only. 6. When BCS = 1, PLLON is forced set and is read-only. MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 Freescale Semiconductor Bit PLLF PLLIE ...
Page 116
... Modulo VCO frequency divider • Phase detector • Loop filter • Lock detector Data Sheet 116 for detailed oscillator circuit description. Section 13. Pulse Width Modulator (PWM) MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 Clock Generator Module (CGM) for detailed description on for detailed Freescale Semiconductor ...
Page 117
... CGMVDV, and the final reference clock, CGMRDV. Therefore, the speed of the lock detector is directly proportional to the final reference frequency, f condition based on this comparison. MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 Freescale Semiconductor is equal to the nominal center-of-range VRS , (38.4 kHz) times a linear factor, L, and a power-of-two NOM ...
Page 118
... Data Sheet 118 8.6.2 PLL Bandwidth Control 8.4.8 Base Clock Selector 8.6.2 PLL Bandwidth Control for information and precautions on using interrupts.) MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 Clock Generator Module (CGM) Register.) Circuit.) The PLL is Register.) If PLL 8.4.8 Base Clock Selector Freescale Semiconductor ...
Page 119
... Such systems typically operate well below f BUSMAX MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 Freescale Semiconductor The ACQ bit (See 8.6.2 PLL Bandwidth Control read-only indicator of the mode of the filter. (See Acquisition and Tracking ...
Page 120
... VCLKDES and f BUS P × VCLK CGMPCLK MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 Clock Generator Module (CGM) , after entering tracking mode , or the desired VCO BUSDES is governed by the VCLK × P × BUS , and the RCLK /R. For RCLK Freescale Semiconductor ...
Page 121
... Calculate N: 4. Calculate and verify the adequacy of the VCO and bus MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 Freescale Semiconductor The relationship between the VCO frequency, f reference frequency, f RCLK f VCLK where N is the integer range multiplier, between 1 and 4095. In cases where desired bus frequency has some tolerance, ...
Page 122
... NOM ≤ -------------------------- – VRS VCLK . For proper operation, f VCLKDES VCLKDES VCLK. MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 Clock Generator Module (CGM 38.4kHz NOM ⎞ ⎟ ⎠ f NOM NOM E × VCLK VRS must be within the VCLK , and f must be as close as VRS Freescale Semiconductor ...
Page 123
... MHz 32 MHz 32 MHz 32 MHz MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 Freescale Semiconductor a. In the PRE bits of the PLL control register (PCTL), program the binary equivalent the VPR bits of the PLL control register (PCTL), program the binary equivalent the PLL multiplier select register low (PMSL) and the PLL multiplier select register high (PMSH), program the binary equivalent of N ...
Page 124
... PLL, so that the PLL would be disabled and the oscillator clock would be forced as the source of the base clock. Data Sheet 124 8.4.6 Programming the PLL Circuit.) MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 Clock Generator Module (CGM) Freescale Semiconductor ...
Page 125
... PLL performance.) 8.5 I/O Signals The following paragraphs describe the CGM I/O signals. MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 Freescale Semiconductor shows the external components for the PLL: Bypass capacitor, C BYP Filter network 8 ...
Page 126
... DDA carefully for maximum noise immunity and place bypass DDA ) SSA pin to the same voltage potential as the V carefully for maximum noise immunity and place bypass SSA MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 Clock Generator Module (CGM) pin. DD pin. SS Freescale Semiconductor ...
Page 127
... CGM Registers The following registers control and monitor operation of the CGM: • • • • • MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 Freescale Semiconductor PLL control register (PCTL) (See 8.6.1 PLL Control Register.) PLL bandwidth control register (PBWC) (See 8.6.2 PLL Bandwidth Control ...
Page 128
... PLL control register clears the PLLF bit. Data Sheet 128 $0036 Bit PLLF PLLIE PLLON BCS Unimplemented Figure 8-4. PLL Control Register (PCTL) MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 Clock Generator Module (CGM Bit 0 PRE1 PRE0 VPR1 VPR0 Freescale Semiconductor ...
Page 129
... PLLON bit is set. Reset clears these bits. These prescaler bits affects the relationship between the VCO clock and the final system bus clock. MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 Freescale Semiconductor 1 = PLL PLL off Circuit.) Reset clears the BCS bit CGMPCLK divided by two drives CGMOUT 0 = CGMXCLK divided by two drives CGMOUT 8 ...
Page 130
... PRE1 and PRE0 PLL, and 8.6.4 PLL VCO Range Select Table 8-3. VPR1 and VPR0 Programming VPR1 and VPR0 MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 Clock Generator Module (CGM) Prescaler Multiplier 8.4.3 PLL Circuits, 8.4.6 . VRS VCO Power-of-Two Range Multiplier Freescale Semiconductor ...
Page 131
... PLL is in acquisition or tracking mode. In automatic bandwidth control mode (AUTO = 1), the last-written value from manual operation is stored in a temporary location and is recovered when manual operation resumes. Reset clears this bit, enabling acquisition mode. MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 Freescale Semiconductor $0037 Bit LOCK ...
Page 132
... Bit Unimplemented $0039 Bit MUL7 MUL6 MUL5 MUL4 PLL.) A value of $0000 in the multiplier select MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 Clock Generator Module (CGM Bit 0 MUL11 MUL10 MUL9 MUL8 Bit 0 MUL3 MUL2 MUL1 MUL0 8.4.3 PLL Circuits and 8.4.6 Freescale Semiconductor ...
Page 133
... VCO range select bits are all clear. The PLL VCO range select register must be programmed correctly. Incorrect programming can result in failure of the PLL to achieve lock. MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 Freescale Semiconductor $003A Bit ...
Page 134
... The default divide value recommended for all applications. Data Sheet 134 $003B Bit Unimplemented PLL.) RDS[3:0] cannot be written when the 8.4.7 Special Programming MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 Clock Generator Module (CGM Bit 0 RDS3 RDS2 RDS1 RDS0 8.4.3 PLL Circuits and 8.4.6 Exceptions.) Reset Freescale Semiconductor ...
Page 135
... PLL is to wake the MCU from wait mode, such as when the PLL is first enabled and waiting for LOCK or LOCK is lost. MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 Freescale Semiconductor Clock Generator Module (CGM) Clock Generator Module (CGM) Interrupts ...
Page 136
... With BCFE at logic 0 (its default state), software can read and write the PLL control register during the break state without affecting the PLLF bit. Data Sheet 136 9.8.3 SIM Break Flag Control MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 Clock Generator Module (CGM) Freescale Semiconductor ...
Page 137
... These reaction times are not constant, however. Many factors directly and indirectly affect the acquisition time. MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 Freescale Semiconductor Clock Generator Module (CGM) Clock Generator Module (CGM) Acquisition/Lock Time Specifications Data Sheet ...
Page 138
... This frequency is the input to the phase RDV and the R value programmed in the reference divider. XCLK Circuits, 8.4.6 Programming the Register.) 8.9.3 Choosing a MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 Clock Generator Module (CGM) PLL, and 8.6.5 PLL Filter.) . The DDA Freescale Semiconductor ...
Page 139
... PLL. The PLL is also dependent on reference frequency and supply voltage. Either of the filter networks in a 32.768kHz reference clock (CGMRCLK). applications requiring better stability. applications where stability is not critical. MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 Freescale Semiconductor 8.9.2 Parametric Influences on Reaction Figure 8-10 Figure 8-10 CGMXFC 10 kΩ 0.01 µF 0.033 µ ...
Page 140
... Clock Generator Module (CGM) Data Sheet 140 MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 Clock Generator Module (CGM) Freescale Semiconductor ...
Page 141
... MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 Freescale Semiconductor Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 SIM Bus Clock Control and Generation . . . . . . . . . . . . . . . . . 144 Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 Clock Start-up from POR or LVI Reset 145 Clocks in Stop Mode and Wait Mode . . . . . . . . . . . . . . . . . 146 Reset and System Initialization 146 External Pin Reset ...
Page 142
... SIM Break Status Register . . . . . . . . . . . . . . . . . . . . . . . . . 162 SIM Reset Status Register . . . . . . . . . . . . . . . . . . . . . . . . 163 SIM Break Flag Control Register . . . . . . . . . . . . . . . . . . . . 164 Figure 9-1. Table 9-1 shows the internal signal names used in this section. MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 System Integration Module (SIM summary of the SIM Freescale Semiconductor ...
Page 143
... Internal address bus IDB Internal data bus PORRST Signal from the power-on reset module to the SIM IRST Internal reset signal R/W Read/write signal MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 Freescale Semiconductor STOP/WAIT CONTROL SIM COUNTER ÷ 2 CLOCK CLOCK GENERATORS CONTROL POR CONTROL ...
Page 144
... IF4 IF3 IF14 IF13 IF12 IF11 Unimplemented (CGM).) MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 System Integration Module (SIM Bit 0 SBSW Note 0 ILAD 0 LVI IF2 IF1 IF10 IF9 IF8 IF7 IF17 IF16 IF15 Reserved Figure 9-3. This clock can come Section Freescale Semiconductor ...
Page 145
... ICLK cycle POR timeout has completed. The RST pin is driven low by the SIM during this entire period. The IBUS clocks start upon completion of the timeout. MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 Freescale Semiconductor OSCCLK CGMXCLK ICLK ...
Page 146
... An internal reset clears the SIM counter (see 9.5 SIM Counter), but an external reset does not. Each of the resets sets a corresponding bit in the SIM reset status register (SRSR). (See Data Sheet 146 MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 System Integration Module (SIM) 9.7.2 Stop Mode.) 9.8 SIM Registers.) Freescale Semiconductor ...
Page 147
... SIM forces the RST pin low. The internal reset signal then follows the sequence from the falling edge of RST shown in Figure MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 Freescale Semiconductor shows the relative timing. Table 9-2. PIN Bit Set Timing Reset Type ...
Page 148
... RST PULLED LOW BY MCU 32 CYCLES Figure 9-5. Internal Reset Timing ILLEGAL ADDRESS RST ILLEGAL OPCODE RST COPRST LVI POR Figure 9-6. Sources of Internal Reset MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 System Integration Module (SIM) 32 CYCLES VECTOR HIGH INTERNAL RESET Freescale Semiconductor ...
Page 149
... RST or the IRQ1 pin. This prevents the COP from becoming disabled as a result of external noise. During a break state, V TST MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 Freescale Semiconductor 4096 32 32 CYCLES CYCLES Figure 9-7 ...
Page 150
... The SIM actively pulls down the RST pin for all internal reset sources. Data Sheet 150 voltage falls to the LVI voltage. The LVI bit in the SIM reset TRIPF Section 10. Monitor ROM MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 System Integration Module (SIM) (MON).) When MODRST Freescale Semiconductor ...
Page 151
... The SIM counter is free-running after all reset states. (See 9.4.2 Active Resets from Internal Sources internal reset recovery sequences.) MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 Freescale Semiconductor System Integration Module (SIM) System Integration Module (SIM) SIM Counter (See 9.7.2 Stop Mode ...
Page 152
... SP – – – – CCR SP – – – CCR – 1[15:8] PC – 1[7:0] MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 System Integration Module (SIM) VECT H VECT L START ADDR V DATA H V DATA L OPCODE OPCODE OPERAND Freescale Semiconductor ...
Page 153
... The arbitration result is a constant that the CPU uses to determine which vector to fetch. Once an interrupt is latched by the SIM, no other interrupt can take precedence, regardless of priority, until the latched interrupt is serviced (or the I bit is cleared). (See MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 Freescale Semiconductor Figure 9-10.) FROM RESET BREAK I BIT SET? ...
Page 154
... Data Sheet 154 CLI LDA #$FF INT1 PSHH INT1 INTERRUPT SERVICE ROUTINE PULH RTI INT2 PSHH INT2 INTERRUPT SERVICE ROUTINE PULH RTI . Figure 9-11 Interrupt Recognition Example MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 System Integration Module (SIM) Figure 9-11 BACKGROUND ROUTINE Freescale Semiconductor ...
Page 155
... IF6–IF1 — Interrupt Flags 6–1 These flags indicate the presence of interrupt requests from the sources shown in Bit 0 and Bit 1 — Always read 0 MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 Freescale Semiconductor Table 9-3 summarizes the interrupt sources and the interrupt $FE04 Bit 7 ...
Page 156
... IF5 TIM1 Channel 1 $FFF3 $FFF4 IF4 TIM1 Channel 0 $FFF5 $FFF6 IF3 PLL $FFF7 $FFF8 IF2 IRQ2 $FFF9 $FFFA IF1 IRQ1 $FFFB $FFFC SWI $FFFD $FFFE Reset $FFFF MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 System Integration Module (SIM) Interrupt Source Freescale Semiconductor ...
Page 157
... These flags indicate the presence of interrupt requests from the sources shown in 9.6.1.6 Interrupt Status Register 3 Address: Read: Write: Reset: IF17–IF15 — Interrupt Flags 17–15 These flags indicate the presence of an interrupt request from the source shown in MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 Freescale Semiconductor $FE05 Bit IF14 IF13 IF12 ...
Page 158
... Upon leaving break mode, execution of the second step will clear the flag as normal. Data Sheet 158 (BRK).) The SIM puts the CPU into the MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 System Integration Module (SIM) (See Freescale Semiconductor ...
Page 159
... If the COP disable bit, COPD, in the mask option register is logic 0, then the computer operating properly module (COP) is enabled and remains active in wait mode. Figure 9-16 MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 Freescale Semiconductor Figure 9-15 shows the timing for wait mode entry. IAB WAIT ADDR ...
Page 160
... IDB $A6 $A6 $A6 $01 Figure 9-16. Wait Recovery from Interrupt or Break 32 CYCLES CYCLES $6E0B $A6 $A6 $A6 Figure 9-17. Wait Recovery from Internal Reset MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 System Integration Module (SIM) $00FF $00FE $00FD $00FC $0B $6E 32 RST VCT H RST VCT L Freescale Semiconductor ...
Page 161
... Figure 9-19. Stop Mode Recovery from Interrupt or Break 9.8 SIM Registers The SIM has three memory-mapped registers: • • • MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 Freescale Semiconductor Figure 9-18 shows stop mode entry timing. IAB STOP ADDR STOP ADDR + 1 IDB PREVIOUS DATA R/W instruction ...
Page 162
... See if wait mode or stop mode was exited by ; break. ;If RETURNLO is not zero, ;then just decrement low byte. ;Else deal with high byte, too. ;Point to WAIT/STOP opcode. ;Restore H register. MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 System Integration Module (SIM Bit 0 SBSW Note 0 Freescale Semiconductor ...
Page 163
... PIN — External Reset Bit COP — Computer Operating Properly Reset Bit ILOP — Illegal Opcode Reset Bit ILAD — Illegal Address Reset Bit (opcode fetches only) LVI — Low-Voltage Inhibit Reset Bit MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 Freescale Semiconductor $FE01 Bit POR ...
Page 164
... MCU break state. To clear status bits during the break state, the BCFE bit must be set Status bits clearable during break 0 = Status bits not clearable during break Data Sheet 164 $FE03 Bit BCFE Reserved MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 System Integration Module (SIM Bit Freescale Semiconductor ...
Page 165
... V vector addresses $FFFE and $FFFF are blank, thus reducing the hardware requirements for in-circuit programming. MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 Freescale Semiconductor Section 10. Monitor ROM (MON) Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .166 Entering Monitor Mode ...
Page 166
... No security feature is absolutely secure. However, Freescale’s strategy is to make reading or copying the FLASH difficult for unauthorized users. Data Sheet 166 1 Figure 10-1 shows an example circuit used to enter monitor MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 Monitor ROM (MON reset vector is TST , is applied to TST Freescale Semiconductor ...
Page 167
... SW2, SW3, and SW4: Position D — Enter monitor mode using 32.768kHz XTAL and internal PLL. 3. See Table 24-5 for IRQ1 voltage level requirements. 4. See Table 10-1 for other monitor mode entry configurations. MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 Freescale Semiconductor V TST (SEE NOTE 3) 10 kΩ 4.9152MHz/9.8304MHz C 6– ...
Page 168
... MHz with PTC1 high (PLL off) TST (this can be implemented through the internal DD IRQ1 pullup; PLL off) (this setting initiates the PLL to boost the external SS 32.768 kHz to an internal bus frequency of 2.4576 MHz) MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 Monitor ROM (MON) Freescale Semiconductor ...
Page 169
Table 10-1. Monitor Mode Signal Requirements and Options Address IRQ1 RST $FFFE/ PTA2 PTA1 $FFFF X GND TST TST TST TST ...
Page 170
... IRQ1 pin in the TST MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 Monitor ROM (MON) is applied to IRQ1. TST then all port A pin TST on IRQ1 (condition set 1), TST is applied to either IRQ1 TST is maintained on the TST is applied to RST after TST was applied to TST is TST Freescale Semiconductor ...
Page 171
... The alternate vectors are in the $FE page instead of the $FF page and allow code execution from the internal monitor firmware instead of user code. MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 Freescale Semiconductor shows a simplified diagram of the monitor mode entry when POR RESET IS VECTOR ...
Page 172
... Figure 10-4. Break Transaction MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 Monitor ROM (MON) Functions Break SWI SWI Vector Vector Vector Low High Low $FFFD $FFFC $FFFD $FEFD $FEFC $FEFD NEXT START STOP BIT 5 BIT 6 BIT 7 BIT BIT 2-STOP BIT DELAY BEFORE ZERO ECHO Freescale Semiconductor ...
Page 173
... See Characteristics 10.4.5 Commands The monitor ROM firmware uses these commands: • • • MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 Freescale Semiconductor lists external frequencies required to achieve a standard and 24.8 5.0V Control Timing Table 10-3. Monitor Baud Rate Selection External IRQ1 PTC1 ...
Page 174
... ADDRESS ADDRESS ADDRESS READ HIGH HIGH LOW Figure 10-5. Read Transaction ADDRESS ADDRESS ADDRESS WRITE HIGH HIGH LOW Figure 10-6. Write Transaction MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 Monitor ROM (MON) ADDRESS DATA LOW RETURN ADDRESS DATA DATA LOW Freescale Semiconductor ...
Page 175
... A brief description of each monitor mode command is given in Table 10-4 Description Operand Returned Description Operand Returned MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 Freescale Semiconductor through Table 10-9. Table 10-4. READ (Read Memory) Command Read byte from memory 2-byte address in high-byte:low-byte order Data Returns contents of specified address ...
Page 176
... FROM HOST IREAD IREAD ECHO Table 10-7. IWRITE (Indexed Write) Command Write to last address accessed + 1 Single data byte None $19 Command Sequence FROM HOST DATA DATA IWRITE IWRITE ECHO MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 Monitor ROM (MON) DATA DATA RETURN Freescale Semiconductor ...
Page 177
... Description Operand Returned Description Operand Returned MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 Freescale Semiconductor Table 10-8. READSP (Read Stack Pointer) Command Reads stack pointer None Returns incremented stack pointer value ( high-byte:low- Data byte order Opcode ...
Page 178
... Data Sheet 178 HIGH BYTE OF INDEX REGISTER CONDITION CODE REGISTER ACCUMULATOR LOW BYTE OF INDEX REGISTER HIGH BYTE OF PROGRAM COUNTER LOW BYTE OF PROGRAM COUNTER Figure 10-7. Stack Pointer at Monitor Mode Entry MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 Monitor ROM (MON Figure 10-8.) Freescale Semiconductor ...
Page 179
... RAM. The mass erase operation clears the security code locations so that all eight security bytes become $FF (blank). MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 Freescale Semiconductor 4096 + 32 ICLK CYCLES 256 BUS CYCLES (MINIMUM) FROM HOST ...
Page 180
... Monitor ROM (MON) Data Sheet 180 MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 Monitor ROM (MON) Freescale Semiconductor ...
Page 181
... TIM Counter Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 11.10.3 TIM Counter Modulo Registers . . . . . . . . . . . . . . . . . . . . . 199 11.10.4 TIM Channel Status and Control Registers . . . . . . . . . . . . 200 11.10.5 TIM Channel Registers 203 MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 Freescale Semiconductor Section 11. Timer Interface Module (TIM) Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 Pin Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 Functional Description ...
Page 182
... Programmable TIM clock input with 7-frequency internal bus clock prescaler selection • Free-running or modulo up-count operation • Toggle any channel pin on overflow • TIM counter stop and reset bits Data Sheet 182 MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 Timer Interface Module (TIM) Figure 11 Freescale Semiconductor ...
Page 183
... The two TIM channels (per timer) are programmable independently as input capture or output compare channels. MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 Freescale Semiconductor 11-1. The generic pin names appear in the text that follows. Table 11-1. Pin Name Conventions TIM Generic Pin Names: ...
Page 184
... MS1A Figure 11-1. TIM Block Diagram summarizes the timer registers. MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 Timer Interface Module (TIM) TOF INTERRUPT LOGIC TOIE TOV0 PORT CH0MAX T[1,2]CH0 LOGIC INTERRUPT LOGIC CH0IE TOV1 PORT CH1MAX T[1,2]CH1 LOGIC INTERRUPT LOGIC CH1IE Freescale Semiconductor ...
Page 185
... Reset: Read: Timer 1 Channel 0 $0027 Write: Register Low (T1CH0L) Reset: Read: Timer 1 Channel 1 Status $0028 and Control Register Write: (T1SC1) Reset: Figure 11-2. TIM I/O Register Summary (Sheet MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 Freescale Semiconductor Bit TOF 0 TOIE TSTOP 0 TRST Bit 15 ...
Page 186
... Bit Bit Bit Bit CH0F CH0IE MS0B MS0A Bit Indeterminate after reset = Unimplemented MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 Timer Interface Module (TIM Bit Bit Bit 0 0 PS2 PS1 PS0 Bit Bit Bit Bit ELS0B ELS0A TOV0 CH0MAX Bit 8 Freescale Semiconductor ...
Page 187
... When an active edge occurs on the pin of an input capture channel, the TIM latches the contents of the TIM counter into the TIM channel registers, TCHxH:TCHxL. The polarity of the active edge is programmable. Input captures can generate TIM CPU interrupt requests. MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 Freescale Semiconductor Bit Bit 7 ...
Page 188
... Writing a larger value in an output compare interrupt routine (at the end of the current pulse) could cause two output compares to occur in the same counter overflow period. Data Sheet 188 11.5.3 Output Compare. The pulses are MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 Timer Interface Module (TIM) Freescale Semiconductor ...
Page 189
... TIM to clear the channel pin on output compare if the state of the PWM pulse is logic 1. Program the TIM to set the pin if the state of the PWM pulse is logic 0. MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 Freescale Semiconductor Figure 11-3 shows, the output compare value in the TIM channel Timer Interface Module (TIM) ...
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... TIM Status and Control OVERFLOW PERIOD PULSE WIDTH OUTPUT COMPARE COMPARE Figure 11-3. PWM Period and Pulse Width 11.5.4 Pulse Width Modulation MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 Timer Interface Module (TIM) Register. OVERFLOW OUTPUT OUTPUT COMPARE (PWM). The pulses are Freescale Semiconductor ...
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... While the MS0B bit is set, the channel 1 pin, TCH1, is available as a general-purpose I/O pin. MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 Freescale Semiconductor When changing to a shorter pulse width, enable channel x output compare interrupts and write the new value in the output compare interrupt routine ...
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... Write 1:0 (to clear output on compare) or 1:1 (to set output on compare) to the edge/level select bits, ELSxB:ELSxA. The output action on compare must force the output to the complement of the pulse width level. (See MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 Timer Interface Module (TIM) Table 11-3.) Table 11-3.) Freescale Semiconductor ...
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... The WAIT and STOP instructions put the MCU in low power- consumption standby modes. MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 Freescale Semiconductor Registers.) TIM overflow flag (TOF) — The TOF bit is set when the TIM counter reaches the modulo value programmed in the TIM counter modulo registers ...
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... BCFE is at logic 0. After the break, doing the second step clears the status bit. Data Sheet 194 9.8.3 SIM Break Flag Control MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 Timer Interface Module (TIM) Freescale Semiconductor ...
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... MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 Freescale Semiconductor Conventions. TIM status and control register (TSC) TIM counter registers (TCNTH:TCNTL) TIM counter modulo registers (TMODH:TMODL) TIM channel status and control registers (TSC0, TSC1) TIM channel registers (TCH0H:TCH0L, TCH1H:TCH1L) ...
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... TIM overflow interrupts enabled 0 = TIM overflow interrupts disabled Data Sheet 196 Bit TOF 0 TOIE TSTOP 0 TRST Unimplemented Figure 11-4. TIM Status and Control Register (TSC) MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 Timer Interface Module (TIM Bit 0 0 PS2 PS1 PS0 Freescale Semiconductor ...
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... PS[2:0] — Prescaler Select Bits These read/write bits select one of the seven prescaler outputs as the input to the TIM counter as PS[2:0] bits. MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 Freescale Semiconductor 1 = TIM counter stopped 0 = TIM counter active 1 = Prescaler and TIM counter cleared effect Table 11-2. Prescaler Selection ...
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... Read: Write: Reset: Data Sheet 198 Bit Bit Unimplemented Figure 11-5. TIM Counter Registers High (TCNTH) Bit Bit Unimplemented Figure 11-6. TIM Counter Registers Low (TCNTL) MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 Timer Interface Module (TIM Bit Bit Bit Bit Freescale Semiconductor ...
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... Read: Write: Reset: Address: T1MODL, $0024 and T2MODL, $002F Read: Write: Reset: NOTE: Reset the TIM counter before writing to the TIM counter modulo registers. MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 Freescale Semiconductor Bit Bit Figure 11-7. TIM Counter Modulo Register High (TMODH) ...
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... Figure 11-10. TIM Channel 1 Status and Control Register (TSC1) Data Sheet 200 Bit CH0F CH0IE MS0B MS0A Bit CH1F 0 CH1IE MS1A MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 Timer Interface Module (TIM Bit 0 ELS0B ELS0A TOV0 CH0MAX Bit 0 ELS1B ELS1A TOV1 CH1MAX Freescale Semiconductor ...