MC68HC711D3VFNE2 Freescale Semiconductor, MC68HC711D3VFNE2 Datasheet - Page 70

IC MCU 8BIT 4K FLASH 44-PLCC

MC68HC711D3VFNE2

Manufacturer Part Number
MC68HC711D3VFNE2
Description
IC MCU 8BIT 4K FLASH 44-PLCC
Manufacturer
Freescale Semiconductor
Series
HC11r
Datasheets

Specifications of MC68HC711D3VFNE2

Core Processor
HC11
Core Size
8-Bit
Speed
2MHz
Connectivity
SCI, SPI
Peripherals
POR, WDT
Number Of I /o
26
Program Memory Size
4KB (4K x 8)
Program Memory Type
OTP
Ram Size
192 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
44-PLCC
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC68HC711D3VFNE2
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
7.4 Wake-up Feature
7.4.1 Idle-Line Wakeup
7.4.2 Address-Mark Wakeup
7-4
The wake-up feature reduces SCI service overhead in multiple receiver systems. Soft-
ware for each receiver evaluates the first character of each message. The receiver is
placed in wakeup mode by writing a one to the RWU bit in the SCCR2 register. While
RWU is one, all of the receiver-related status flags (RDRF, IDLE, OR, NF, and FE) are
inhibited (cannot become set). Although RWU can be cleared by a software write to
SCCR2, to do so would be unusual. Normally RWU is set by software and is cleared
automatically with hardware. Whenever a new message begins, logic alerts the sleep-
ing receivers to wake up and evaluate the initial character of the new message.
Two methods of wake-up are available: idle line wake-up and address mark wake-up.
During idle line wake-up, a sleeping receiver awakens as soon as the RxD line be-
comes idle. In the address mark wake-up, logic one in the most significant bit (MSB)
of a character wakes up all sleeping receivers.
To use the receiver wake-up method, establish a software addressing scheme to allow
the transmitting devices to direct a message to individual receivers or to groups of re-
ceivers. This addressing scheme can take any form as long as all transmitting and re-
ceiving devices are programmed to understand the same scheme. Because the
addressing information is usually the first frame(s) in a message, receivers that are not
part of the current task do not become burdened with the entire set of addressing
frames. All receivers are awake (RWU = 0) when each message begins. As soon as
a receiver determines that the message is not intended for it, software sets the RWU
bit (RWU = 1), which inhibits further flag setting until the RxD line goes idle at the end
of the message. As soon as an idle line is detected by receiver logic, hardware auto-
matically clears the RWU bit so that the first frame of the next message can be re-
ceived. This type of receiver wakeup requires a minimum of one idle-line frame time
between messages, and no idle time between frames in a message.
The serial characters in this type of wakeup consist of seven (eight if M = 1) information
bits and an MSB, which indicates an address character (when set to one — mark). The
first character of each message is an addressing character (MSB = 1). All receivers in
the system evaluate this character to determine if the remainder of the message is di-
rected toward this particular receiver. As soon as a receiver determines that a mes-
sage is not intended for it, the receiver activates the RWU function by using a software
write to set the RWU bit. Because setting RWU inhibits receiver-related flags, there is
no further software overhead for the rest of this message. When the next message be-
gins, its first character has its MSB set, which automatically clears the RWU bit and
enables normal character reception. The first character whose MSB is set is also the
first character to be received after wakeup because RWU gets cleared before the stop
bit for that frame is serially received. This type of wakeup allows messages to include
gaps of idle time, unlike the idle-line method, but there is a loss of efficiency because
of the extra bit time for each character (address bit) required for all characters.
Freescale Semiconductor, Inc.
For More Information On This Product,
SERIAL COMMUNICATIONS INTERFACE
Go to: www.freescale.com
TECHNICAL DATA

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