HD64F38024DV Renesas Electronics America, HD64F38024DV Datasheet

IC H8/SLP MCU FLASH 80QFP

HD64F38024DV

Manufacturer Part Number
HD64F38024DV
Description
IC H8/SLP MCU FLASH 80QFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300L SLPr
Datasheets

Specifications of HD64F38024DV

Core Processor
H8/300L
Core Size
8-Bit
Speed
10MHz
Connectivity
SCI
Peripherals
LCD, PWM, WDT
Number Of I /o
51
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
80-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD64F38024DV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
To our customers,
Corporation, and Renesas Electronics Corporation took over all the business of both
companies. Therefore, although the old company name remains in this document, it is a valid
Renesas Electronics document. We appreciate your understanding.
Issued by: Renesas Electronics Corporation (http://www.renesas.com)
Send any inquiries to http://www.renesas.com/inquiry.
On April 1
st
, 2010, NEC Electronics Corporation merged with Renesas Technology
Renesas Electronics website:
Old Company Name in Catalogs and Other Documents
http://www.renesas.com
April 1
Renesas Electronics Corporation
st
, 2010

Related parts for HD64F38024DV

HD64F38024DV Summary of contents

Page 1

To our customers, Old Company Name in Catalogs and Other Documents st On April 1 , 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the ...

Page 2

All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm ...

Page 3

The revision list can be viewed directly by clicking the title page. The revision list summarizes the locations of revisions and additions. Details should always be checked by referring to the relevant text. H8/38024, H8/38024S, H8/38024R, H8/38124 Group Hardware Manual ...

Page 4

This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in ...

Page 5

General Precautions in the Handling of MPU/MCU Products The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes on the products covered by this manual, refer to the relevant sections of the manual. If ...

Page 6

Configuration of This Manual This manual comprises the following items: 1. General Precautions in the Handling of MPU/MCU Products 2. Configuration of This Manual 3. Preface 4. Contents 5. Overview 6. Description of Functional Modules • CPU and System-Control Modules ...

Page 7

The H8/38024 Group is a single-chip microcomputer built around the high-speed H8/300L CPU and equipped with peripheral system functions on-chip. The H8/38024 Group incorporates peripheral functions including ROM, RAM, timer, serial communications interface (SCI), 10-bit PWM, A/D converter, LCD controller/driver, ...

Page 8

Specifications Item Memory ROM 32 Kbytes RAM 1 Kbyte Operating 4 MHz voltage and 2 MHz operating 1.8 to 5.5 V frequency 2.7 to 3.6 V 1.8 to 3.6 V I/O ports ...

Page 9

Target Readers: This manual is designed for use by people who design application systems using the H8/38024 Group, H8/38024S Group, H8/38024R Group, and H8/38124 Group. To use this manual, basic knowledge of electric circuits, logic circuits and microcomputers is required. ...

Page 10

Application Note Name of Document H8S, H8/300 Series C/C++ Compiler Package Application Note Notes: The following limitations apply to H8/38024, H8/38024R, and H8/38124 programming and debugging when the on-chip emulator is used. 1. Pin 95 is not available because ...

Page 11

Section 1 Overview................................................................................................1 1.1 Overview................................................................................................................................ 1 1.2 Internal Block Diagram.......................................................................................................... 7 1.3 Pin Arrangement and Functions............................................................................................. 9 1.3.1 Pin Arrangement ....................................................................................................... 9 1.3.2 Pin Functions .......................................................................................................... 19 Section 2 CPU......................................................................................................25 2.1 Overview.............................................................................................................................. 25 2.1.1 Features................................................................................................................... 25 2.1.2 Address Space......................................................................................................... 26 ...

Page 12

Program Halt State.................................................................................................. 59 2.7.4 Exception-Handling State ....................................................................................... 59 2.8 Memory Map ....................................................................................................................... 60 2.8.1 Memory Map .......................................................................................................... 60 2.9 Application Notes ................................................................................................................ 66 2.9.1 Notes on Data Access ............................................................................................. 66 2.9.2 Notes on Bit Manipulation...................................................................................... 68 2.9.3 Notes ...

Page 13

Notes on H8/38124 Group ................................................................................................. 119 Section 5 Power-Down Modes ..........................................................................121 5.1 Overview............................................................................................................................ 121 5.1.1 System Control Registers...................................................................................... 124 5.2 Sleep Mode ........................................................................................................................ 128 5.2.1 Transition to Sleep Mode...................................................................................... 128 5.2.2 Clearing Sleep Mode............................................................................................. 129 5.2.3 Clock Frequency in ...

Page 14

Section 6 ROM ..................................................................................................145 6.1 Overview............................................................................................................................ 145 6.1.1 Block Diagram ...................................................................................................... 145 6.2 H8/38024 PROM Mode ..................................................................................................... 146 6.2.1 Setting to PROM Mode ........................................................................................ 146 6.2.2 Socket Adapter Pin Arrangement and Memory Map............................................ 146 6.3 H8/38024 Programming..................................................................................................... 149 6.3.1 Writing ...

Page 15

Status Polling ........................................................................................................ 189 6.10.8 Programmer Mode Transition Time...................................................................... 190 6.10.9 Notes on Memory Programming........................................................................... 190 6.11 Power-Down States for Flash Memory.............................................................................. 191 Section 7 RAM ..................................................................................................193 7.1 Overview............................................................................................................................ 193 7.1.1 Block Diagram ...................................................................................................... 193 Section 8 I/O Ports ...

Page 16

Port 7.................................................................................................................................. 224 8.7.1 Overview............................................................................................................... 224 8.7.2 Register Configuration and Description................................................................ 224 8.7.3 Pin Functions ........................................................................................................ 226 8.7.4 Pin States............................................................................................................... 226 8.8 Port 8.................................................................................................................................. 227 8.8.1 Overview............................................................................................................... 227 8.8.2 Register Configuration and Description................................................................ 227 8.8.3 Pin Functions ........................................................................................................ 229 ...

Page 17

Overview............................................................................................................... 255 9.3.2 Register Descriptions ............................................................................................ 257 9.3.3 Timer Operation.................................................................................................... 260 9.3.4 Timer C Operation States...................................................................................... 262 9.4 Timer F .............................................................................................................................. 263 9.4.1 Overview............................................................................................................... 263 9.4.2 Register Descriptions ............................................................................................ 266 9.4.3 CPU Interface ....................................................................................................... 273 9.4.4 Operation .............................................................................................................. 276 ...

Page 18

Serial Mode Register (SMR)................................................................................. 339 10.2.6 Serial Control Register 3 (SCR3).......................................................................... 342 10.2.7 Serial Status Register (SSR) ................................................................................. 346 10.2.8 Bit Rate Register (BRR) ....................................................................................... 350 10.2.9 Clock stop register 1 (CKSTPR1)......................................................................... 356 10.2.10 Serial Port Control Register (SPCR)..................................................................... ...

Page 19

Start of A/D Conversion by External Trigger Input.............................................. 402 12.3.3 A/D Converter Operation Modes .......................................................................... 403 12.4 Interrupts ............................................................................................................................ 403 12.5 Typical Use ........................................................................................................................ 403 12.6 A/D Conversion Accuracy Definitions .............................................................................. 407 12.7 Application Notes .............................................................................................................. 409 12.7.1 Permissible ...

Page 20

Power-On Reset Circuit ........................................................................................ 439 14.3.2 Low-Voltage Detection Circuit............................................................................. 440 Section 15 Power Supply Circuit (H8/38124 Group Only)...............................447 15.1 When Using Internal Power Supply Step-Down Circuit.................................................... 447 15.2 When Not Using Internal Power Supply Step-Down Circuit............................................. 448 Section 16 ...

Page 21

AC Characteristics ................................................................................................ 515 16.8.4 A/D Converter Characteristics .............................................................................. 517 16.8.5 LCD Characteristics.............................................................................................. 518 16.8.6 Flash Memory Characteristics .............................................................................. 519 16.8.7 Power Supply Voltage Detection Circuit Characteristics ..................................... 521 16.8.8 Power-On Reset Circuit Characteristics................................................................ 524 16.8.9 Watchdog Timer Characteristics........................................................................... ...

Page 22

Appendix G Specifications of Chip Form .........................................................643 Appendix H Form of Bonding Pads ..................................................................645 Appendix I Specifications of Chip Tray............................................................646 Main Revisions for This Edition .........................................................................649 Rev. 8.00 Mar. 09, 2010 Page REJ09B0042-0800 ...

Page 23

Overview The H8/300L Series is a series of single-chip microcomputers (MCU: microcomputer unit), built around the high-speed H8/300L CPU and equipped with peripheral system functions on-chip. Within the H8/300L Series, the H8/38024 Group, H8/38024S Group, and H8/38124 Group comprise ...

Page 24

Section 1 Overview Table 1.1 Features Item Specification CPU High-speed H8/300L CPU • General-register architecture General registers: Sixteen 8-bit registers (can be used as eight 16-bit registers) • Operating speed ⎯ Max. operating speed: 8 MHz (5 MHz for HD64F38024 ...

Page 25

Item Specification Clock pulse Two on-chip clock pulse generators generators • System clock pulse generator: 1 MHz: H8/38024 Group 1 MHz: HD64F38024, HD64F38024R, and H8/38024S Group 2 MHz: H8/38124 Group • Subclock pulse generator: ...

Page 26

Section 1 Overview Item Specification Timers Six on-chip timers • Timer A: 8-bit timer Count-up timer with selection of eight internal clock signals divided from the system clock (φ) * and four clock signals divided from the watch clock (φ ...

Page 27

Item Specification • Serial SCI3: 8-bit synchronous/asynchronous serial interface communication interface 10-bit PWM Pulse-division PWM output for reduced ripple • Can be used as a 10-bit D/A converter by connecting to an external low- pass filter. A/D converter Successive approximations ...

Page 28

Section 1 Overview Item Specification Product lineup Mask ROM Version HD64338024 HD64338023 HD64338022 HD64338021 HD64338020 HD64338024S HD64338023S HD64338022S HD64338021S HD64338020S HD64338124 HD64338123 HD64338122 HD64338121 HD64338120 Refer to appendix E for information on product model numbers. Note: * See section 4, ...

Page 29

Internal Block Diagram Figure 1.1(1) shows a block diagram of the H8/38024 Group and H8/38024S Group. Figure 1.1(2) shows a block diagram of the H8/38124 Group OSC 1 OSC 2 P1 /TMIG 3 P1 /IRQ ...

Page 30

Section 1 Overview OSC 1 OSC 2 P1 /TMIG 3 P1 /IRQ /ADTRG (8 Kbytes to 32 Kbytes /IRQ /TMIF 7 3 low-voltage detect circuits P3 / /TMOFL 1 P3 /TMOFH ...

Page 31

Pin Arrangement and Functions 1.3.1 Pin Arrangement The H8/38024 Group, H8/38024R Group, H8/38024S Group, and H8/38124 Group pin arrangements are shown in figures 1.2, 1.3, and 1.4. The bonding pad location diagram of the HCD64338024, HCD64338023, HCD64338022, HCD64338021, and ...

Page 32

Section 1 Overview P3 / /TMOFL 1 P3 /TMOFH /AEVH 6 P3 /AEVL 7 P4 /SCK /RXD /TXD /IRQ 3 0 ...

Page 33

P3 /TMOFH /AEVH /AEVL /SCK /RXD /TXD /IRQ 74 3 ...

Page 34

Section 1 Overview Note: Pins are shown in transparent view. Figure 1.4 Pin Arrangement (TLP-85V, H8/38024R Group, H8/38024S Group) Rev. ...

Page 35

Figure 1.5 Bonding Pad Location Diagram of HCD64338024, HCD64338023, HCD64338022, HCD64338021, and ...

Page 36

Section 1 Overview Table 1.2 Bonding Pad Coordinates of HCD64338024, HCD64338023, HCD64338022, HCD64338021, and HCD64338020 Pad No. Pad Name P13/TMIG 3 P14/IRQ4/ADTRG 4 P16 5 P17/IRQ3/TMIF ...

Page 37

Figure 1.6 Bonding Pad Location Diagram of HCD64F38024, HCD64F38024R (Top View ...

Page 38

Section 1 Overview Table 1.3 Bonding Pad Coordinates of HCD64F38024, HCD64F38024R Pad No. Pad Name 1 PB7/AN7 P13/TMIG 4 P14/IRQ4/ADTRG 5 P16 6 P17/IRQ3/TMIF OSC2 ...

Page 39

Figure 1.7 Bonding Pad Location Diagram of HCD64338024S, ...

Page 40

Section 1 Overview Table 1.4 Bonding Pad Coordinates of HCD64338024S, HCD64338023S, HCD64338022S, HCD64338021S, and HCD64338020S Pad No. Pad Name P13/TMIG 3 P14/IRQ4/ADTRG 4 P16 5 P17/IRQ3/TMIF ...

Page 41

Pin Functions Table 1.5 outlines the pin functions of the H8/38024 Group. Table 1.5 Pin Functions FP-80A Type Symbol TFP-80C FP-80B TLP-85V Power source pins ...

Page 42

Section 1 Overview FP-80A Type Symbol TFP-80C FP-80B TLP-85V Clock OSC 10 1 pins OSC RES System 12 control TEST 11 IRQ Interrupt 72 0 IRQ pins 76 1 IRQ 5 3 ...

Page 43

FP-80A Type Symbol TFP-80C FP-80B TLP-85V WKP Interrupt WKP pins 0 Timer AEVL 68 pins AEVH 67 TMIC TMIF 5 TMOFL 62 TMOFH 63 TMIG 2 Pin No. Pad Pad No. * ...

Page 44

Section 1 Overview FP-80A Type Symbol TFP-80C FP-80B TLP-85V 10-bit PWM1 54 PWM pin PWM2 55 I/O ports ...

Page 45

FP-80A Type Symbol TFP-80C FP-80B TLP-85V I/O ports ...

Page 46

Section 1 Overview FP-80A Type Symbol TFP-80C FP-80B TLP-85V ADTRG A/D 3 converter LCD COM controller/ COM 1 driver SEG SEG — Low ref voltage ...

Page 47

Overview The H8/300L CPU has sixteen 8-bit general registers, which can also be paired as eight 16-bit registers. Its concise instruction set is designed for high-speed operation. 2.1.1 Features Features of the H8/300L CPU are listed below. • General-register ...

Page 48

Section 2 CPU 2.1.2 Address Space The H8/300L CPU supports an address space Kbytes for storing program code and data. See section 2.8, Memory Map, for details of the memory map. 2.1.3 Register Configuration Figure 2.1 ...

Page 49

Register Descriptions 2.2.1 General Registers All the general registers can be used as both data registers and address registers. When used as data registers, they can be accessed as 16-bit registers (R0 to R7), or the high bytes (R0H ...

Page 50

Section 2 CPU Condition Code Register (CCR) This 8-bit register contains internal status information, including the interrupt mask bit (I) and half-carry (H), negative (N), zero (Z), overflow (V), and carry (C) flags. These bits can be read and written ...

Page 51

Initial Register Values When the CPU is reset, the program counter (PC) is initialized to the value stored at address H'0000 in the vector table, and the I bit in the CCR is set to 1. The other CCR ...

Page 52

Section 2 CPU 2.3.1 Data Formats in General Registers Data of all the sizes above can be stored in general registers as shown in figure 2.3. Data Type Register No. 7 1-bit data RnH 7 1-bit data RnL 7 Byte ...

Page 53

Memory Data Formats Figure 2.4 indicates the data formats in memory. The H8/300L CPU can access word data stored in memory (MOV.W instruction), but the word data must always begin at an even address. If word data starting at ...

Page 54

Section 2 CPU 2.4 Addressing Modes 2.4.1 Addressing Modes The H8/300L CPU supports the eight addressing modes listed in table 2.1. Each instruction uses a subset of these addressing modes. Table 2.1 Addressing Modes No. Address Modes 1 Register direct ...

Page 55

Register Indirect with Post-Increment or Pre-Decrement—@Rn+ or @–Rn: • Register indirect with post-increment—@Rn+ The @Rn+ mode is used with MOV instructions that load registers from memory. The register field of the instruction specifies a 16-bit general register containing the address ...

Page 56

Section 2 CPU The upper 8 bits of the absolute address are assumed (H'00), so the address range is from H'0000 to H'00FF (0 to 255). Note that with the H8/300L Series, the lower end of the ...

Page 57

Table 2.2 Effective Address Calculation Section 2 CPU Rev. 8.00 Mar. 09, 2010 Page 35 of 658 REJ09B0042-0800 ...

Page 58

Section 2 CPU Rev. 8.00 Mar. 09, 2010 Page 36 of 658 REJ09B0042-0800 ...

Page 59

Section 2 CPU Rev. 8.00 Mar. 09, 2010 Page 37 of 658 REJ09B0042-0800 ...

Page 60

Section 2 CPU 2.5 Instruction Set The H8/300L Series can use a total of 55 instructions, which are grouped by function in table 2.3. Table 2.3 Instruction Set Function Instructions MOV, PUSH * Data transfer Arithmetic operations ADD, SUB, ADDX, ...

Page 61

Notation Rd General register (destination) Rs General register (source) Rn General register (EAd), <EAd> Destination operand (EAs), <EAs> Source operand CCR Condition code register N N (negative) flag of CCR Z Z (zero) flag of CCR V V (overflow) flag ...

Page 62

Section 2 CPU 2.5.1 Data Transfer Instructions Table 2.4 describes the data transfer instructions. Figure 2.5 shows their object code formats. Table 2.4 Data Transfer Instructions Size * Instruction MOV B/W POP W PUSH W Note: * Size: Operand size ...

Page 63

Operation field rm, rn: Register field disp: Displacement abs: Absolute address IMM: Immediate data Figure 2.5 Data Transfer ...

Page 64

Section 2 CPU 2.5.2 Arithmetic Operations Table 2.5 describes the arithmetic instructions. Table 2.5 Arithmetic Instructions Size * Instruction ADD B/W SUB ADDX B SUBX INC B DEC ADDS W SUBS DAA B DAS MULXU B DIVXU B CMP B/W ...

Page 65

Logic Operations Table 2.6 describes the four instructions that perform logic operations. Table 2.6 Logic Operation Instructions Size * Instruction AND XOR B NOT B Note: * Size: Operand size B: Byte Function Rd ∧ Rs ...

Page 66

Section 2 CPU 2.5.4 Shift Operations Table 2.7 describes the eight shift instructions. Table 2.7 Shift Instructions Size * Instruction SHAL B SHAR SHLL B SHLR ROTL B ROTR ROTXL B ROTXR Note: * Size: Operand size B: Byte Rev. ...

Page 67

Figure 2.6 shows the instruction code format of arithmetic, logic, and shift instructions [Legend] op: Operation field rm, rn: Register field IMM: Immediate data ...

Page 68

Section 2 CPU 2.5.5 Bit Manipulations Table 2.8 describes the bit-manipulation instructions. Figure 2.7 shows their object code formats. Table 2.8 Bit-Manipulation Instructions Size * Instruction BSET B BCLR B BNOT B BTST B BAND B BIAND B BOR B ...

Page 69

Size * Instruction BXOR B BIXOR B BLD B BILD B BST B BIST B Note: * Size: Operand size B: Byte Certain precautions are required in bit manipulation. See section 2.9.2, Notes on Bit Manipulation, for details. Figure 2.7 ...

Page 70

Section 2 CPU [Legend] op: Operation field rm, rn: Register field abs: Absolute address IMM: Immediate ...

Page 71

Operation field rm, rn: Register field abs: Absolute address IMM: Immediate data Figure 2.7 Bit Manipulation Instruction Codes (cont IMM ...

Page 72

Section 2 CPU 2.5.6 Branching Instructions Table 2.9 describes the branching instructions. Figure 2.8 shows their object code formats. Table 2.9 Branching Instructions Instruction Size Bcc — JMP — BSR — JSR — RTS — Rev. 8.00 Mar. 09, 2010 ...

Page 73

Operation field cc: Condition field rm: Register field disp: Displacement abs: Absolute address Figure 2.8 Branching Instruction Codes 8 7 disp 8 ...

Page 74

Section 2 CPU 2.5.7 System Control Instructions Table 2.10 describes the system control instructions. Figure 2.9 shows their object code formats. Table 2.10 System Control Instructions Size * Instruction RTE — SLEEP — LDC B STC B ANDC B ORC ...

Page 75

Operation field rn: Register field IMM: Immediate data Figure 2.9 System Control Instruction Codes 2.5.8 Block Data Transfer Instruction Table 2.11 describes the block data transfer instruction. Figure 2.10 shows its object code ...

Page 76

Section 2 CPU 15 [Legend] op: Operation field Figure 2.10 Block Data Transfer Instruction Code Rev. 8.00 Mar. 09, 2010 Page 54 of 658 REJ09B0042-0800 ...

Page 77

Basic Operational Timing CPU operation is synchronized by a system clock (φ subclock (φ clock signals see section 4, Clock Pulse Generators. The period from a rising edge of φ or φ the next rising edge is ...

Page 78

Section 2 CPU 2.6.2 Access to On-Chip Peripheral Modules On-chip peripheral modules are accessed in two states or three states. The data bus width is 8 bits, so access is by byte size only. This means that for accessing word ...

Page 79

Three-state access to on-chip peripheral modules T φ or φ SUB Internal address bus Internal read signal Internal data bus (read access) Internal write signal Internal data bus (write access) Figure 2.13 On-Chip Peripheral Module Access Cycle (3-State Access) 2.7 ...

Page 80

Section 2 CPU CPU state The CPU is initialized Program halt state A state in which some or all of the chip functions are stopped to conserve power A transient state in which the CPU changes the processing flow due ...

Page 81

Reset state Reset occurs Program halt state 2.7.2 Program Execution State In the program execution state the CPU executes program instructions in sequence. There are three modes in this state, two active modes (high speed and medium speed) and one ...

Page 82

Section 2 CPU 2.8 Memory Map 2.8.1 Memory Map The memory map of the H8/38024, H8/38024S, and H8/38124 are shown in figure 2.16(1), that of the H8/38023, H8/38023S, and H8/38123 in figure 2.16(2), that of the H8/38022, H8/38022S, and H8/38122 ...

Page 83

HD64F38024, HD64F38024R, HD64F38124 (flash memory version) H'0000 Interrupt vector area H'0029 H'002A On-chip ROM H'7000 Firmware for on-chip emulator * 1 H'7FFF Not used H'F020 Internal I/O register H'F02B Not used H'F740 LCD RAM (16 bytes) H'F74F Not used H'F780 ...

Page 84

Section 2 CPU H'0000 H'0029 H'002A H'5FFF H'F740 H'F74F H'FB80 H'FF7F H'FF80 H'FFFF Figure 2.16(2) H8/38023, H8/38023S, and H8/38123 Memory Map Rev. 8.00 Mar. 09, 2010 Page 62 of 658 REJ09B0042-0800 Interrupt vector area On-chip ROM Not used LCD RAM ...

Page 85

Flash memory version H'0000 Interrupt vector area H'0029 H'002A On-chip ROM H'3FFF Not used H'7000 Firmware for on-chip emulator H'7FFF Not used H'F020 Internal I/O register H'F02B Not used H'F740 LCD RAM (16 bytes) H'F74F Not used H'F780 (Workarea for ...

Page 86

Section 2 CPU H'0000 H'0029 H'002A H'2FFF H'F740 H'F74F H'FD80 H'FF7F H'FF80 H'FFFF Figure 2.16(4) H8/38021, H8/38021S, and H8/38121 Memory Map Rev. 8.00 Mar. 09, 2010 Page 64 of 658 REJ09B0042-0800 Interrupt vector area On-chip ROM Not used LCD RAM ...

Page 87

H'0000 Interrupt vector area H'0029 H'002A On-chip ROM H'1FFF Not used H'F740 LCD RAM (16 bytes) H'F74F Not used H'FD80 On-chip RAM H'FF7F H'FF80 Internal I/O registers (128 bytes) H'FFFF Figure 2.16(5) H8/38020, H8/38020S, and H8/38120 Memory Map Section 2 ...

Page 88

Section 2 CPU 2.9 Application Notes 2.9.1 Notes on Data Access 1. Access to Empty Areas: The address space of the H8/300L CPU includes empty areas in addition to the RAM, registers, and ROM areas available to the user. If ...

Page 89

H'0000 Interrupt vector area (42 bytes) H'0029 H'002A On-chip ROM * 1 H'7FFF Not used H'F020 Internal I/O registers H'F02B Not used H'F740 LCD RAM (16 bytes) H'F74F Not used H'F780 (1-Kbyte work area for flash memory programming) H'FB7F Internal ...

Page 90

Section 2 CPU 2.9.2 Notes on Bit Manipulation The BSET, BCLR, BNOT, BST, and BIST instructions read one byte of data, modify the data, then write the data byte again. Special care is required when using these instructions in cases ...

Page 91

Example 2: BSET instruction executed designating port 3 P3 and P3 are designated as input pins, with a low-level signal input signal The remaining pins example, the BSET instruction is used ...

Page 92

Section 2 CPU To avoid this problem, store a copy of the PDR3 data in a work area in memory. Perform the bit manipulation on the data in the work area, then write this data to PDR3. [A: Prior to ...

Page 93

Bit manipulation in a register containing a write-only bit Example 3: BCLR instruction executed designating port 3 control register PCR3 As in the examples above, P3 high-level signal The remaining pins signals. In this ...

Page 94

Section 2 CPU To avoid this problem, store a copy of the PCR3 data in a work area in memory. Perform the bit manipulation on the data in the work area, then write this data to PCR3. [A: Prior to ...

Page 95

Table 2.12 Registers with Shared Addresses Register Name Timer counter C/Timer load register C Port data register 1 * Port data register 3 * Port data register 4 * Port data register 5 * Port data register 6 * Port ...

Page 96

Section 2 CPU 2.9.3 Notes on Use of the EEPMOV Instruction • The EEPMOV instruction is a block data transfer instruction. It moves the number of bytes specified by R4L from the address specified the address specified ...

Page 97

Section 3 Exception Handling 3.1 Overview Exception handling is performed in the H8/38024 Group, H8/38024S Group, H8/38024F-ZTAT Group, and H8/38124 Group when a reset or interrupt occurs. Table 3.1 shows the priorities of these two types of exception handling. Table ...

Page 98

Section 3 Exception Handling When system power is turned on or off, the RES pin should be held low. Figure 3.1 shows the reset sequence starting from RES input. See section 14.3.1, Power-On Reset Circuit, for information on the reset ...

Page 99

Interrupts 3.3.1 Overview The interrupt sources include 13 external interrupts (WKP IRQAEC) and 9 internal interrupts from on-chip peripheral modules. Table 3.2 shows the interrupt sources, their priorities, and their vector addresses. When more than one interrupt is requested, ...

Page 100

Section 3 Exception Handling Table 3.2 Interrupt Sources and Their Priorities Interrupt Source Interrupt RES Reset Watchdog timer IRQ IRQ 0 0 Low-voltage detect interrupt * LVDI * IRQ IRQ 1 1 IRQAEC IRQAEC IRQ IRQ 3 3 IRQ IRQ ...

Page 101

Interrupt Control Registers Table 3.3 lists the registers that control interrupts. Table 3.3 Interrupt Control Registers Name IRQ edge select register Interrupt enable register 1 Interrupt enable register 2 Interrupt request register 1 Interrupt request register 2 Wakeup interrupt ...

Page 102

Section 3 Exception Handling Bit 4—IRQ Edge Select (IEG4) 4 Bit 4 selects the input sensing of the IRQ Bit 4 IEG4 Description Falling edge of IRQ 0 Rising edge of IRQ 1 Bit 3—IRQ Edge Select (IEG3) 3 Bit ...

Page 103

Interrupt Enable Register 1 (IENR1) Bit 7 IENTA Initial value 0 Read/Write R/W IENR1 is an 8-bit read/write register that enables or disables interrupt requests. Bit 7—Timer A Interrupt Enable (IENTA) Bit 7 enables or disables timer A overflow interrupt ...

Page 104

Section 3 Exception Handling Bit 2—IRQAEC Interrupt Enable (IENEC2) Bit 2 enables or disables IRQAEC interrupt requests. Bit 2 IENEC2 Description 0 Disables IRQAEC interrupt requests 1 Enables IRQAEC interrupt requests Bits 1 and 0—IRQ and IRQ 1 Bits 1 ...

Page 105

Bit 6—A/D Converter Interrupt Enable (IENAD) Bit 6 enables or disables A/D converter interrupt requests. Bit 6 IENAD Description 0 Disables A/D converter interrupt requests 1 Enables A/D converter interrupt requests Bit 5—Reserved Bit 5 is reserved bit: it can ...

Page 106

Section 3 Exception Handling Bit 1—Timer C Interrupt Enable (IENTC) Bit 1 enables or disables timer C overflow and underflow interrupt requests. Bit 1 IENTC Description 0 Disables timer C interrupt requests 1 Enables timer C interrupt requests Bit 0—Asynchronous ...

Page 107

Bit 7—Timer A Interrupt Request Flag (IRRTA) Bit 7 IRRTA Description 0 Clearing condition: When IRRTA = cleared by writing 0 1 Setting condition: When the timer A counter value overflows Bit 6—Reserved Bit 6 is reserved; ...

Page 108

Section 3 Exception Handling Bits 1 and 0—IRQ and IRQ 1 Bit n IRRIn Description 0 Clearing condition: When IRRIn = cleared by writing 0 1 Setting condition: When pin IRQn is designated for interrupt input and ...

Page 109

Bit 6—A/D Converter Interrupt Request Flag (IRRAD) Bit 6 IRRAD Description 0 Clearing condition: When IRRAD = cleared by writing 0 1 Setting condition: When A/D conversion is completed and ADSF is cleared ADSR ...

Page 110

Section 3 Exception Handling Bit 2—Timer FL Interrupt Request Flag (IRRTFL) Bit 2 IRRTFL Description 0 Clearing condition: When IRRTFL = cleared by writing 0 1 Setting condition: When TCFL and OCRFL match in 8-bit timer mode ...

Page 111

Wakeup Interrupt Request Register (IWPR) Bit 7 IWPF7 IWPF6 Initial value 0 R/(W) * R/(W) * Read/Write Note: * Only a write of 0 for flag clearing is possible IWPR is an 8-bit read/write register containing wakeup interrupt request flags. ...

Page 112

Section 3 Exception Handling Wakeup Edge Select Register (WEGR) Bit 7 WKEGS7 WKEGS6 Initial value 0 Read/Write R/W WEGR is an 8-bit read/write register that specifies rising or falling edge sensing for pins WKPn. WEGR is initialized to H'00 by ...

Page 113

Interrupts IRQ , IRQ , IRQ 4 3 Interrupts IRQ4, IRQ3, IRQ1, and IRQ0 are requested by input signals to pins IRQ and IRQ . These interrupts are detected by either rising edge sensing or falling edge sensing, 0 depending ...

Page 114

Section 3 Exception Handling 3.3.5 Interrupt Operations Interrupts are controlled by an interrupt controller. Figure 3.2 shows a block diagram of the interrupt controller. Figure 3.3 shows the flow up to interrupt acceptance. External or internal interrupts External interrupts or ...

Page 115

If the interrupt request is accepted, after processing of the current instruction is completed, both PC and CCR are pushed onto the stack. The state of the stack at this time is shown in figure 3.4. The PC value ...

Page 116

Section 3 Exception Handling Program execution state IRRI0 = 1 Yes IEN0 = 1 Yes Yes PC contents saved CCR contents saved I ← 1 Branch to interrupt handling routine [Legend] PC: Program counter CCR: Condition code ...

Page 117

SP − − − − (R7) Stack area Prior to start of interrupt exception handling [Legend Upper 8 bits of program counter (PC Lower 8 bits of ...

Page 118

Section 3 Exception Handling Rev. 8.00 Mar. 09, 2010 Page 96 of 658 REJ09B0042-0800 Figure 3.5 Interrupt Sequence ...

Page 119

Interrupt Response Time Table 3.4 shows the number of wait states after an interrupt request flag is set until the first instruction of the interrupt handler is executed. Table 3.4 Interrupt Wait States Item Waiting time for completion of ...

Page 120

Section 3 Exception Handling 3.4 Application Notes 3.4.1 Notes on Stack Area Use When word data is accessed in the LSI, the least significant bit of the address is regarded as 0. Access to the stack always takes place in ...

Page 121

Notes on Rewriting Port Mode Registers When a port mode register is rewritten to switch the functions of external interrupt pins and when the value of ECPWME in AEGSR is rewritten to switch between selection/non-selection of IRQAEC, the following ...

Page 122

Section 3 Exception Handling Interrupt Request Flags Set to 1 Conditions When PMR5 bit WKP7 is changed from while pin WKP IWPR IWPF7 WKEGS7 = 0. When PMR5 bit WKP7 is changed from while ...

Page 123

AEGSR) access without executing an intervening instruction, the flag will not be cleared. An alternative method is to avoid the setting of interrupt request flags when pin functions are switched by keeping ...

Page 124

Section 3 Exception Handling • Example of a malfunction When flags are cleared with multiple instructions, other flags might be cleared during execution of the instructions, even though they are currently set, and this will cause a malfunction. Here is ...

Page 125

Section 4 Clock Pulse Generators 4.1 Overview Clock oscillator circuitry (CPG: clock pulse generator) is provided on-chip, including both a system clock pulse generator and a subclock pulse generator. The system clock pulse generator consists of a system clock oscillator ...

Page 126

Section 4 Clock Pulse Generators Internal reset signal (other than watchdog timer or low-voltage detect circuit reset IRQAEC Latch System OSC 1 clock OSC oscillator 2 On-chip R OSC oscillator X 1 Subclock oscillator ( ...

Page 127

Register Descriptions Table 4.1 lists the registers that control the clock pulse generators. The registers listed in table 4.1 are only implemented in the H8/38124 Group. Table 4.1 Clock Pulse Generator Control Registers Name Clock pulse generator control register ...

Page 128

Section 4 Clock Pulse Generators Bit 2—IRQAEC Flag (IRQAECF) This bit indicates the IRQAEC pin input level set during resets. Bit 2 IRQAECF Description 0 IRQAEC pin set to GND during resets 1 IRQAEC pin set to V Bit 1—OSC ...

Page 129

OSC OSC 2 Figure 4.3(1) Typical Connection to Crystal Oscillator C 1 OSC OSC 2 Figure 4.3(2) Typical Connection to Crystal Oscillator Figure 4.3 shows the equivalent circuit of a crystal oscillator. ...

Page 130

Section 4 Clock Pulse Generators Table 4.2 Crystal Oscillator Parameters Frequency (MHz) RS max (Ω) C max (pF) 0 Connecting a Ceramic Oscillator Figure 4.5(1) shows a typical method of connecting a ceramic oscillator to the H8/38024 or H8/38024R Group, ...

Page 131

Notes on Board Design When generating clock pulses by connecting a crystal or ceramic oscillator, pay careful attention to the following points. Avoid running signal lines close to the oscillator circuit, since the oscillator may be adversely affected by induction ...

Page 132

Section 4 Clock Pulse Generators External Clock Input Method Connect an external clock signal to pin OSC typical connection. OSC 1 OSC 2 Figure 4.7 External Clock Input (Example) Frequency Duty cycle On-Chip Oscillator Selection Method (H8/38124 Group Only) The ...

Page 133

Subclock Generator Connecting a 32.768 kHz/38.4 kHz Crystal Oscillator Clock pulses can be supplied to the subclock divider by connecting a 32.768 kHz/38.4 kHz crystal oscillator, as shown in figure 4.8. Follow the same precautions as noted under 3. ...

Page 134

Section 4 Clock Pulse Generators Pin Connection when Not Using Subclock When the subclock is not used, connect pin X 4.10. Figure 4.10 Pin Connection when not Using Subclock External Clock Input Connect the external clock to the X1 pin ...

Page 135

Frequency Duty Method for Disabling Subclock Oscillator (H8/38124 Group Only) The subclock oscillator can be disabled by programs by setting the SUBSTP bit in the OSCCR register to 1. The register setting to disable the subclock oscillator should be made ...

Page 136

Section 4 Clock Pulse Generators Prescaler W (PSW) Prescaler 5-bit counter using a 32.768 kHz/38.4 kHz signal divided by 4 (φ clock. Prescaler W is initialized to H' reset, and starts counting on exit from ...

Page 137

Note on Oscillators Oscillator characteristics are closely related to board design and should be carefully evaluated by the user in mask ROM and ZTAT versions, referring to the examples shown in this section. Oscillator circuit constants will differ depending ...

Page 138

Section 4 Clock Pulse Generators Negative resistance, addition of −R (1) Negative Resistance Measuring Circuit Modification point (3) Oscillator Circuit Modification Suggestion 2 Figure 4.13 Negative Resistance Measurement and Circuit Modification Suggestions 4.5.1 Definition ...

Page 139

Oscillation stabilization time (t The time from the point at which the system clock oscillator oscillation waveform starts to change when an interrupt is generated, until the amplitude of the oscillation waveform increases and the oscillation frequency stabilizes. 2. ...

Page 140

Section 4 Clock Pulse Generators amplitude of the oscillation waveform increases and the oscillation frequency stabilizes—that is, the oscillation stabilization time—is required. The oscillation stabilization time in the case of these state transitions is the same as the oscillation stabilization ...

Page 141

For example, if erroneous operation occurs with a wait time setting of 16 states, check the operation with a wait time setting of 1,024 * states or more. If the same kind of erroneous operation occurs after a reset as ...

Page 142

Section 4 Clock Pulse Generators Rev. 8.00 Mar. 09, 2010 Page 120 of 658 REJ09B0042-0800 ...

Page 143

Section 5 Power-Down Modes 5.1 Overview The LSI has nine modes of operation after a reset. These include eight power-down modes, in which power dissipation is significantly reduced. Table 5.1 gives a summary of the nine operating modes. Table 5.1 ...

Page 144

Section 5 Power-Down Modes Reset state Program halt state Standby mode *1 instruction Watch mode Mode Transition Conditions (1) LSON MSON SSBY * ...

Page 145

Table 5.2 Internal State in Each Operating Mode Active Mode High- Function Speed System clock oscillator Functions Functions Functions Functions Halted Subclock oscillator Functions Functions Functions Functions Functions CPU Instructions Functions Functions Halted operations RAM Registers I/O ports External IRQ ...

Page 146

Section 5 Power-Down Modes 11. On the H8/38124 Group, operates only when the on-chip oscillator is selected; otherwise stops and stands by. On the H8/38024, H8/38024S, and H8/38024R Group, stops and stands by. 5.1.1 System Control Registers The operation mode ...

Page 147

Bits 6 to 4—Standby Timer Select (STS2 to STS0) These bits designate the time the CPU and peripheral modules wait for stable clock operation after exiting from standby mode or watch mode to active mode due to ...

Page 148

Section 5 Power-Down Modes Bit 3—Low Speed on Flag (LSON) This bit chooses the system clock (φ) or subclock (φ mode is cleared. The resulting operation mode depends on the combination of other control bits and interrupt input. Bit 3 ...

Page 149

Bit 4—Noise Elimination Sampling Frequency Select (NESEL) This bit selects the frequency at which the watch clock signal (φ pulse generator is sampled, in relation to the oscillator clock (φ pulse generator. When φ MHz, clear ...

Page 150

Section 5 Power-Down Modes Bit 2 MSON Description 0 Operation in active (high-speed) mode 1 Operation in active (medium-speed) mode Bits 1 and 0—Subactive Mode Clock Select (SA1, SA0) These bits select the CPU clock rate (φ cannot be modified ...

Page 151

Clearing Sleep Mode Sleep mode is cleared by any interrupt (timer A, timer C, timer F, timer G, asynchronous event counter, IRQAEC, IRQ , IRQ 4 the RES pin. • Clearing by interrupt When an interrupt is requested, sleep ...

Page 152

Section 5 Power-Down Modes 5.3 Standby Mode 5.3.1 Transition to Standby Mode The system goes from active mode to standby mode when a SLEEP instruction is executed while the SSBY bit in SYSCR1 is set to 1, the LSON bit ...

Page 153

When a oscillator is used The table below gives settings for various operating frequencies. Set bits STS2 to STS0 for a wait time at least as long as the oscillation stabilization time. Table 5.4(1) Clock Frequency and Stabilization Time ...

Page 154

Section 5 Power-Down Modes • When the on-chip oscillator is used 8,192 states (STS2 = STS1 = STS0 = 0) is recommended if the on-chip oscillator is used on the H8/38124 Group. 5.3.4 Standby Mode Transition and Pin States When ...

Page 155

Notes on External Input Signal Changes before/after Standby Mode 1. When external input signal changes before/after standby mode or watch mode When an external input signal such as IRQ, WKP, or IRQAEC is input, both the high- and low-level ...

Page 156

Section 5 Power-Down Modes Active (high-speed, Operating medium-speed) mode mode or subactive mode φ or φ SUB External input signal Capture possible: case 1 Capture possible: case 2 Capture possible: case 3 Capture not possible Figure 5.3 External Input Signal ...

Page 157

Clearing Watch Mode Watch mode is cleared by an interrupt (timer A, timer F, timer G, IRQ0, or WKP7 to WKP0 input at the RES pin. • Clearing by interrupt When watch mode is cleared by interrupt, ...

Page 158

Section 5 Power-Down Modes 5.5 Subsleep Mode 5.5.1 Transition to Subsleep Mode The system goes from subactive mode to subsleep mode when a SLEEP instruction is executed while the SSBY bit in SYSCR1 is cleared to 0, LSON bit in ...

Page 159

Subactive Mode 5.6.1 Transition to Subactive Mode Subactive mode is entered from watch mode if a timer A, timer F, timer G, IRQ WKP interrupt is requested while the LSON bit in SYSCR1 is set to 1. From subsleep ...

Page 160

Section 5 Power-Down Modes 5.7 Active (Medium-Speed) Mode 5.7.1 Transition to Active (Medium-Speed) Mode If the MSON bit in SYSCR2 is set to 1 while the LSON bit in SYSCR1 is cleared transition to active (medium-speed) mode ...

Page 161

Direct Transfer 5.8.1 Overview of Direct Transfer The CPU can execute programs in three modes: active (high-speed) mode, active (medium-speed) mode, and subactive mode. A direct transfer is a transition among these three modes without the stopping of program ...

Page 162

Section 5 Power-Down Modes • Direct transfer from active (medium-speed) mode to subactive mode When a SLEEP instruction is executed in active (medium-speed) mode while the SSBY and LSON bits in SYSCR1 are set to 1, the DTON bit in ...

Page 163

Time for direct transition from active (medium-speed) mode to active (high-speed) mode A direct transition from active (medium-speed) mode to active (high-speed) mode is performed by executing a SLEEP instruction in active (medium-speed) mode while bits SSBY and LSON ...

Page 164

Section 5 Power-Down Modes 4. Time for direct transition from subactive mode to active (medium-speed) mode A direct transition from subactive mode to active (medium-speed) mode is performed by executing a SLEEP instruction in subactive mode while bit SSBY is ...

Page 165

Module Standby Mode 5.9.1 Setting Module Standby Mode Module standby mode is set for individual peripheral functions. All the on-chip peripheral modules can be placed in module standby mode. When a module enters module standby mode, the system clock ...

Page 166

Section 5 Power-Down Modes Register Name Bit Name CKSTPR2 LDCKSTP PW1CKSTP WDCKSTP AECKSTP PW2CKSTP LVDCKSTP* Notes: For details of module operation, see the sections on the individual modules. * LVDCKSTP is implemented on the H8/38124 group only. 5.10 Usage Note ...

Page 167

Overview The H8/38024, H8/38024S, and H8/38124 have 32 Kbytes of on-chip mask ROM, the H8/38023, H8/38023S, and H8/38123 have 24 Kbytes, the H8/38022, H8/38022S, and H8/38122 have 16 Kbytes, the H8/38021, H8/38021S, and H8/38121 have 12 Kbytes, and the ...

Page 168

Section 6 ROM 6.2 H8/38024 PROM Mode 6.2.1 Setting to PROM Mode If the on-chip ROM is PROM, setting the chip to PROM mode stops operation as a microcontroller and allows the PROM to be programmed in the same way ...

Page 169

H8/38024 FP-80A, TFP-80C FP-80B RES ...

Page 170

Section 6 ROM Address in MCU mode Note: * The output data is not guaranteed if this address area is read in PROM mode. Therefore, when programming with a PROM programmer, be sure to specify addresses from H'0000 to H'7FFF. ...

Page 171

H8/38024 Programming The write, verify, and other modes are selected as shown in table 6.2 in H8/38024 PROM mode. Table 6.2 Mode Selection in PROM Mode (H8/38024 Mode Write L H Verify L L Programming L L ...

Page 172

Section 6 ROM Yes No n < 25 Error Figure 6.4 High-Speed, High-Reliability Programming Flowchart Rev. 8.00 Mar. 09, 2010 Page 150 of 658 REJ09B0042-0800 Start Set write/verify mode = 6.0 V ± 0. 12.5 V ± ...

Page 173

Tables 6.3 and 6.4 give the electrical characteristics in programming mode. Table 6.3 DC Characteristics Conditions 6.0 V ±0. Item Input high-level voltage OE, CE, PGM Input ...

Page 174

Section 6 ROM Table 6.4 AC Characteristics Conditions 6.0 V ±0. Item Address setup time OE setup time Data setup time Address hold time Data hold time Data output disable time V setup time PP ...

Page 175

Figure 6.5 shows a PROM write/verify timing diagram. Address t AS Data Input data VPS VCS CES PGM ...

Page 176

Section 6 ROM 6.3.2 Programming Precautions • Use the specified programming voltage and timing. The programming voltage in PROM mode (V permanently damage the chip. Be especially careful with respect to PROM programmer overshoot. Setting the PROM programmer to Renesas ...

Page 177

Reliability of Programmed Data A highly effective way to improve data retention characteristics is to bake the programmed chips at 150°C, then screen them for data errors. This procedure quickly eliminates chips with PROM memory cells prone to early ...

Page 178

Section 6 ROM 6.5 Flash Memory Overview 6.5.1 Features The features of the 32-Kbyte or 16-Kbyte flash memory built into the flash memory versions are summarized below. • Programming/erase methods ⎯ The flash memory is programmed 128 bytes at a ...

Page 179

Block Diagram FLMCR1 FLMCR2 EBR FLPWCR FENR [Legend] FLMCR1: Flash memory control register 1 FLMCR2: Flash memory control register 2 EBR: Erase block register FLPWCR: Flash memory power control register FENR: Flash memory enable register Figure 6.7 Block Diagram ...

Page 180

Section 6 ROM 6.5.3 Block Configuration Figure 6.8 shows the block configuration of the flash memory. The thick lines indicate erasing units, the narrow lines indicate programming units, and the values are addresses. In versions with 32 Kbytes of flash ...

Page 181

H'0000 H'0001 Erase unit H'0080 H'0081 1 Kbyte H'0380 H'0381 H'0400 H'0401 Erase unit H'0480 H'0481 1 Kbyte H'0780 H'0781 H'0800 H'0801 H'0880 H'0881 Erase unit 1 Kbyte H'0B80 H'0B81 H'0C00 H'0C01 Erase unit H'0C80 H'0C81 1 Kbyte H'0F80 H'0F81 ...

Page 182

Section 6 ROM 6.5.4 Register Configuration Table 6.5 lists the register configuration to control the flash memory when the built in flash memory is effective. Table 6.5 Register Configuration Register Name Flash memory control register 1 Flash memory control register ...

Page 183

Bit 6—Software Write Enable (SWE) This bit is to set enabling/disabling of programming/enabling of flash memory (set when bits and the EBR register are to be set). Bit 6 SWE Description 0 Programming/erasing is disabled. Other FLMCR1 ...

Page 184

Section 6 ROM Bit 3 EV Description 0 Erase-verify mode is cancelled 1 The flash memory changes to erase-verify mode Bit 2—Program-Verify (PV) This bit is to set changing to or cancelling program-verify mode (do not set SWE, ESU, PSU, ...

Page 185

Flash Memory Control Register 2 (FLMCR2) Bit 7 FLER Initial value 0 Read/Write R FLMCR2 is a register that displays the state of flash memory programming/erasing. FLMCR2 is a read-only register, and should not be written to. Bit 7—Flash ...

Page 186

Section 6 ROM 6.6.3 Erase Block Register (EBR) Bit 7 — Initial value 0 Read/Write — EBR specifies the flash memory erase area block. EBR is initialized to H'00 when the SWE bit in FLMCR1 not set ...

Page 187

Bit 7—Power-down Disable (PDWND) This bit selects the power-down mode of the flash memory when a transition to the subactive mode is made. Bit 7 PDWND Description 0 When this bit is 0 and a transition is made to the ...

Page 188

Section 6 ROM 6.7 On-Board Programming Modes There are two modes for programming/erasing of the flash memory; boot mode, which enables on- board programming/erasing, and programmer mode, in which programming/erasing is performed with a PROM programmer. On-board programming/erasing can also ...

Page 189

When the boot program is initiated, the chip measures the low-level period of asynchronous SCI communication data (H'00) transmitted continuously from the host. The chip then calculates the bit rate of transmission from the host, and adjusts the SCI3 ...

Page 190

Section 6 ROM Table 6.8 Boot Mode Operation Host Operation Processing Contents Item Bit rate Continuously transmits data H'00 at adjustment specified bit rate. Flash memory erase Transmits data H'55 when data H'00 is received and no error occurs. Transfer ...

Page 191

Programming/Erasing in User Program Mode The term user mode refers to the status when a user program is being executed. On-board programming/erasing of an individual flash memory block can also be performed in user program mode by branching to ...

Page 192

Section 6 ROM 6.7.3 Notes on On-Board Programming 1. You must use the system clock oscillator when programming or erasing flash memory on the H8/38124 Group. The on-chip oscillator should not be used for programming or erasing flash memory. See ...

Page 193

Consecutively transfer 128 bytes of data in byte units from the reprogramming data area or additional-programming data area to the flash memory. The ...

Page 194

Section 6 ROM Write pulse application subroutine Apply Write Pulse WDT enable Set PSU bit in FLMCR1 Wait 50 μs Set P bit in FLMCR1 Wait (Wait time = programming time) Clear P bit in FLMCR1 Wait 5 μs Clear ...

Page 195

Table 6.10 Reprogram Data Computation Table Program Data Verify Data Table 6.11 Additional-Program Data Computation Table Reprogram Data Verify Data Table 6.12 Programming Time ...

Page 196

Section 6 ROM 6.8.2 Erase/Erase-Verify When erasing flash memory, the erase/erase-verify flowchart shown in figure 6.11 should be followed. 1. Prewriting (setting erase block data to all 0s) is not necessary. 2. Erasing is performed in block units. Make only ...

Page 197

Erase start SWE bit ← 1 Wait 1 μs n ← 1 Set EBR Enable WDT ESU bit ← 1 Wait 100 μs E bit ← 1 Wait bit ← 0 Wait 10 μs ESU bit ← ...

Page 198

Section 6 ROM 6.9 Program/Erase Protection There are three kinds of flash memory program/erase protection; hardware protection, software protection, and error protection. 6.9.1 Hardware Protection Hardware protection refers to a state in which programming/erasing of flash memory is forcibly disabled ...

Page 199

Error Protection In error protection, an error is detected when CPU runaway occurs during flash memory programming/erasing, or operation is not performed in accordance with the program/erase algorithm, and the program/erase operation is aborted. Aborting the program/erase operation prevents ...

Page 200

Section 6 ROM 6.10.2 Programmer Mode Commands The following commands are supported in programmer mode. • Memory Read Mode • Auto-Program Mode • Auto-Erase Mode • Status Read Mode Status polling is used for auto-programming, auto-erasing, and status read modes. ...

Related keywords