R5F61668RN50FPV Renesas Electronics America, R5F61668RN50FPV Datasheet
R5F61668RN50FPV
Specifications of R5F61668RN50FPV
Available stocks
Related parts for R5F61668RN50FPV
R5F61668RN50FPV Summary of contents
Page 1
To our customers, Old Company Name in Catalogs and Other Documents st On April 1 , 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the ...
Page 2
All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm ...
Page 3
H8SX/1668R Group, 32 H8SX/1668M Group Hardware Manual Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series All information contained in these materials, including products and product specifications, represents information on the product at the time of publication and is subject ...
Page 4
Rev. 2.00 Sep. 24, 2008 Page ii of xxxii ...
Page 5
This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in ...
Page 6
General Precautions in the Handling of MPU/MCU Products The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes on the products covered by this manual, refer to the relevant sections of the manual. If ...
Page 7
Objective and Target Users This manual was written to explain the hardware functions and electrical characteristics of this LSI to the target users, i.e. those who will be using this LSI in the design of application systems. Target users ...
Page 8
Description of Numbers and Symbols Aspects of the notations for register names, bit names, numbers, and symbolic names in this manual are explained below. (1) Overall notation In descriptions involving the names of bits and bit fields within this ...
Page 9
Description of Registers Each register description includes a bit chart, illustrating the arrangement of bits, and a table of bits, describing the meanings of the bit settings. The standard format and notation for bit charts and tables are described ...
Page 10
Description of Abbreviations The abbreviations used in this manual are listed below. • Abbreviations specific to this product Abbreviation Description BSC Bus controller CPG Clock pulse generator DTC Data transfer controller INTC Interrupt controller PPG Programmable pulse generator SCI ...
Page 11
Section 1 Overview................................................................................................1 1.1 Features................................................................................................................................. 1 1.1.1 Applications .......................................................................................................... 1 1.1.2 Overview of Functions.......................................................................................... 2 1.2 List of Products................................................................................................................... 10 1.3 Block Diagram.................................................................................................................... 12 1.4 Pin Assignments ................................................................................................................. 13 1.4.1 Pin Assignments ................................................................................................. 13 1.4.2 Correspondence between Pin Configuration and ...
Page 12
Addressing Modes and Effective Address Calculation....................................................... 67 2.8.1 Register Direct—Rn ........................................................................................... 67 2.8.2 Register Indirect—@ERn................................................................................... 68 2.8.3 Register Indirect with Displacement —@(d:2, ERn), @(d:16, ERn), or @(d:32, ERn)...................................................................................................... 68 2.8.4 Index Register Indirect with Displacement—@(d:16,RnL.B), @(d:32,RnL.B), @(d:16,Rn.W), @(d:32,Rn.W), @(d:16,ERn.L), ...
Page 13
Section 4 Resets ...................................................................................................95 4.1 Types of Resets................................................................................................................... 95 4.2 Input/Output Pin ................................................................................................................. 97 4.3 Register Descriptions.......................................................................................................... 98 4.3.1 Reset Status Register (RSTSR)........................................................................... 98 4.3.2 Reset Control/Status Register (RSTCSR)......................................................... 100 4.4 Pin Reset ........................................................................................................................... 101 4.5 Power-on Reset (POR) (H8SX/1668M ...
Page 14
Instruction Exception Handling ........................................................................................ 124 6.7.1 Trap Instruction ................................................................................................ 124 6.7.2 Sleep Instruction Exception Handling .............................................................. 125 6.7.3 Exception Handling by Illegal Instruction ........................................................ 126 6.8 Stack Status after Exception Handling ............................................................................. 127 6.9 Usage Note ....................................................................................................................... 128 Section ...
Page 15
Section 8 User Break Controller (UBC) ............................................................171 8.1 Features............................................................................................................................. 171 8.2 Block Diagram.................................................................................................................. 172 8.3 Register Descriptions........................................................................................................ 173 8.3.1 Break Address Register n (BARA, BARB, BARC, BARD) ............................ 174 8.3.2 Break Address Mask Register n (BAMRA, BAMRB, BAMRC, BAMRD) .... ...
Page 16
Chip Select Signals ........................................................................................... 230 9.5.4 External Bus Interface ...................................................................................... 231 9.5.5 Area and External Bus Interface ....................................................................... 236 9.5.6 Endian and Data Alignment.............................................................................. 241 9.6 Basic Bus Interface ........................................................................................................... 244 9.6.1 Data Bus ........................................................................................................... 244 9.6.2 I/O Pins ...
Page 17
DRAM Interface ............................................................................................................... 280 9.10.1 Setting DRAM Space........................................................................................ 280 9.10.2 Address Multiplexing........................................................................................ 280 9.10.3 Data Bus............................................................................................................ 281 9.10.4 I/O Pins Used for DRAM Interface .................................................................. 281 9.10.5 Basic Timing..................................................................................................... 282 9.10.6 Controlling Column Address Output Cycle...................................................... 283 9.10.7 Controlling ...
Page 18
Write Data Buffer Function .............................................................................................. 365 9.15.1 Write Data Buffer Function for External Data Bus .......................................... 365 9.15.2 Write Data Buffer Function for Peripheral Modules ........................................ 366 9.16 Bus Arbitration ................................................................................................................. 367 9.16.1 Operation .......................................................................................................... 367 9.16.2 Bus Transfer ...
Page 19
Section 11 EXDMA Controller (EXDMAC) ....................................................453 11.1 Features............................................................................................................................. 453 11.2 Input/Output Pins.............................................................................................................. 456 11.3 Registers Descriptions ...................................................................................................... 457 11.3.1 EXDMA Source Address Register (EDSAR)................................................... 459 11.3.2 EXDMA Destination Address Register (EDDAR)........................................... 460 11.3.3 EXDMA Offset Register (EDOFR).................................................................. 461 11.3.4 EXDMA ...
Page 20
Section 12 Data Transfer Controller (DTC)...................................................... 559 12.1 Features............................................................................................................................. 559 12.2 Register Descriptions........................................................................................................ 561 12.2.1 DTC Mode Register A (MRA) ......................................................................... 562 12.2.2 DTC Mode Register B (MRB).......................................................................... 563 12.2.3 DTC Source Address Register (SAR)............................................................... 564 12.2.4 DTC Destination Address ...
Page 21
Transfer Information Modification ................................................................... 593 12.9.8 Endian Format................................................................................................... 593 12.9.9 Points for Caution when Overwriting DTCER ................................................. 594 Section 13 I/O Ports ...........................................................................................595 13.1 Register Descriptions........................................................................................................ 603 13.1.1 Data Direction Register (PnDDR ...
Page 22
Port Function Control Register B (PFCRB) ..................................................... 677 13.3.11 Port Function Control Register C (PFCRC) ..................................................... 679 13.3.12 Port Function Control Register D (PFCRD) ..................................................... 680 13.4 Usage Notes ...................................................................................................................... 681 13.4.1 Notes on Input Buffer Control Register (ICR) ...
Page 23
Conflict between TGR Write and Compare Match........................................... 769 14.10.7 Conflict between Buffer Register Write and Compare Match .......................... 770 14.10.8 Conflict between TGR Read and Input Capture ............................................... 770 14.10.9 Conflict between TGR Write and Input Capture .............................................. 771 ...
Page 24
Time Constant Register A (TCORA)................................................................ 819 16.3.3 Time Constant Register B (TCORB) ................................................................ 820 16.3.4 Timer Control Register (TCR).......................................................................... 820 16.3.5 Timer Counter Control Register (TCCR) ......................................................... 822 16.3.6 Timer Control/Status Register (TCSR)............................................................. 827 16.4 Operation .......................................................................................................................... 831 16.4.1 ...
Page 25
EXCKSN=0 Operation ..................................................................................... 850 17.4 Interrupt Source ................................................................................................................ 853 17.5 Usage Notes ...................................................................................................................... 854 17.5.1 Changing Values of Bits EXCKSN, CKS1, and CKS0 .................................... 854 17.5.2 Note on Register Initialization .......................................................................... 854 17.5.3 Usage Notes on 32K Timer............................................................................... 854 ...
Page 26
Serial Extended Mode Register (SEMR_2) ...................................................... 902 19.3.11 Serial Extended Mode Register 5 and 6 (SEMR_5 and SEMR_6)................... 904 19.3.12 IrDA Control Register (IrCR)........................................................................... 911 19.4 Operation in Asynchronous Mode .................................................................................... 912 19.4.1 Data Transfer Format........................................................................................ 913 19.4.2 Receive ...
Page 27
Receive Error Flags and Transmit Operations (Clocked Synchronous Mode Only) ................................................................. 953 19.10.5 Relation between Writing to TDR and TDRE Flag .......................................... 954 19.10.6 Restrictions on Using DTC or DMAC.............................................................. 954 19.10.7 SCI Operations during Power-Down State ....................................................... 955 ...
Page 28
Transceiver Test Register 0 (TRNTREG0) ...................................................... 996 20.3.27 Transceiver Test Register 1 (TRNTREG1) ...................................................... 998 20.4 Interrupt Sources............................................................................................................. 1000 20.5 Operation ........................................................................................................................ 1002 20.5.1 Cable Connection............................................................................................ 1002 20.5.2 Cable Disconnection ....................................................................................... 1003 20.5.3 Suspend and Resume Operations.................................................................... 1003 20.5.4 ...
Page 29
I C Bus Status Register (ICSR)....................................................................... 1045 21.3.6 Slave Address Register (SAR)........................................................................ 1048 2 21.3 Bus Transmit Data Register (ICDRT)....................................................... 1049 2 21.3 Bus Receive Data Register (ICDRR)........................................................ 1049 2 21.3 Bus ...
Page 30
Notes on Board Design ................................................................................... 1095 22.7.8 Notes on Noise Countermeasures ................................................................... 1095 Section 23 D/A Converter ............................................................................... 1097 23.1 Features........................................................................................................................... 1097 23.2 Input/Output Pins............................................................................................................ 1098 23.3 Register Descriptions...................................................................................................... 1098 23.3.1 D/A Data Registers 0 and 1 (DADR0 and ...
Page 31
Error Protection............................................................................................... 1168 25.10 Flash Memory Emulation Using RAM........................................................................... 1170 25.11 Switching between User MAT and User Boot MAT...................................................... 1173 25.12 Programmer Mode .......................................................................................................... 1174 25.13 Standard Serial Communications Interface Specifications for Boot Mode..................... 1174 25.14 Usage Notes .................................................................................................................... ...
Page 32
Section 28 Power-Down Modes...................................................................... 1235 28.1 Features........................................................................................................................... 1235 28.2 Register Descriptions...................................................................................................... 1239 28.2.1 Standby Control Register (SBYCR) ............................................................... 1239 28.2.2 Module Stop Control Registers A and B (MSTPCRA and MSTPCRB) ........ 1242 28.2.3 Module Stop Control Register C (MSTPCRC)............................................... 1245 ...
Page 33
Timing Sequence at Power-On ....................................................................... 1280 28.10 Sleep Instruction Exception Handling ............................................................................ 1281 28.11 φ Clock Output Control................................................................................................... 1284 28.12 Usage Notes .................................................................................................................... 1285 28.12.1 I/O Port Status................................................................................................. 1285 28.12.2 Current Consumption during Oscillation Settling Standby Period ................. 1285 ...
Page 34
Main Revisions and Additions in this Edition................................................... 1433 Index ................................................................................................................. 1461 Rev. 2.00 Sep. 24, 2008 Page xxxii of xxxii ...
Page 35
Features The core of each product in the H8SX/1668R Group and H8SX/1668M Group of CISC (complex instruction set computer) microcontrollers is an H8SX CPU, which has an internal 32-bit architecture. The H8SX CPU provides upward-compatibility with the CPUs of ...
Page 36
Section 1 Overview 1.1.2 Overview of Functions Table 1.1 lists the functions of these LSI products in outline. Table 1.2 shows the comparison of support functions in each group. Table 1.1 Overview of Functions Module/ Classification Function Memory ROM RAM ...
Page 37
Module/ Classification Function CPU MCU operating mode Power on reset (POR) * Voltage detection circuit (LVD)* Interrupt Interrupt (source) controller (INTC) Break interrupt (UBC) Description Mode 1: User boot mode (selected by driving the MD2 and MD1 pins low and ...
Page 38
Section 1 Overview Module/ Classification Function DMA EXDMA controller (EXDMAC) DMA controller (DMAC) Data transfer controller (DTC) External bus Bus extension controller (BSC) Rev. 2.00 Sep. 24, 2008 Page 4 of 1468 REJ09B0412-0200 Description • Four-channel DMA transfer available • ...
Page 39
Module/ Classification Function External bus Bus extension controller (BSC) Clock Clock pulse generator (CPG) Description Bus formats • External memory interfaces (for the connection of ROM, burst ROM, SRAM, byte control SRAM, DRAM, and synchronous DRAM) • Address/data bus format: ...
Page 40
Section 1 Overview Module/ Classification Function A/D converter A/D converter (ADC) D/A converter D/A converter (DAC) Timer 8-bit timer (TMR) Rev. 2.00 Sep. 24, 2008 Page 6 of 1468 REJ09B0412-0200 Description • 10-bit resolution × two units • Selectable input ...
Page 41
Module/ Classification Function Timer 16-bit timer pulse unit (TPU) Program- mable pulse generator (PPG) Watchdog timer Watchdog timer (WDT) 32K timer 32K timer (TM32K) Description • 16 bits × 12 channels (unit 0, unit 1*) • Select from among eight ...
Page 42
Section 1 Overview Module/ Classification Function Serial interface Serial communi- cations interface (SCI) Smart card/SIM Universal serial Universal bus interface serial bus interface (USB bus interface I C bus interface 2 (IIC2) I/O ports Package Operating ...
Page 43
Table 1.2 Comparison of Support Functions in the H8SX/1668R Group and H8SX/1668M Group Function DMAC DTC PPG UBC SCI IIC2 TMR WDT 10-bit ADC 8-bit DAC EXDMAC SDRAM interface 32K timer POR/LVD Package LQFP-144 LFBGA-176 H8SX/1668R Group ...
Page 44
... Section 1 Overview 1.2 List of Products Table 1.3 is the list of products, and figure 1.1 shows how to read the product name code. Table 1.3 List of Products Group Part No. H8SX/1668R R5F61668RN50FPV Group R5F61664RN50FPV R5F61663RN50FPV R5F61668RN50BGV 1024 Kbytes R5F61664RN50BGV 512 Kbytes R5F61663RN50BGV 384 Kbytes R5F61668RD50FPV R5F61664RD50FPV ...
Page 45
Part No 61668RN50 FP Figure 1.1 How to Read the Product Name Code • Small Package Package Package Code PLQP0144KA-A (FP-144LV)* 20.0 × 20.0 mm LQFP-144 LFBGA-176 PLBG0176GA-A (BP-176V)* Note: * Pb-free version V Indicates the Pb-free ...
Page 46
Section 1 Overview 1.3 Block Diagram RAM ROM H8SX CPU DTC Main clock oscillator Subclock oscillator 2 POR/LVD* [Legend] CPU: Central processing unit DTC: Data transfer controller BSC: Bus controller DMAC: DMA controller EXDMAC: EXDMA controller TM32K: 32K timer WDT: ...
Page 47
Pin Assignments 1.4.1 Pin Assignments 108 107 106 105 104 103 102 101 100 P62/TMO2/SCK4/DACK2/IRQ10-B/TRST/EDACK0-B 109 110 PLLV cc 111 P63/TMRI3/DREQ3/IRQ11-B/TMS/EDREQ1-B 112 PLLV ss 113 P64/TMCI3/TEND3/TDI/ETEND1-B P65/TMO3/DACK3/TCK/EDACK1-B 114 ...
Page 48
Section 1 Overview PB1 PA4 PB3 B PB0 PA7 PA5 PB2 PA6 MD2 PB7 PM2 PM1 ...
Page 49
Correspondence between Pin Configuration and Operating Modes Table 1.4 Pin Configuration in Each Operating Mode (H8SX/1668RGroup, H8SX/1668M Group) Pin No. LQFP- LFBG 144 A-176 Modes 1, 2, and PB1/CS1/CS2-B/CS5-A/CS6- B/ CS7 PB2/CS2-A/CS6-A/RAS 3 B1 ...
Page 50
Section 1 Overview Pin No. LQFP- LFBG 144 A-176 Modes 1, 2, and PE7/A15 21 J4 PE6/A14 22 J3 PE5/A13 23 J1 Vss 24 J2 PE4/A12 25 K4 Vcc PE3/A11 27 K2 ...
Page 51
Pin No. LQFP- LFBG 144 A-176 Modes 1, 2, and PD2/ PD1/ PD0/ EMLE PM3 PM4 42 R3 DrVcc 43 P4 ...
Page 52
Section 1 Overview Pin No. LQFP- LFBG 144 A-176 Modes 1, 2, and P21/PO1/TIOCA3/TMCI0/Rx D0/ IRQ9 P22/PO2/TIOCC3/TMO0/TxD 0/ IRQ10 P23/PO3/TIOCC3/TIOCD3/ IRQ11 P24/PO4/TIOCA4/TIOCB4/T MRI1/ SCK1 55 R9 P25/PO5/TIOCA4/TMCI1/ P30/PO8/TIOCA0/DREQ0-B/ ...
Page 53
Pin No. LQFP- LFBG 144 A-176 Modes 1, 2, and 6 71 R14 PH5/D5 72 P14 PH6/D6 73 R15 PH7/D7 N13 VSS 74 P15 Vcc N14 NC 75 M13 PI0/D8 76 N15 PI1/D9 77 M14 PI2/D10 78 L12 ...
Page 54
Section 1 Overview Pin No. LQFP- LFBG 144 A-176 Modes 1, 2, and 6 RES 91 G12 92 G13 VCL 93 G15 P14/TCLKA- B/TxD5/IrTXD/SDA1/ DREQ1-A/IRQ4-A/EDREQ1 G14 P15/TCLKB- B/RxD5/IrRxD/SCL1/ TEND1-A/IRQ5-A/ETEND1-A WDTOVF 95 F12 96 F13 Vss 97 F15 XTAL ...
Page 55
Pin No. LQFP- LFBG 144 A-176 Modes 1, 2, and 6 110 A15 PLLVcc 111 C13 P63/TMRI3/DREQ3/ IRQ11-B/EDREQ1-B A14 NC 112 B13 PLLVss 113 C12 P64/TMCI3/TEND3/ETEND1- B 114 A13 P65/TMO3/DACK3/EDACK1- B 115 B12 MD0 116 D11 PC2/LUCAS/DQMLU 117 A12 ...
Page 56
Section 1 Overview Pin No. LQFP- LFBG 144 A-176 Modes 1, 2, and 6 129 B7 MD1 130 D6 PB4/CS4-B/WE 131 C6 PB5/CS5-D/OE/CKE 132 A6 PB6/CS6-D/(RD/WR- B)/ADTRG0-B 133 B6 MD3 134 C5 PA0/BREQO/BS-A 135 A5 PA1/BACK/(RD/WR-A) 136 B5 PA2/BREQ/WAIT 137 ...
Page 57
Pin Functions Table 1.5 Pin Functions Classification Pin Name Power supply PLLV CC PLLV SS DrV CC DrV SS Clock XTAL EXTAL OSC1 OSC2 Bφ SDRAMφ Operating mode MD3 to MD0 Input control ...
Page 58
Section 1 Overview Classification Pin Name Address bus A23 to A0 Data bus D15 to D0 BREQ Bus control BREQO BACK BS-A/BS RD/WR-A/RD/WR-B Output LHWR LLWR LUB LLB Rev. 2.00 Sep. 24, 2008 Page 24 of 1468 ...
Page 59
Classification Pin Name CS0 Bus control CS1 CS2-A/CS2-B CS3-A CS4-A/CS4-B CS5-A/CS5-B/ CS5-D CS6-A/CS6-B/ CS6-D CS7-A/CS7-B WAIT RAS CAS WE OE/CKE LUCAS LLCAS DQMLU DQMLL I/O Description Output Select signals for areas Input Requests wait cycles in access ...
Page 60
Section 1 Overview Classification Pin Name Interrupt NMI IRQ11-A/IRQ11-B IRQ10-A/IRQ10-B IRQ9-A/IRQ9-B IRQ8-A/IRQ8-B IRQ7-A/IRQ7-B IRQ6-A/IRQ6-B IRQ5-A/IRQ5-B IRQ4-A/IRQ4-B IRQ3-A/IRQ3-B IRQ2-A/IRQ2-B IRQ1-A/IRQ1-B IRQ0-A/IRQ0-B DREQ0-A/DREQ0-B DMA controller DREQ1-A/DREQ1-B (DMAC) DREQ2 DREQ3 DACK0-A/DACK0-B DACK1-A/DACK1-B DACK2 DACK3 TEND0-A/TEND0-B TEND1-A/TEND1-B TEND2 TEND3 Rev. 2.00 Sep. 24, 2008 ...
Page 61
Classification Pin Name EDREQ0-A/ EXDMA EDREQ0-B controller EDREQ1-A/ (EXDMAC) EDREQ1-B EDREQ2 EDREQ3 EDACK0-A/ EDACK0-B EDACK1-A/ EDACK1-B EDACK2 EDACK3 ETEND0-A/ ETEND0-B ETEND1-A/ ETEND1-B ETEND2 ETEND3 EDRAK0 EDRAK1 16-bit timer TCLKA-A/TCLKA-B pulse unit (TPU) TCLKB-A/TCLKB-B TCLKC-A/TCLKC-B TCLKD-A/TCLKD-B TIOCA0 TIOCB0 TIOCC0 TIOCD0 TIOCA1 ...
Page 62
Section 1 Overview Classification Pin Name 16-bit timer TIOCA5 pulse unit (TPU) TIOCB5 TCLKE TCLKF TCLKG TCLKH TIOCA6 TIOCB6 TIOCC6 TIOCD6 TIOCA7 TIOCB7 TIOCA8 TIOCB8 TIOCA9 TIOCB9 TIOCC9 TIOCD9 TIOCA10 TIOCB10 TIOCA11 TIOCB11 Programmable PO31 to PO0 pulse generator (PPG) ...
Page 63
Classification Pin Name Serial TxD0 communications TxD1 interface (SCI) TxD2 TxD4 TxD5 TxD6 RxD0 RxD1 RxD2 RxD4 RxD5 RxD6 SCK0 SCK1 SCK2 SCK4 SCI with IrDA IrTxD (SCI) IrRxD bus interface SCL0 2 (IIC2) SCL1 SDA0 SDA1 ...
Page 64
Section 1 Overview Classification Pin Name A/D converter D/A converter AV SS Vref I/O ports P17 to P10 P27 to P20 P37 to P30 P57 to P50 P65 to P60 PA7 PA6 to PA0 PB7 to PB0 PC3 ...
Page 65
Classification Pin Name I/O ports PJ7 to PJ0* PK7 to PK0* Note: * These pins can be used when the PCJKE bit in PFCRD is set single-chip mode. I/O Description Input/ 8-bit input/output pins. output Input/ 8-bit ...
Page 66
Section 1 Overview Rev. 2.00 Sep. 24, 2008 Page 32 of 1468 REJ09B0412-0200 ...
Page 67
The H8SX CPU is a high-speed CPU with an internal 32-bit architecture that is upward compatible with the H8/300, H8/300H, and H8S CPUs. The H8SX CPU has sixteen 16-bit general registers, can handle a 4-Gbyte linear address space, and is ...
Page 68
Section 2 CPU • Two base registers Vector base register Short address base register • 4-Gbyte address space Program: 4 Gbytes Data: 4 Gbytes • High-speed operation All frequently-used instructions executed in one or two ...
Page 69
CPU Operating Modes The H8SX CPU has four operating modes: normal, middle, advanced and maximum modes. These modes can be selected by the mode pins of this LSI. CPU operating modes 2.2.1 Normal Mode The exception vector table and ...
Page 70
Section 2 CPU • Exception Vector Table and Memory Indirect Branch Addresses In normal mode, the top area starting at H'0000 is allocated to the exception vector table. One branch address is stored per 16 bits. The structure of the ...
Page 71
Middle Mode The program area in middle mode is extended to 16 Mbytes as compared with that in normal mode. • Address Space The maximum address space of 16 Mbytes can be accessed as a total of the program ...
Page 72
Section 2 CPU 2.2.3 Advanced Mode The data area is extended to 4 Gbytes as compared with that in middle mode. • Address Space The maximum address space of 4 Gbytes can be linearly accessed. For individual areas ...
Page 73
Stack Structure The stack structure subroutine branch and that of PC and CCR at an exception handling are shown in figure 2.5. The PC contents are saved or restored in 24-bit units. SP Reserved (a) ...
Page 74
Section 2 CPU H'00000000 H'00000001 H'00000002 H'00000003 H'00000004 H'00000005 H'00000006 H'00000007 Figure 2.6 Exception Vector Table (Maximum Modes) The memory indirect (@@aa:8) and extended memory indirect (@@vec:7) addressing modes are used in the JMP and JSR instructions. An 8-bit absolute ...
Page 75
Instruction Fetch The H8SX CPU has two modes for instruction fetch: 16-bit and 32-bit modes recommended that the mode be set according to the bus width of the memory in which a program is stored. The instruction-fetch ...
Page 76
Section 2 CPU 2.5 Registers The H8SX CPU has the internal registers shown in figure 2.9. There are two types of registers: general registers and control registers. The control registers are the 32-bit program counter (PC), 8-bit extended control register ...
Page 77
General Registers The H8SX CPU has eight 32-bit general registers. These general registers are all functionally alike and can be used as both address registers and data registers. When a general register is used as a data register, it ...
Page 78
Section 2 CPU General register ER7 has the function of stack pointer (SP) in addition to its general-register function, and is used implicitly in exception handling and subroutine branches. Figure 2.11 shows the stack. SP (ER7) 2.5.2 Program Counter (PC) ...
Page 79
Condition-Code Register (CCR) CCR is an 8-bit register that contains internal CPU status information, including an interrupt mask (I) and user (UI, U) bits and half-carry (H), negative (N), zero (Z), overflow (V), and carry (C) flags. Operations can ...
Page 80
Section 2 CPU Initial Bit Bit Name Value 2 Z Undefined R Undefined R Undefined R/W 2.5.4 Extended Control Register (EXR) EXR is an 8-bit register that contains the trace bit (T) and three interrupt mask ...
Page 81
Vector Base Register (VBR) VBR is a 32-bit register in which the upper 20 bits are valid. The lower 12 bits of this register are read as 0s. This register is a base address of the vector area for ...
Page 82
Section 2 CPU 2.6 Data Formats The H8SX CPU can process 1-bit, 4-bit BCD, 8-bit (byte), 16-bit (word), and 32-bit (longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit … ...
Page 83
Memory Data Formats Figure 2.13 shows the data formats in memory. The H8SX CPU can access word data and longword data which are stored at any addresses in memory. When word data begins at an odd address or longword ...
Page 84
Section 2 CPU 2.7 Instruction Set The H8SX CPU has 87 types of instructions. The instructions are classified by function as shown in table 2.1. The arithmetic operation, logic operation, shift, and bit manipulation instructions are called operation instruction in ...
Page 85
Function Instructions Branch BRA/BS, BRA/BC, BSR/BS, BSR/BC 4 Bcc* , JMP, BSR, JSR, RTS RTS/L BRA/S System control TRAPA, RTE, SLEEP, NOP RTE/L LDC, STC, ANDC, ORC, XORC [Legend] B: Byte size W: Word size L: Longword size Notes: 1. ...
Page 86
Section 2 CPU 2.7.1 Instructions and Addressing Modes Table 2.2 indicates the combinations of instructions and addressing modes that the H8SX CPU can use. Table 2.2 Combinations of Instructions and Addressing Modes (1) Classifi- cation Instruction Size Data MOV B/W/L ...
Page 87
Classifi- cation Instruction Size Arithmetic MULXS, B/W operations DIVXS MULS, DIVS W/L NEG B W/L EXTU, EXTS W/L TAS B 12 MAC* — 12 CLRMAC* — 12 LDMAC* — 12 STMAC* — Logic AND, OR, XOR B operations B B ...
Page 88
Section 2 CPU Classifi- cation Instruction Size Bit BFLD B manipu- BFST B lation 8 Branch BRA/BS, BRA/BC BSR/BS, BSR/BC* B System LDC B/W* control (CCR, EXR) LDC L (VBR, SBR) STC B/W* (CCR, EXR) STC L (VBR, ...
Page 89
Table 2.2 Combinations of Instructions and Addressing Modes (2) Classifi- cation Instruction Size — Branch BRA/BS, BRA/BC — BSR/BS, BSR/BC — Bcc — BRA — BRA/S — JMP — BSR — JSR — RTS, RTS/L — System TRAPA control — ...
Page 90
Section 2 CPU 2.7.2 Table of Instructions Classified by Function Tables 2.4 to 2.11 summarize the instructions in each functional category. The notation used in these tables is defined in table 2.3. Table 2.3 Operation Notation Operation Notation Description Rd ...
Page 91
Table 2.4 Data Transfer Instructions Instruction Size Function #IMM → (EAd), (EAs) → (EAd) MOV B/W/L Transfers data between immediate data, general registers, and memory. (EAs) → Rd MOVFPE B Rs → (EAs) MOVTPE B @SP+ → Rn POP W/L ...
Page 92
Section 2 CPU Table 2.5 Block Transfer Instructions Instruction Size Function EEPMOV.B B Transfers a data block. EEPMOV.W Transfers byte data which begins at a memory location specified by ER5 to a memory location specified by ER6. The number of ...
Page 93
Table 2.6 Arithmetic Operation Instructions Instruction Size Function (EAd) ± #IMM → (EAd), (EAd) ± (EAs) → (EAd) ADD B/W/L SUB Performs addition or subtraction on data between immediate data, general registers, and memory. Immediate byte data cannot be subtracted ...
Page 94
Section 2 CPU Instruction Size Function Rd ÷ Rs → Rd DIVU W/L Performs unsigned division on data in two general registers: either 16 bits ÷ 16 bits → 16-bit quotient bits ÷ 32 bits → 32-bit quotient. ...
Page 95
Table 2.7 Logic Operation Instructions Instruction Size Function (EAd) ∧ #IMM → (EAd), (EAd) ∧ (EAs) → (EAd) AND B/W/L Performs a logical AND operation on data between immediate data, general registers, and memory. (EAd) ∨ #IMM → (EAd), (EAd) ...
Page 96
Section 2 CPU Table 2.9 Bit Manipulation Instructions Instruction Size Function 1 → (<bit-No.> of <EAd>) BSET B Sets a specified bit in the contents of a general register or a memory location to 1. The bit number is specified ...
Page 97
Instruction Size Function C ∨ [~ (<bit-No.> of <EAd>)] → C BIOR B ORs the carry flag with the inverse of a specified bit in the contents of a general register or a memory location and stores the result in ...
Page 98
Section 2 CPU Instruction Size Function ∼ Z → (<bit-No.> of <EAd>) BISTZ B Transfers the inverse of the zero flag value to a specified bit in the contents of a memory location. The bit number is specified by 3-bit ...
Page 99
Table 2.11 System Control Instructions Instruction Size Function TRAPA — Starts trap-instruction exception handling. RTE — Returns from an exception-handling routine. RTE/L — Returns from an exception-handling routine, restoring data from the stack to multiple general registers. SLEEP — Causes ...
Page 100
Section 2 CPU 2.7.3 Basic Instruction Formats The H8SX CPU instructions consist of 2-byte (1-word) units. An instruction consists of an operation field (op field), a register field (r field), an effective address extension (EA field), and a condition field ...
Page 101
Addressing Modes and Effective Address Calculation The H8SX CPU supports the 11 addressing modes listed in table 2.12. Each instruction uses a subset of these addressing modes. Bit manipulation instructions use register direct, register indirect, or absolute addressing mode ...
Page 102
Section 2 CPU 2.8.2 Register Indirect—@ERn The operand value is the contents of the memory location which is pointed to by the contents of an address register (ERn). ERn is specified by the register field of the instruction code. In ...
Page 103
Register Indirect with Post-Increment, Pre-Decrement, Pre-Increment, or Post-Decrement—@ERn+, @−ERn, @+ERn, or @ERn− • Register indirect with post-increment—@ERn+ The operand value is the contents of a memory location which is pointed to by the contents of an address register (ERn). ...
Page 104
Section 2 CPU Example 2: MOV.B @ER0+, @ER0+ When ER0 before execution is H'00001000, H'00001000 is read and the contents is written at H'00001001. After execution, ER0 is H'00001002. 2.8.6 Absolute Address—@aa:8, @aa:16, @aa:24, or @aa:32 The operand value is ...
Page 105
Immediate—#xx The operand value is 8-bit (#xx:8), 16-bit (#xx:16), or 32-bit (#xx:32) data included in the instruction code. This addressing mode has short formats in which 3- or 4-bit immediate data can be used. When the size of immediate ...
Page 106
Section 2 CPU 2.8.10 Memory Indirect—@@aa:8 This mode can be used by the JMP and JSR instructions. The operand value is a branch address, which is the contents of a memory location pointed 8-bit absolute address in ...
Page 107
Extended Memory Indirect—@@vec:7 This mode can be used by the JMP and JSR instructions. The operand value is a branch address, which is the contents of a memory location pointed to by the following operation result: the sum of ...
Page 108
Section 2 CPU Table 2.14 Effective Address Calculation for Transfer and Operation Instructions No. Addressing Mode and Instruction Format 1 Immediate op IMM Register direct Register indirect Register indirect with 16-bit displacement ...
Page 109
Table 2.15 Effective Address Calculation for Branch Instructions No. Addressing Mode and Instruction Format Register indirect Program-counter relative with 8-bit displacement 2 op disp Program-counter relative with 16-bit displacement op disp Program-counter relative with index register 3 ...
Page 110
Section 2 CPU 2.9 Processing States The H8SX CPU has five main processing states: the reset state, exception-handling state, program execution state, bus-released state, and program stop state. Figure 2.16 indicates the state transitions. • Reset state In this state ...
Page 111
RES = high Exception-handling state Request for exception End of exception handling handling Program execution state A transition to the reset state occurs whenever the STBY signal goes low. Note transition to the reset state occurs when the ...
Page 112
Section 2 CPU Rev. 2.00 Sep. 24, 2008 Page 78 of 1468 REJ09B0412-0200 ...
Page 113
Section 3 MCU Operating Modes 3.1 Operating Mode Selection This LSI has seven operating modes (modes and 7). The operating mode is selected by the setting of mode pins MD2 to MD0. Enabling and ...
Page 114
Section 3 MCU Operating Modes Modes 1 and 2 are the user boot mode and the boot mode, respectively, in which the flash memory can be programmed and erased. For details on the user boot mode and boot mode, see ...
Page 115
Register Descriptions The following registers are related to the operating mode setting. • Mode control register (MDCR) • System control register (SYSCR) 3.2.1 Mode Control Register (MDCR) MDCR indicates the current operating mode. When MDCR is read from, the ...
Page 116
Section 3 MCU Operating Modes Bit Bit Name Initial Value R/W 11 MDS3 Undefined* 10 MDS2 Undefined* 9 MDS1 Undefined* 8 MDS0 Undefined* 7 Undefined* 3 Undefined* 2 ...
Page 117
System Control Register (SYSCR) SYSCR controls MAC saturation operation, selects bus width mode for instruction fetch, sets external bus mode, enables/disables the on-chip RAM, and selects the DTC address mode. Bit 15 14 Bit Name Initial Value ...
Page 118
Section 3 MCU Operating Modes Initial Bit Bit Name Value 10 Undefined 9 EXPE Undefined 8 RAME 1 All 0 1 DTCMD 1 Notes: 1. The initial value depends on the LSI ...
Page 119
Operating Mode Descriptions 3.3.1 Mode 1 This is the user boot mode for the flash memory. The LSI operates in the same way as in mode 7 except for programming and erasing of the flash memory. For details, ...
Page 120
Section 3 MCU Operating Modes 3.3.5 Mode 5 The CPU operating mode is advanced mode in which the address space is 16 Mbytes, and the on- chip ROM is disabled. The initial bus width mode immediately after a reset is ...
Page 121
Pin Functions Table 3.4 shows the pin functions in each operating mode. Table 3.4 Pin Functions in Each Operating Mode (Advanced Mode) MCU Port A Operating Mode PA7 PA6-3 PA2-0 1 P*/C P*/C P*/C 2 P*/C P*/C P*/C 3 ...
Page 122
Section 3 MCU Operating Modes Modes 1 and 2 User boot mode, boot mode (Advanced mode) H'000000 On-chip ROM H'100000 xternal address space reserved area* * H'FD9000 Access prohibited area H'FDC000 External address space reserved ...
Page 123
Mode 6 On-chip ROM enabled extended mode (Advanced mode) H'000000 On-chip ROM H'100000 External address space H'FD9000 Access prohibited area H'FDC000 External address space H'FEC000 Reserved area* H'FEE000 On-chip RAM/ External address space H'FFC000 External address space H'FFEA00 On-chip I/O ...
Page 124
Section 3 MCU Operating Modes Modes 1 and 2 User boot mode, boot mode (Advanced mode) H'000000 On-chip ROM H'080000 Access prohibited area H'100000 External address space reserved area H'FD9000 Access prohibited area H'FDC000 External address ...
Page 125
Mode 6 On-chip ROM enabled extended mode (Advanced mode) H'000000 On-chip ROM H'080000 Access prohibited area H'100000 External address space H'FD9000 Access prohibited area H'FDC000 External address space H'FEC000 Reserved area* H'FF2000 On-chip RAM/ External address space* H'FFC000 External address ...
Page 126
Section 3 MCU Operating Modes Modes 1 and 2 User boot mode, boot mode (Advanced mode) H'000000 On-chip ROM H'060000 Access prohibited area H'100000 External address space reserved area H'FD9000 Access prohibited area H'FDC000 External address ...
Page 127
Mode 6 On-chip ROM enabled extended mode (Advanced mode) H'000000 On-chip ROM H'060000 Access prohibited area H'100000 External address space H'FD9000 Access prohibited area H'FDC000 External address space H'FEC000 Reserved area * H'FF2000 On-chip RAM/ External address space H'FFC000 External ...
Page 128
Section 3 MCU Operating Modes Rev. 2.00 Sep. 24, 2008 Page 94 of 1468 REJ09B0412-0200 ...
Page 129
Types of Resets There are three types of resets: a pin reset, power-on reset*, voltage-monitoring reset*, deep software standby reset, and watchdog timer reset. Table 4.1 shows the reset names and sources. The internal state and pins are initialized ...
Page 130
Section 4 Resets RES Vcc Power-on reset circuit* Voltage detection circuit* Deep software standby reset generation circuit Watchdog timer Note: * Supported only by the H8SX/1668M Group. Figure 4.1 Block Diagram of Reset Circuit Rev. 2.00 Sep. 24, 2008 Page ...
Page 131
Note that some registers are not initialized by any of the resets. The following describes the CPU internal registers. The PC, one of the CPU internal registers, is initialized by loading the start address from vector addresses with the reset ...
Page 132
Section 4 Resets 4.3 Register Descriptions This LSI has the following registers for resets. • Reset status register (RSTSR) • Reset control/status register (RSTCSR) 4.3.1 Reset Status Register (RSTSR) RSTSR indicates a source for generating an internal reset and voltage ...
Page 133
H8SX/1668R Group All 0 • H8SX/1668M Group 2 LVDF Undefined 1 — Undefined 0 PORF Undefined Notes: 1. Only 0 can be written to clear the flag. 2. Supported only by the H8SX/1668M Group. R/W ...
Page 134
Section 4 Resets 4.3.2 Reset Control/Status Register (RSTCSR) RSTCSR controls an internal reset signal generated by the watchdog timer and selects the internal reset signal type. RSTCSR is initialized to H’ pin reset or a deep software standby ...
Page 135
Pin Reset This is a reset generated by the RES pin. When the RES pin is driven low, all the processing in progress is aborted and the LSI enters a reset state. In order to firmly reset the LSI, ...
Page 136
Section 4 Resets 1 Vpor* External power supply Vcc RES pin Vcc POR signal Vcc ("L" is valid) V Reset signal V Vcc ("L" is valid) Pin reset and OR signal for POR Set V Vcc PORF Notes: For details ...
Page 137
Deep Software Standby Reset This is an internal reset generated when deep software standby mode is canceled by an interrupt. When deep software standby mode is canceled, a deep software standby reset is generated, and simultaneously, clock oscillation starts. ...
Page 138
Section 4 Resets 4.9 Determination of Reset Generation Source Reading RSTCSR, RSTSR, or LVDCR* of the voltage-detection circuit determines which reset was used to execute the reset exception handling. Figure 4.2 shows an example of the flow to identify a ...
Page 139
Section 5 Voltage Detection Circuit (LVD) The voltage detection circuit (LVD) is only supported by the H8SX/1668M Group. This circuit is used to monitor Vcc. The LVD is capable of internally resetting the LSI when Vcc falls and crosses the ...
Page 140
Section 5 Voltage Detection Circuit (LVD) 5.2 Register Descriptions The registers of the voltage detection circuit are listed below. • Voltage detection control register (LVDCR) • Reset status register (RSTSR) 5.2.1 Voltage Detection Control Register (LVDCR) The LVDCR controls the ...
Page 141
Bit Bit Name Initial Value 4 LVDMON — 0 5.2.2 Reset Status Register (RSTSR) RSTSR indicates the source of an internal reset or voltage monitoring interrupt. Bit 7 6 Bit name DPSRSTF — Initial value: 0 ...
Page 142
Section 5 Voltage Detection Circuit (LVD) Bit Bit Name Initial Value — All 0 2 LVDF Undefined 1 — Undefined 0 PORF Undefined Note clear the flag, only 0 should be written to. Rev. 2.00 ...
Page 143
Voltage Detection Circuit 5.3.1 Voltage Monitoring Reset Figure 5.2 shows the timing of a voltage monitoring reset by the voltage-detection circuit. When Vcc falls below Vdet in the state where the LVDE bit in LVDCR has been set to ...
Page 144
Section 5 Voltage Detection Circuit (LVD) 5.3.2 Voltage Monitoring Interrupt Figure 5.3 shows the timing of a voltage monitoring interrupt by the voltage-detection circuit. When Vcc falls below the Vdet in a state where the LVDE and LVDRI bits in ...
Page 145
Voltage monitoring interrupt (IRQ14) disabled Voltage detection and IRQ register settings If the flag has been set to 1 before the voltage-monitoring interrupt is enabled, clear it by writing 0 after having read Voltage-monitoring interrupt (IRQ14) enabled ...
Page 146
Section 5 Voltage Detection Circuit (LVD) 5.3.3 Release from Deep Software Standby Mode by the Voltage-Detection Circuit If the LVDE and LVDRI bits in LVDCR and the DLVDIE bit in DPSIER have all been set to 1 during a period ...
Page 147
Section 6 Exception Handling 6.1 Exception Handling Types and Priority As table 6.1 indicates, exception handling is caused by a reset, a trace, an address error, an interrupt, a trap instruction, a sleep instruction, and an illegal instruction (general illegal ...
Page 148
Section 6 Exception Handling 6.2 Exception Sources and Exception Handling Vector Table Different vector table address offsets are assigned to different exception sources. The vector table addresses are calculated from the contents of the vector base register (VBR) and vector ...
Page 149
Exception Source Reserved for system use User area (not used) External interrupt IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 IRQ8 IRQ9 IRQ10 IRQ11 Reserved for system use 4 Internal interrupt* Notes: 1. Lower 16 bits of the address. 2. ...
Page 150
Section 6 Exception Handling Table 6.3 Calculation Method of Exception Handling Vector Table Address Exception Source Calculation Method of Vector Table Address Reset, CPU address error Vector table address = (vector table address offset) Vector table address = VBR + ...
Page 151
Interrupts after Reset If an interrupt is accepted after a reset but before the stack pointer (SP) is initialized, the PC and CCR will not be saved correctly, leading to a program crash. To prevent this, all interrupt requests, ...
Page 152
Section 6 Exception Handling Bφ RES Address bus RD HWR, LWR D15 to D0 (1)(3) Reset exception handling vector address (when reset, (1) = H'000000, (3) = H'000002) (2)(4) Start address (contents of reset exception handling vector address) (5) Start ...
Page 153
Traces Traces are enabled in interrupt control mode 2. Trace mode is not activated in interrupt control mode 0, irrespective of the state of the T bit. Before changing interrupt control modes, the T bit must be cleared. For ...
Page 154
Section 6 Exception Handling 6.5 Address Error 6.5.1 Address Error Source Instruction fetch, stack operation, or data read/write shown in table 6.5 may cause an address error. Table 6.5 Bus Cycle and Address Error Bus Cycle Type Bus Master Instruction ...
Page 155
Bus Cycle Type Bus Master Data read/write EXDMAC Single address DMAC or transfer EXDMAC Notes: 1. For on-chip peripheral module space, see section 9, Bus Controller (BSC). 2. For the access prohibited area, refer to figure 3.1 in section 3.4, ...
Page 156
Section 6 Exception Handling When an address error occurs, the following is performed to halt the DTC, DMAC, and EXDMAC. • The ERR bit of DTCCR in the DTC is set to 1. • The ERRF bit of DMDR_0 in ...
Page 157
Interrupts 6.6.1 Interrupt Sources Interrupt sources are NMI, IRQ0 to IRQ11, and on-chip peripheral modules, as shown in table 6.7. Table 6.7 Interrupt Sources Type Source NMI NMI pin (external input) UBC break UBC break controller (UBC) interrupt Pins ...
Page 158
Section 6 Exception Handling The interrupt exception handling is as follows: 1. The contents of PC, CCR, and EXR are saved in the stack. 2. The interrupt mask bit is updated and the T bit is cleared ...
Page 159
Sleep Instruction Exception Handling The sleep instruction exception handling starts when a sleep instruction is executed with the SSBY bit in SBYCR set to 0 and the SLPIE bit in SBYCR set to 1. The sleep instruction exception handling ...
Page 160
Section 6 Exception Handling 6.7.3 Exception Handling by Illegal Instruction The illegal instructions are general illegal instructions and slot illegal instructions. The exception handling by the general illegal instruction starts when an undefined code is executed. The exception handling by ...
Page 161
Stack Status after Exception Handling Figure 6.3 shows the stack after completion of exception handling. Advanced mode SP Interrupt control mode 0 Note: * Ignored on return. Figure 6.3 Stack Status after Exception Handling SP CCR PC (24 bits) ...
Page 162
Section 6 Exception Handling 6.9 Usage Note When performing stack-manipulating access, this LSI assumes that the lowest address bit is 0. The stack should always be accessed by a word transfer instruction or a longword transfer instruction, and the value ...
Page 163
Section 7 Interrupt Controller 7.1 Features • Two interrupt control modes Any of two interrupt control modes can be set by means of bits INTM1 and INTM0 in the interrupt control register (INTCR). • Priority can be assigned by the ...
Page 164
Section 7 Interrupt Controller A block diagram of the interrupt controller is shown in figure 7.1. INTCR NMI input IRQ11 to 0 input TM32K IRQ15 input LVD* IRQ14 input Internal interrupt sources WOVI to RESUME [Legend] INTCR: Interrupt control register ...
Page 165
Input/Output Pins Table 7.1 shows the pin configuration of the interrupt controller. Table 7.1 Pin Configuration Name I/O NMI Input IRQ11 to IRQ0 Input 7.3 Register Descriptions The interrupt controller has the following registers. • Interrupt control register (INTCR) ...
Page 166
Section 7 Interrupt Controller 7.3.1 Interrupt Control Register (INTCR) INTCR selects the interrupt control mode, and the edge to detect NMI. Bit 7 6 Bit Name Initial Value Initial Bit Bit Name Value ...
Page 167
CPU Priority Control Register (CPUPCR) CPUPCR sets whether or not the CPU has priority over the DTC, DMAC and EXDMAC. The interrupt exception handling by the CPU can be given priority over that of the DTC, DMAC and EXDMAC ...
Page 168
Section 7 Interrupt Controller Initial Bit Bit Name Value 3 IPSETE 0 2 CPUP2 0 1 CPUP1 0 0 CPUP0 0 Note: * When the IPSETE bit is set to 1, the CPU priority is automatically updated, so these bits ...
Page 169
Interrupt Priority Registers and R (IPRA to IPRO, IPRQ, and IPRR) IPR sets priory (levels for interrupts other than NMI. Setting a value in the range from B'000 to B'111 in the ...
Page 170
Section 7 Interrupt Controller Initial Bit Bit Name Value 10 IPR10 1 9 IPR9 1 8 IPR8 1 IPR6 1 5 IPR5 1 4 IPR4 1 IPR2 1 1 IPR1 1 0 ...
Page 171
IRQ Enable Register (IER) IER enables interrupt requests IRQ15, IRQ14, and IRQ11 to IRQ0. Bit 15 14 Bit Name IRQ15E IRQ14E* Initial Value 0 0 R/W R/W R/W Bit 7 6 Bit Name IRQ7E IRQ6E Initial Value 0 0 ...
Page 172
Section 7 Interrupt Controller Initial Bit Bit Name Value 7 IRQ7E 0 6 IRQ6E 0 5 IRQ5E 0 4 IRQ4E 0 3 IRQ3E 0 2 IRQ2E 0 1 IRQ1E 0 0 IRQ0E 0 Note: Supported only by the H8SX/1668M Group. ...
Page 173
ISCRH Bit 15 14 Bit Name IRQ15SR IRQ15SF Initial Value 0 0 R/W R/W R/W Bit 7 6 Bit Name IRQ11SR IRQ11SF Initial Value 0 0 R/W R/W R/W • ISCRL Bit 15 14 Bit Name IRQ7SR IRQ7SF Initial ...
Page 174
Section 7 Interrupt Controller Initial Bit Bit Name Value 13 IRQ14SR* 0 IRQ14SF All 0 7 IRQ11SR 0 6 IRQ11SF 0 5 IRQ10SR 0 4 IRQ10SF 0 Rev. 2.00 Sep. 24, 2008 Page 140 ...
Page 175
Initial Bit Bit Name Value 3 IRQ9SR 0 2 IRQ9SF 0 1 IRQ8SR 0 0 IRQ8SF 0 Note: * Supported only by the H8SX/1668M. R/W Description R/W IRQ9 Sense Control Rise R/W IRQ9 Sense Control Fall 00: Interrupt request generated ...
Page 176
Section 7 Interrupt Controller • ISCRL Initial Bit Bit Name Value 15 IRQ7SR 0 14 IRQ7SF 0 13 IRQ6SR 0 12 IRQ6SF 0 11 IRQ5SR 0 10 IRQ5SF 0 9 IRQ4SR 0 8 IRQ4SF 0 7 IRQ3SR 0 6 IRQ3SF ...
Page 177
Initial Bit Bit Name Value 5 IRQ2SR 0 4 IRQ2SF 0 3 IRQ1SR 0 2 IRQ1SF 0 1 IRQ0SR 0 0 IRQ0SF 0 R/W Description R/W IRQ2 Sense Control Rise IRQ2 Sense Control Fall R/W 00: Interrupt request generated by ...
Page 178
Section 7 Interrupt Controller 7.3.6 IRQ Status Register (ISR) ISR is an IRQ15, IRQ14, and IRQ11 to IRQ0 interrupt request register. Bit 15 14 Bit Name IRQ15F IRQ14F* Initial Value 0 0 R/W R/(W)* 1 R/(W)* Bit 7 6 Bit ...
Page 179
Initial Bit Bit Name Value 11 IRQ11F 0 10 IRQ10F 0 9 IRQ9F 0 8 IRQ8F 0 7 IRQ7F 0 6 IRQ6F 0 5 IRQ5F 0 4 IRQ4F 0 3 IRQ3F 0 2 IRQ2F 0 1 IRQ1F 0 0 IRQ0F ...
Page 180
Section 7 Interrupt Controller Initial Bit Bit Name Value 15 SSI15 0 All 0 11 SSI11 0 10 SSI10 0 9 SSI9 0 8 SSI8 0 7 SSI7 0 6 SSI6 0 5 SSI5 0 4 ...
Page 181
Interrupt Sources 7.4.1 External Interrupts There are thirteen external interrupts: NMI and IRQ11 to IRQ0. These interrupts can be used to leave software standby mode. (1) NMI Interrupts Nonmaskable interrupt request (NMI) is the highest-priority interrupt, and is always ...
Page 182
Section 7 Interrupt Controller Detection of IRQn interrupts is enabled through the P1ICR, P2ICR, and P5ICR register settings, and does not change regardless of the output setting. However, when a pin is used as an external interrupt input pin, the ...
Page 183
Interrupt Exception Handling Vector Table Table 7.2 lists interrupt exception handling sources, vector address offsets, and interrupt priority. In the default priority order, a lower vector number corresponds to a higher priority. When interrupt control mode 2 is set, ...
Page 184
Section 7 Interrupt Controller Vector Classification Interrupt Source Number Reserved for 80 system use WDT WOVI 81 Reserved for 82 system use Refresh CMI 83 controller Reserved for 84 system use 85 A/D_0 ADI0 86 Reserved ...
Page 185
Vector Classification Interrupt Source Number TPU_4 TGI4A 106 TGI4B 107 TCI4V 108 TCI4U 109 TPU_5 TGI5A 110 TGI5B 111 TCI5V 112 TCI5U 113 Reserved for 114 system use 115 TMR_0 CMI0A 116 CMI0B 117 OV0I 118 TMR_1 CMI1A 119 ...
Page 186
Section 7 Interrupt Controller Vector Classification Interrupt Source Number EXDMAC EXDMTEND0 132 EXDMTEND1 133 EXDMTEND2 134 EXDMTEND3 135 DMAC DMEEND0 136 DMEEND1 137 DMEEND2 138 DMEEND3 139 EXDMAC EXDMEEND0 140 EXDMEEND1 141 EXDMEEND2 142 EXDMEEND3 143 SCI_0 ERI0 144 RXI0 ...
Page 187
Vector Classification Interrupt Source Number SCI_4 ERI4 160 RXI4 161 TXI4 162 TEI4 163 TPU_6 TGI6A 164 TGI6B 165 TGI6C 166 TGI6D 167 TCI6V 168 TPU_7 TGI7A 169 TGI7B 170 TGI7V 171 TCI7U 172 TPU_8 TGI8A 173 TGI8B 174 TCI8V ...
Page 188
Section 7 Interrupt Controller Vector Classification Interrupt Source Number TPU_11 TGI11A 188 TGI11B 189 TCI11V 190 TCI11U 191 Reserved for 192 system use | 215 IIC2_0 IICI0 216 Reserved for 217 system use IIC2_1 IICI1 218 Reserved ...
Page 189
Vector Classification Interrupt Source Number USB USBINTN0 232 USBINTN1 233 USBINTN2 234 USBINTN3 235 Reserved for 236 system use A/D_1 ADI1 237 USB resume 238 Reserved for 239 system use | 255 Notes: 1. Lower 16 bits of ...
Page 190
Section 7 Interrupt Controller 7.6 Interrupt Control Modes and Interrupt Operation The interrupt controller has two interrupt control modes: interrupt control mode 0 and interrupt control mode 2. Interrupt operations differ depending on the interrupt control mode. The interrupt control ...
Page 191
The CPU generates a vector address for the accepted interrupt and starts execution of the interrupt handling routine at the address indicated by the contents of the vector address in the vector table. IRQ0 Figure 7.3 Flowchart of Procedure ...
Page 192
Section 7 Interrupt Controller 7.6.2 Interrupt Control Mode 2 In interrupt control mode 2, interrupt requests except for NMI are masked by comparing the interrupt mask level ( bits) in EXR of the CPU and the IPR setting. ...
Page 193
Program execution state Interrupt generated? Yes No Level 7 interrupt? Yes Level 6 interrupt? No Mask level 6 or below? Yes Mask level 5 Save PC, CCR, and EXR Clear T bit to 0 Update mask level Read vector address ...
Page 194
Section 7 Interrupt Controller 7.6.3 Interrupt Exception Handling Sequence Figure 7.5 shows the interrupt exception handling sequence. The example is for the case where interrupt control mode 0 is set in maximum mode, and the program area and stack area ...
Page 195
Interrupt Response Times Table 7.4 shows interrupt response times – the interval between generation of an interrupt request and execution of the first instruction in the interrupt handling routine. The symbols for execution states used in table 7.4 are ...
Page 196
Section 7 Interrupt Controller Table 7.5 Number of Execution States in Interrupt Handling Routine On-Chip Symbol Memory Vector fetch Instruction fetch Stack manipulation [Legend] m: Number of wait cycles in an ...
Page 197
Figure 7.6 shows a block diagram of the DTC, DMAC and interrupt controller. Interrupt request DMAC On-chip select peripheral circuit Interrupt request module clear signal Interrupt request IRQ Interrupt request interrupt clear signal Interrupt controller Figure 7.6 Block Diagram of ...
Page 198
Section 7 Interrupt Controller to the DTCP and DMAP setting. If the CPU is given priority over the DTC or DMAC, the DTC or DMAC may not be activated, and the data transfer may not be performed. (2) Priority Determination ...
Page 199
To initiate multiple channels for the DTC and DMAC with the same interrupt, the same priority (DTCP = DMAP) should be assigned. 7.7 CPU Priority Control Function Over DTC, DMAC and EXDMAC The interrupt controller has a function to control ...
Page 200
Section 7 Interrupt Controller the condition that has held the activation source is cancelled (CPUPCE = 1 and the value of the bits CPUP2 to CPUP0 is greater than that of the bits EDMAP2 to EDMAP0). When different priority level ...