M30626FJPFP#U5C Renesas Electronics America, M30626FJPFP#U5C Datasheet - Page 287

IC M16C MCU FLASH 512K 100QFP

M30626FJPFP#U5C

Manufacturer Part Number
M30626FJPFP#U5C
Description
IC M16C MCU FLASH 512K 100QFP
Manufacturer
Renesas Electronics America
Series
M16C™ M16C/60r
Datasheets

Specifications of M30626FJPFP#U5C

Core Processor
M16C/60
Core Size
16-Bit
Speed
24MHz
Connectivity
I²C, IEBus, UART/USART
Peripherals
DMA, WDT
Number Of I /o
85
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
31K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 26x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
100-QFP
For Use With
867-1000 - KIT QUICK START RENESAS 62PR0K33062PS001BE - R0K33062P STARTER KITR0K33062PS000BE - KIT EVAL STARTER FOR M16C/62PM3062PT3-CPE-3 - EMULATOR COMPACT M16C/62P/30P
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

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6
Figure 6.1.5. When executing an instruction to transfer data between even addresses starting from an even address
Figure 6.1.6. When executing an instruction to read from even addresses starting from an even address
Instructions
under execution
Fetch code
Instruction
queue buffer
Address bus
Data bus (L)
RD
BCLK
Data bus (H)
WR
Instructions
under execution
Address bus
Fetch code
Instruction
queue buffer
BCLK
Data bus (H)
Data bus (L)
RD
WR
DW : Indicates a data write.
DR : Indicates a data read.
P : Indicates a prefetch (reading from memory into the instruction queue buffer).
DW : Indicates a data write.
DR : Indicates a data read.
: Indicates the locations of the instruction queue buffer that are cleared.
P : Indicates a prefetch (reading from memory into the instruction queue buffer).
: Indicates the locations of the instruction queue buffer that are cleared.
Content at jump address is
prefetched at the same time
the instruction queue buffer
is cleared.
Content at jump address is
prefetched at the same time
the instruction queue buffer
is cleared.
Jump address
64
04
04
04
04
04
04
64
(Program area: 16-bit bus without wait state; Data area: 16-bit bus with wait state)
(Program area: 16-bit bus without wait state; Data area: 16-bit bus without wait state)
FC06E
Jump address
FC152
04
04
04
04
04
04
JMP
JMP
TEST_11
04
04
04
TEST_11
04
04
04
Address from which
to read data
Address from which to read data
FC072
FC156
73
FF
73
73
73
F1
P
FF
73
F1
73
P
Fetch
FC074
Fetch
FC158
FF
73
00
40
73
F1
00
40
P
40
00
40
00
P
FC076
Fetch
73FF
Fetch
00
40
02
40
FC15A
73F1
02
00
40
64
04
40
P
64
04
P
MOV.W
04000
0040
Fetch
02
40
0040
DR
AA
AA
64
04
MOV.W
04000
04002
0240
DR
The instruction
queue buffer is
emptied, so one
more cycle is waited.
AA
AA
Content at address 4001
Content at address 4000
DW
AA
AA
64
04
Address from which to write data
1 wait
0FC078
64
04
Fetch
04
64
P
64
04
04
04
Content at address 4001
Content at address 4000
04
04
P
64
04
04
04
Fetch
269
04
04
P
64
04
04
04
Content at jump address is prefetched at
the same time the instruction queue buffer
is cleared.
FC15C
64
04
04
04
FC07A
16
16
04
04
04
Content at jump address is
prefetched at the same time
the instruction queue buffer is
cleared.
JMP
04
04
04
JMP
04
04
04
TEST_12
16
16
TEST_12
04
04
04
FC160
FF
73
FC07E
73
FF
P
73
F1
F1
73
P
FC162
FF
73
00
40
FC080
00
40
73
F1
00
40
P
00
40
Calculation number of cycles
P
Sample program
Address
FC06C
FC06D
FC06E
FC06F
FC070
FC071
FC072
FC072
FC078
FC079
FC07A
FC07B
FC07C
FC07D
FC07E
Sample program
Address
FC150
FC151
FC152
FC153
FC154
FC155
FC156
FC156
FC15A
FC15B
FC15C
FC15D
FC15E
FC15F
FC160
Code
64
04
04
04
04
04
73FF00400240 MOV.W
64
04
04
04
04
04
6.1 Instruction queue buffer
TEST_11:
TEST_12:
Code
64
04
04
04
04
04
73F10040
64
04
04
04
04
04
TEST_11:
TEST_12:
Instruction
JMP
NOP
NOP
NOP
NOP
NOP
JMP
NOP
NOP
NOP
NOP
NOP
Instruction
JMP
NOP
NOP
NOP
NOP
NOP
MOV.W 04000h, R1
JMP
NOP
NOP
NOP
NOP
NOP
TEST_11
04000h, 04002h
TEST_12
TEST_11
TEST_12

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