M30626FJPFP#U5C Renesas Electronics America, M30626FJPFP#U5C Datasheet - Page 288

• Manufacturer Part Number: M30626FJPFP#U5C
• Description: IC M16C MCU FLASH 512K 100QFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/60r

Specifications of M30626FJPFP#U5C

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 24MHz
• Connectivity: I²C, IEBus, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 85
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 31K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 26x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-QFP
• For Use With: 867-1000 - KIT QUICK START RENESAS 62PR0K33062PS001BE - R0K33062P STARTER KITR0K33062PS000BE - KIT EVAL STARTER FOR M16C/62PM3062PT3-CPE-3 - EMULATOR COMPACT M16C/62P/30P
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

6
Figure 6.1.7. When executing a read instruction for memory connected to 8-bit bus
Figure 6.1.8. When executing a read instruction for memory connected to 8-bit bus
Instructions
under execution
Fetch code
Instruction
queue buffer
BCLK
Address bus
Data bus (H)
Data bus (L)
RD
WR
Instructions
under execution
Fetch code
Instruction
queue buffer
BCLK
Address bus
Data bus (H)
Data bus (L)
RD
WR
DW : Indicates a data write.
DR : Indicates a data read.
DW : Indicates a data write.
P : Indicates a prefetch (reading from memory into the instruction queue buffer).
DR : Indicates a data read.
P : Indicates a prefetch (reading from memory into the instruction queue buffer).
: Indicates the locations of the instruction queue buffer that are cleared.
: Indicates the locations of the instruction queue buffer that are cleared.
Content at jump address is
prefetched at the same time
the instruction queue buffer
is cleared.
Content at jump address is
prefetched at the same time
the instruction queue buffer
is cleared.
64
04
04
04
64
04
04
04
(Program area: 16-bit bus without wait state; Data area: 8-bit bus without wait state)
Jump address
(Program area: 8-bit bus without wait state; Data area: 8-bit bus without wait state)
Jump address
FC065
FC05A
04
04
04
04
04
04
JMP
JMP
04
04
04
TEST_11
04
04
04
TEST_11
FC068
Low-order address from
which to read data
73
Content at address 4000
FC05E
73
P
73
73
F1
F1
P
73
FC069
Fetch
73
F1
FC060
F1
P
73
F1
00
40
Fetch
FC06A
P
40
00
73
F1
00
Fetch
FC062
00
P
73F1
00
40
64
04
Low-order address from
which to read data
FC06B
64
73F1
04
P
00
40
16
40
P
04000
0040
Content at address 4000
64
04
FC06C
MOV.W
DR
AA
00
40
64
64
P
04001
Fetch
64
04
FC06D
AA
DR
00
40
64
04
04
MOV.W
High-order address from
which to read data
P
Fetch
64
04
04
04
Content at address 4001
0040
04000
64
04
04
04
P
DR
AA
16
04001
64
04
04
04
64
04
270
Content at jump address is prefetched
at the same time the instruction queue
buffer is cleared.
DR
AA
FC064
High-order address from
which to read data
FC06E
Fetch
Content at address 4001
04
04
04
64
04
04
JMP
04
P
16
04
04
04
64
04
04
04
TEST_12
04
P
Content at jump address is prefetched
at the same time the instruction queue
buffer is cleared.
FC06F
FC068
04
04
04
73
FF
FF
73
P
JMP
16
FC06A
04
04
04
FF
73
00
40
00
40
TEST_12
P
FC072
73
73
P
Calculation number of cycles
FC073
FF
73
Sample program
Address
FC058
FC059
FC05A
FC05B
FC05C
FC05D
FC05E
FC05E
FC062
FC063
FC064
FC065
FC066
FC067
FC068
FF
P
FC074
FF
73
00
00
P
Code
64
04
04
04
04
04
73F10040
64
04
04
04
04
04
Sample programs
Address
FC062
FC063
FC064
FC065
FC066
FC067
FC068
FC068
FC06C
FC06D
FC06E
FC06F
FC070
FC071
FC072
6.1 Instruction queue buffer
TEST_11:
TEST_12:
Code
64
04
04
04
04
04
73F10040
64
04
04
04
04
04
TEST_11:
TEST_12:
Instruction
JMP
NOP
NOP
NOP
NOP
NOP
MOV.W
JMP
NOP
NOP
NOP
NOP
NOP
Instruction
JMP
NOP
NOP
NOP
NOP
NOP
MOV.W 04000h, R1
JMP
NOP
NOP
NOP
NOP
NOP
04000h, R1
TEST_12
TEST_11
TEST_11
TEST_12