M30626FJPFP#U5C Renesas Electronics America, M30626FJPFP#U5C Datasheet - Page 103

• Manufacturer Part Number: M30626FJPFP#U5C
• Description: IC M16C MCU FLASH 512K 100QFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/60r

Specifications of M30626FJPFP#U5C

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 24MHz
• Connectivity: I²C, IEBus, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 85
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 31K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 26x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-QFP
• For Use With: 867-1000 - KIT QUICK START RENESAS 62PR0K33062PS001BE - R0K33062P STARTER KITR0K33062PS000BE - KIT EVAL STARTER FOR M16C/62PM3062PT3-CPE-3 - EMULATOR COMPACT M16C/62P/30P
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M16C/62P Group (M16C/62P, M16C/62PT)
Rev.2.41
REJ09B0185-0241
Figure 10.4
Oscillation Stop Detection Register
b7 b6 b5 b4
NOTES :
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
0 0
Rew rite this register after setting the PRC0 bit in the PRCR register to “1” (w rite enable).
When the CM20 bit is set to “1” (oscillation stop, re-oscillation detection function enabled), the CM27 bit is set to “1”
(oscillation stop, re-oscillation detection interrupt), and the CPU clock source is the main clock, the CM21 bit is set to
“1” (on-chip oscillator clock) if the main clock stop is detected.
If the CM20 bit is set to “1” and the CM23 bit is set to “1” (main clock stops), do not set the CM21 bit to “0”.
This bit is set to “1” w hen the main clock stop is detected and the main clock re-oscillation is detected. When this
flag changes state from “0” to “1”, an oscillation stop or a re-oscillation detection interrupt is generated. Use this bit in
an interrupt routine to determine the factors of interrupts betw een the oscillation stop and re-oscillation detection
interrupt and the w atchdog timer interrupt. This bit is set to “0” by w riting “0” in a program. (This bit remains
unchanged even if w riting “1”. Nor is it set to “0” w hen an oscillation stop or a re-oscillation detection interrupt
request is acknow ledged.)
When the CM22 bit is set to “1” and an oscillation stop or a re-oscillation is detected, an oscillation stop or a re-
oscillation detection interrupt is not generated.
Determine the main clock status by reading the CM23 bit several times in an oscillation stop or a re-oscillation
detection interrupt routine
This bit is valid w hen the CM07 bit in the CM0 register is set to “0”.
When the PM21 bit in the PM2 register is set to “1” (disable clock modification), this bit remains unchanged even if
w riting to the CM20 bit.
Where the CM20 bit is set to “1” (oscillation stop, re-oscillation detection function enabled), the CM27 bit is “1”
(oscillation stop, re-oscillation detection interrupt), and the CM11 bit is set to “1” (PLL clock is selected as the CPU
clock source), the CM21 bit remains unchanged even if a main clock stop is detected. When the CM22 bit is set to
“0” under these conditions, an oscillation stop, a re-oscillation detection interrupt request is generated at main clock
stop detection. Set the CM21 bit to “1” (on-chip oscillator clock) in the interrupt routine.
Set the CM20 bit to “0” (disabled) before entering stop mode. Exit stop mode before setting the CM20 bit back to “1”
(enabled).
Set the CM20 bit in the CM2 register to “0” (disabled) before setting the CM05 bit in the CM0 register to “1” (main clock
stops).
The CM20, CM21 and CM27 bits remain unchanged at the oscillation stop detection reset.
When the CM21 bit is set to “0” (on-chip oscillator stops) and the CM05 bit is set to “1” (main clock stops), the CM06
bit is fixed to “1” (divide-by-8 mode) and the CM15 bit is fixed to “1” (drive capacity High).
Jan 10, 2006
b3 b2 b1 b0
CM2 Register
Bit Symbol
(b5-b4)
Symbol
CM20
CM21
CM22
CM23
CM27
CM2
(b6)
Page 86 of 390
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Oscillation Stop,
Re-Oscillation Detection
Enable Bit
System Clock Select Bit 2
(2, 3, 6, 8, 11, 12)
Oscillation Stop,
Re-Oscillation Detection
Flag
XIN Monitor Flag
Reserved Bit
Nothing is assigned. When w rite, set to “0”.
When read, its content is “0”.
Operation Select Bit
(w hen an oscillation stop,
re-oscillation is detected)
(4)
(1)
(7, 9, 10,11)
Address
Bit Name
000Ch
(5)
(11)
0: Oscillation stop, re-oscillation detection
1: Oscillation stop, re-oscillation detection
0: Main clock or PLL clock
1: On-chip oscillator clock
0: Main clock stops, re-oscillation not
1: Main clock stops, re-oscillation detected
0: Main clock oscillates
1: Main clock stops
Set to “0”
0: Oscillation stop detection reset
1: Oscillation stop, re-oscillation detection
function disabled
function enabled
(On-chip oscillator oscillates)
detected
interrupt
0X000000b
After Reset
Function
10. Clock Generation Circuit
(11)
RW
RW
RW
RW
RW
RW
RO
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