M30626FJPFP#U5C Renesas Electronics America, M30626FJPFP#U5C Datasheet - Page 220

• Manufacturer Part Number: M30626FJPFP#U5C
• Description: IC M16C MCU FLASH 512K 100QFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/60r

Specifications of M30626FJPFP#U5C

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 24MHz
• Connectivity: I²C, IEBus, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 85
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 31K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 26x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-QFP
• For Use With: 867-1000 - KIT QUICK START RENESAS 62PR0K33062PS001BE - R0K33062P STARTER KITR0K33062PS000BE - KIT EVAL STARTER FOR M16C/62PM3062PT3-CPE-3 - EMULATOR COMPACT M16C/62P/30P
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M16C/62P Group (M16C/62P, M16C/62PT)
Rev.2.41
REJ09B0185-0241
Figure 17.22
Figure 17.23
17.1.2.4
17.1.2.5
The data written to the UiTB register has its logic reversed before being transmitted. Similarly, the received
data has its logic reversed when read from the UiRB register. Figure 17.22 shows Serial Data Logic Switching.
This function inverses the polarities of the TXDi pin output and RXDi pin input. The logic levels of all input/
output data (including the start, stop and parity bits) are inversed. Figure 17.23 shows the TXD and RXD I/O
Polarity Inverse.
(1) When the UiLCH bit in the UiC1 Register = 0 (No Reverse)
(2) When the UiLCH Bit = 1 (Reverse)
NOTES :
(1) When the IOPOL Bit in the UiMR Register = 0 (No Reverse)
(2) When the IOPOL Bit = 1 (Reverse)
NOTES :
Transfer Clock
Jan 10, 2006
Transfer Clock
(No Reverse)
Transfer Clock
Transfer Clock
1. This applies to the case where the CKPOL bit in the UiC0 register = 0
1. This applies to the case where the UFORM bit in the UiC0 register = 0
(No Reverse)
(No Reverse)
(Reverse)
(transmit data output at the falling edge of the transfer clock),
the UFORM bit in the UiC0 register = 0 (LSB first),
the STPS bit in the UiMR register = 0 (1 stop bit) and
the PRYE bit in the UiMR register = 1 (parity enabled).
(LSB first), the STPS bit in the UiMR register = 0 (1 stop bit) and the
PRYE bit in the UiMR register = 1 (parity enabled).
(Reverse)
(Reverse)
Serial Data Logic Switching Function
TXD and RXD I/O Polarity Inverse Function
TXD and RXD I/O Polarity Inverse
Serial Data Logic Switching
TXDi
TXDi
RXDi
RXDi
TXDi
TXDi
“H”
“H”
“H”
“H”
“H”
“L”
“H”
“H”
“L”
“L”
“L”
“L”
“L”
“L”
“H”
“L”
“H”
“H”
“L”
“L”
Page 203 of 390
ST
ST
ST
ST
ST
ST
D0
D0
D0
D0
D0
D0
D1
D1
D1
D1
D1
D1
D2
D2
D2
D2
D2
D2
D3
D3
D3
D3
D3
D3
D4
D4
D4
D4
D4
D4
D5
D5
D5
D5
D5
D5
D6
D6
D6
D6
D6
D6
D7
D7
D7
D7
D7
D7
P
P
P
P
P
P
SP
SP
SP
SP
SP
SP
ST : Start bit
P : Parity bit
SP : Stop bit
i = 0 to 2
ST : Start bit
P : Parity bit
SP : Stop bit
i = 0 to 2
17. Serial Interface